Sync clock about MCASP

user6000372

Hi,

Our project is based on DRA78x,SDK is pdk4.3.05.

in our project,mcasp1 has 2 serial, and each seraial has 8 slots.we use internal bit clock and sync clock.now,the bit clock is 12.288M,and the sync clock is 48k,I think the sync clock is wrong,it should be 192k(48k*8),is it right?

Could you tell me how to config the register to generate 192k sync clock? the below is my configuration,please help me to check it?

The clock source is 24.576M.

#define RX_NUM_SERIALIZER (1u)
#define TX_NUM_SERIALIZER (2u)

static Mcasp_HwSetupData mcasp0RcvSetup = {
    /* .rmask    = */
    0xFFFFFFFF,                   /* All the data bits are to be used     */
    /* .rfmt     = */ 0x000180F0, /* 0/1 bit delay from framsync
                                   * MSB first
                                   * No extra bit padding
                                   * Padding bit (ignore)
                                   * slot Size is 32
                                   * Reads from DMA port
                                   * NO rotation
                                   */

    /* .afsrctl = */ 0x00000111, /* I2S mode,
                                   * Frame sync is one word
                                   * External generated frame sync
                                   * Falling edge is start of frame
                                   */

    /* .rtdm     = */ 0x00000003, /* 2 slots are active (I2S)           */
    /* .rintctl = */ 0x00000003, /* sync error and overrun error       */
    /* .rstat    = */ 0x000001FF, /* reset any existing status bits     */
    /* .revtctl = */ 0x00000000, /* DMA request is enabled or disabled */
    {
        /* .aclkrctl = */ 0x000000C0, /* Div (8), ASync mode,Externel Source, falling edge */
        /* .ahclkrctl = */ 0x00000000, /* Div (20), Internal AUX_CLK Source     */
        /* .rclkchk   = */ 0x00000000
    }
};

static Mcasp_HwSetupData mcasp0XmtSetup = {
    /* .xmask    = */
    0xFFFFFFFF,                   /* All the data bits are to be used     */
    /* .xfmt     = */ 0x000080F0, /* 0/1 bit delay from framsync
                                   * MSB first
                                   * No extra bit padding
                                   * Padding bit (ignore)
                                   * slot Size is 32
                                   * Reads from DMA port
                                   * 0-bit rotation
                                   */

    /* .afsxctl = */ 0x00000402, /* TDM mode,
                                   * Frame sync is one bit
                                   * internally generated frame sync
                                   * Rising edge is start of frame
                                   */

    /* .xtdm     = */ 0x00000008, /* 8 slots are active (TDM) */
    /* .xintctl = */ 0x00000003, /* sync error,overrun error,clK error   */
    /* .xstat    = */ 0x000001FF, /* reset any existing status bits       */
    /* .xevtctl = */ 0x00000000, /* DMA request is enabled or disabled   */
    {
        /* .aclkxctl = */ 0x000000A1, /* Div (a78), Internal Source, SYNC, Falling edge */
        /* .ahclkxctl = */ 0x00000000, /* Div (20), Internal AUX_CLK Source */
        /* .xclkchk   = */ 0x00000000
    },
};

/* McAsp channel parameters                                  */
Mcasp_ChanParams mcasp_chanparam_test[2] = {
    {
        RX_NUM_SERIALIZER,                    /* number of serialisers      */
        {Mcasp_SerializerNum_3}, /* serialiser index */
        &mcasp0RcvSetup,
        TRUE,
        Mcasp_OpMode_TDM,          /* Mode (TDM/DIT)             */
        Mcasp_WordLength_32,
        NULL,
        0,
        NULL,
        (Mcasp_GblCallback)&GblErrRcvTest,
        2, /* number of TDM channels      */
        Mcasp_BufferFormat_1SER_MULTISLOT_INTERLEAVED,
        TRUE,
        RX_FIFO_EVENT_DMA_RATIO,
        TRUE,
        Mcasp_WordBitsSelect_LSB
    },
    {
        TX_NUM_SERIALIZER,                   /* number of serialisers       */
  {Mcasp_SerializerNum_8, Mcasp_SerializerNum_9},
        &mcasp0XmtSetup,
        TRUE,
        Mcasp_OpMode_TDM,
        Mcasp_WordLength_32,      /* word width                  */
        NULL,
        0,
        NULL,
        (Mcasp_GblCallback)&GblErrXmtTest,
        8, /* number of TDM channels      */
        Mcasp_BufferFormat_MULTISER_MULTISLOT_SEMI_INTERLEAVED_1,
        TRUE,
        TX_FIFO_EVENT_DMA_RATIO,
        TRUE,
        Mcasp_WordBitsSelect_LSB
    }
};

Many thanks,

He Weibing

over 5 years ago