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AM5746: DMA questions

rei
Mastermind 6155 points
Part Number: AM5746
Other Parts Discussed in Thread: SYSBIOS

My customers have two questions about DMA.

1.
To the source or destination address of the DMA descriptor (PaRAM), If the 0x0 address is specified by mistake, it will end abnormally.

They hope,
In the case of areas that cannot be sent, we just want to report errors and continue processing.
Are there such functions?

2.
Currently, only the last descriptor receives a completion interrupt, and all necessary transfer requests are made simultaneously.
In this case, if a request is made to transfer a high priority channel after a low priority channel transfer,
Priority arbitration is not possible.
How can we mediate using the above transfer method?

dma_2.pdf

AM574x
CCS v8
GCC GNU v6.3.1(Linaro)
HW IDK574xEVM
SW pdk_am57xx_1_0_11
bios_6_76_00_08
XDCTools 3.50.3.33

Regards,

Rei

  • 0
    TI__Guru* 95265 points

    Hi,

    For Q1, "If the 0x0 address is specified by mistake, it will end abnormally.". What do you mean? The program abort? exception? This runs on A15? Do you enable the MMU for the region for the wrong address 0x0? Do you use SYSBIOS? By default, the first 1GB (0x0000_0000 to 0x4000_0000) MMU is not enabled in SYSBIOS. 

    For Q2, you:

    • used only one channel for linked transfer
    • the PaRAM set is linked for total 256 groups
    • Then you have another channel starts transfer, this channel is suppose to have higher priority, but you think it is blocked due to the 256 linked low priority transfer is in progress

    The solution is to have the two channels submit to different EDMA transfer controllers (TC0 and TC1). 

    Regards, Eric

  • 0 in reply to lding
    Mastermind 6155 points

    Hi Eric,
    Thank you for your reply. I send your comments to customers. However, they have questions.

    Q1 -> Change the question.
    Q1-1. Could you tell me how to use Memory Protection in edma3_lld?
    Please let me know if you have any example code.

    Q1-2. If EDMA transfer requests are made to access-prohibited area, it will be exception. Can we detect anomalies using Memory Protection or TPCC Event Missed Register?

    Q2 -> The solution is to have the two channels submit to different EDMA transfer controllers (TC0 and TC1).
    Q2-1.
    They want to interrupt during transfer with EDMA. Is there only a way to do it between TC0 and TC1? In other words, we can only mediate at 2 levels. They hope to set 8 priorities during EDMA transfers.

    Q2-2.
    Are TC0 and TC1 the argument of EDMA3_DRV_open (phyCtrllerInstId)?

    Q2-3.
    They hope to interrupt 8 high priority transfers during EDMA transfer.
    Please let me know if you have any implementation method or example source code.

    Sorry for the many questions.

    Regards, Rei

  • 0 in reply to rei
    TI__Guru* 95265 points

    Hi,

    You used GCC GNU v6.3.1(Linaro), it means you do EDMA on A15 core. 

    Q1-1. Could you tell me how to use Memory Protection in edma3_lld? ======> I need to double check how memory protection worked.

    Q1-2. Certainly you will see EMR set and you can also check ERRSTAT and ERRDET registers, for memory protection I need to check.

    Q2-1. EDMA priority is set at QUEPRI register, the priority is per TC with 8 levels. For the same TC, all the transfers have the same transfer priority. You can set up different queues with different level and the priority is arbitrated at the system level. For the transfer submitted to the same TC, the latter submitted ones have to wait for the previous one to finish.

    Q2-2. No, EDMA3_DRV_open uses the EDMA CC instance number, not the TC. 

    Q2-3, EDMA can generate intermediate or complete transfer interrupt to CPU. All the examples are under edma3_lld_2_12_05_30x\examples\edma3_driver\src.

    Regards, Eric

  • 0 in reply to lding
    Mastermind 6155 points

    Hi Eric,

    Thank you for your reply. Please investigate Q1 ,,,

    Q1-2: Customers don't want "exception" and want to handle using memory protection and EMR register.

    (Please provide documents (or sample code) that shows how to implement memory protection…)

     

    Regards, Rei

  • 0 in reply to rei
    TI__Guru* 95265 points

    Hi,

    For the EDMA memory protection, the TRM says

    16.2.4.10 Memory Protection

    The EDMA channel controller supports two kinds of memory protection: active and proxy.
    16.2.4.10.1 Active Memory Protection
    Active memory protection is a feature that allows or prevents read and write accesses to the
    EDMA_TPCC registers.

    16.2.4.10.2 Proxy Memory Protection
    Proxy memory protection allows an EDMA transfer programmed by a given peripheral module connected
    to EDMA, to have its permissions travel with the transfer through the EDMA_TPTC. The permissions
    travel along with the read transactions to the source and the write transactions to the destination
    endpoints. The EDMA_TPCC_OPT_n[31] PRIV bit and EDMA_TPCC_OPT_n[27:24] PRIVID bit is set
    with the peripheral module's PRIV value and PRIVID values, respectively, when any part of the PaRAM
    set is written.
    The EDMA_TPCC_OPT_n[31] PRIV is the privilege level (i.e., user vs. supervisor). The
    EDMA_TPCC_OPT_n[27:24] PRIVID refers to a privilege ID with a number that is associated with an
    peripheral module connected to EDMA.
    These options are part of the TR that are submitted to the transfer controller. The transfer controller uses
    the above values on their respective read and write command bus so that the target endpoints can
    perform memory protection checks based on these values.

    Maybe Proxy Memory Protection is what you are looking for. I don't have example codes for this but this is illustrated well in the above TRM section by programming the EDMA_TPCC_OPT_n[31] PRIV bit and EDMA_TPCC_OPT_n[27:24] PRIVID bit.

    Regards, Eric