AM5728: DDR access from PCIe peripheral

Hideaki Matsumoto

Part Number: AM5728
Other Parts Discussed in Thread: XIO2001,

Hi,

My customer is now developing their own board based on AM5728. AM5728 as root complex is connected with ASIC as end-point via XIO2001 PCI-PCIe bridge.

AM5728 (RC) – PCIe – XIO2001(Bridge) – PCI – ASIC (EP)

DDR3

ASIC can read data in specific address of DDR3 connected with AM5728, right ? In this case, MMU2 should be used ? or needless to use it ?

Could you tell them how to set up and use PCIe ?

They tried to read the address 0x8000_000 (DDR3) and the address 0x4881e000 (L4_PER3) from ASIC (via XIO2001), but couldn’t read expected data and couldn’t write too.

They set the same address to both the base address (PCI register offset: 20h, 22h) of XIO2001 and the base address (PCIECTRL_RC_DBICS_PREF_MEM_BASE_LIMIT) of AM5728 as RC in PCIe configuration memory space.

And, set PCIECTRL_PL_IATU_INDEX as INBOUND (bit31 = 0b1), then confirmed REGION_ENAGE (bit31) in PCIECTRL_PL_IATU_REG_CTRL_2 to “0” in every index (bit3:0).

For now, MMU for PCIe inbound was not used. (as default)

Could you provide any your advice ?

Best regards,

Hideaki Matsumoto

over 5 years ago

0 Biser Gatchev-XID over 5 years ago

TI__Guru**** 393215 points

Please post what software is used, and which version? Linux or RTOS?

0 Hideaki Matsumoto over 5 years ago in reply to Biser Gatchev-XID

TI__Genius 9160 points

They're using PROCESSOR-SDK-RTOS-AM57X 06_00_00_07.

Thanks and regards,
Hideaki

0 lding over 5 years ago in reply to Hideaki Matsumoto

TI__Guru* 95265 points

Hideaki,

>>>>ASIC can read data in specific address of DDR3 connected with AM5728, right ? In this case, MMU2 should be used ? or needless to use it ?

Could you tell them how to set up and use PCIe ?>>>>>>Yes, it should be able to access DDR3 of AM57x from ASIC. There is no need to setup MMU2. The PCIE example is under pdk_am57xx_1_0_xx\packages\ti\drv\pcie\example\sample\src, user guide http://software-dl.ti.com/processor-sdk-rtos/esd/docs/latest/rtos/index_device_drv.html#pcie

>>>>They set the same address to both the base address (PCI register offset: 20h, 22h) of XIO2001 and the base address>>>> I have no knowledge of PCI and I can't comment

>>>>For now, MMU for PCIe inbound was not used. (as default)>>>> You need MMU setup see the TI PCIE example I mentioned above

And, please refer to the same example for BAR setup and inbound translation setup.

Regards, Eric

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AM5728: DDR access from PCIe peripheral