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EVMK2H: SGMII connection with DP83867ERGZ-S-EVM failed on U-boot

Part Number: EVMK2H

I produced a custom board based on the design of EVMK2H but didn't solve the problem for PHY. So I'm considering replacing PHY with DP83867 from TI.

To explore the possibilities, I first tested EVMK2H - DP83867ERGZ-S-EVM combination. The connection status is as below:

- PHY ID 0 : Marvell 88E1111 <--> SGMII 1st Port

- PHY ID 1 : Marvell 88E1111 <--> SGMII 2nd Port

- PHY ID 3 : TI DP83867 <--> SGMII 3rd Port

And I modified "keystone-k2hk-evm.dts" as below:

&mdio {
status = "ok";
ethphy0: ethernet-phy@0 {
compatible = "marvell,88E1111", "ethernet-phy-ieee802.3-c22";
reg = <0>;
};

ethphy1: ethernet-phy@1 {
compatible = "marvell,88E1111", "ethernet-phy-ieee802.3-c22";
reg = <1>;
};

ethphy2: ethernet-phy@2 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <3>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
ti,min-output-impedance;
ti,dp83867-rxctrl-strap-quirk;
};
};

However, the connection of SGMII 3rd port does not seem to be established on U-boot. LSB value of SGMII_STATUS register in Port 3 SGMII modules (0x0209 0414) is zero.

  • Hi,

    Can you try using the following configuration:
       ethphy2: ethernet-phy@2 {
           reg = <2>;
           ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
           ti,min-output-impedance;
           ti,dp83867-rxctrl-strap-quirk;
    };

    Best Regards,
    Yordan

  • According to our board engineer, there is no resistance so PHY ID of DP83867 cannot be changed to 2.

    I changed "reg" value from 2 to 3 in the configuration you recommended, but it didn't solve the problem.

    Do PHY IDs have to be arranged in order?

  • Hi,

    "I changed "reg" value from 2 to 3 in the configuration you recommended"

    In your post you show:
    ethphy2: ethernet-phy@2 {
    compatible = "ethernet-phy-ieee802.3-c22";
    reg = <3>;

    I recommended using:
        ethphy2: ethernet-phy@2 {
           reg = <2>;
           ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
           ti,min-output-impedance;
           ti,dp83867-rxctrl-strap-quirk;
    };

    It should be possible to remap the phy and use reg = <3>, as you wanted. Another thing, did you enalbe the CONFIG_PHY_TI in Menuconfig (k2hk_evm_defconfig) to enable the TI phy driver in u-boot? Currently only CONFIG_PHY_MARVEL is enabled.

    Best Regards,
    Yordan

  • I have checked the results for both configurations:

    When PHY ID was 3:

    ethphy2: ethernet-phy@2 {
           reg = <3>;
           ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
           ti,min-output-impedance;
           ti,dp83867-rxctrl-strap-quirk;
    };

    After modify PHY ID from 3 to 2:

    ethphy2: ethernet-phy@2 {
           reg = <2>;
           ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
           ti,min-output-impedance;
           ti,dp83867-rxctrl-strap-quirk;
    };

    I also added CONFIG_PHY_TI in "k2hk_evm_defconfig". However, SGMII link still does not work.

  • Hi,

    Have you revised your hardware schematics? Do you comply with the timings provided in datasheet?

    Best Regards,
    Yordan