• State Resolved
  • Locked Locked
  • Replies 3 replies
  • Subscribers 98 subscribers
  • Views 499 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TDA3MV: McASP3 pinmux for TDA3 (SR2.0)

Arseniy Platonov
Expert 1555 points
Part Number: TDA3MV

Hi.

I want to connect AIC3106 to my TDA3MVRBFABFQ1 via McASP3.

TDA3 Devive Datasheet (SPRS964G, March2019).
Page 64: Table 4-18:
H19 (mcasp3_ahclkx), F22 (mcasp3_aclkx), H22 (mcasp3_fsx), G18 (mcasp3_axr1), G19 (mcasp3_axr0).

Table 4-2.
Page 30. Ball H19, Muxmode 15, "xref_clk2" and "mcasp3_ahclkx".
Page 30. Ball H22, Muxmode 15, "Driver off" AND "mcasp3_fsx".
Page 29. Ball F22, Muxmode 15, "Driver off" AND "mcasp3_aclkx".
Page 29. Ball G18, Muxmode 15, "Driver off" AND "mcasp3_axr1".
Page 32. Ball G19, Muxmode 15, "Driver off" AND "mcasp3_axr0".

What does mean both AND "driver off" AND mcasp3 func in one cell?
Is this about two different SiliconRevisions (SR1.0 and SR2.0)?

I can't find any proper mux mode for mcasp3 in Tda3_TRM (SPRUIE7D, Jul2019).
Chapter 14 (Control Module).

Page 5002: Table 14-674: CTRL_CORE_PAD_VIN1A_D5 (0x4A0034A0): bits 3..0: VIN1A_D5_MUXMODE: 0xF: Driver off (SR1.0 Only) / xref_clk2 (SR2.0 Only)
Where is any info about "mcasp3_ahclkx"?

Page 4993: Table 14-654: CTRL_CORE_PAD_VIN1A_CLK0 (0x4A003478): bits 3..0: VIN1A_CLK0_MUXMODE: 0xF: Driver off
Where is any info about "mcasp3_aclkx"?

Page 5003: Table 14-676: CTRL_CORE_PAD_VIN1A_D6 (0x4A0034A4): bits 3..0: VIN1A_D6_MUXMODE: 0xF: Driver off
Where is any info about "mcasp3_fsx"?

Page 4998: Table 14-664: CTRL_CORE_PAD_VIN1A_D0 (0x4A00348C): bits 3..0: VIN1A_D0_MUXMODE: 0xF: Driver off
Where is any info about "mcasp3_axr1"?

Page 4997: Table 14-662: CTRL_CORE_PAD_VIN1A_VSYNC0 (0x4A003488): bits 3..0: VIN1A_VSYNC0_MUXMODE: 0xF: Driver off
Where is any info about "mcasp3_axr0"?

There is no info about McASP3 in Errata (SPRZ425F, Oct2019).

Is McASP3 supported in TDA3 SR2.0?
Can you update TRM with McASP3 pinmuxing?


best regards.

  • 0
    TI__Genius 13630 points

    Hello and thanks for the questions. Let us evaluate each one of them and will get back to you here soon.

    Thanks,

    Alex

  • 0
    TI__Genius 13630 points

    Hello ,

    So we've looked into this. Let me try to explain this in one shot. Basically, you are having an alternate mode to the driver off mode in function 15 on these balls. I think the easiest way to study the alternate modes is with the PinMux tool. It gives you a GUI perspective on these things: https://dev.ti.com/pinmux/ 

    Let's take an example. In the tool, go ahead and configure mcasp3_ahclkx on H19. If you look closely, you will see it is in function 17 (anything beyond function 15 is an alternate mode). if you generate one of the C files available, you will see the configuration in code, as shown below:

    And if you cross-check this in the TRM, you will find that 2 registers need to be configured for this signal(mcasp3_ahclkx) to be re-routed to pin H19. 

    - CTRL_CORE_PAD_VIN1A_D5 (muxmode 0xF) and

    - CTRL_CORE_SMA_SW_14 (0x100000)

    By the way, these alternate options are pretty well explained in table "Pads Having Capability for Additional Signal Mapping" in TDA2Px TRM. However, these indeed are not included in the TDA3 TRM. I will check with the documentation team, and will update the TRM accordingly.

    Hope this helps,

    thanks,

    Alex

  • 0
    TI__Genius 13630 points

    Hello again @senchuss,

    Here is what we currently have in the TRM, which I think completes the answe to your question:

    SR2.0 Only:


    Except the maximum 16 possible combinations through the MUXMODE bit fields using the bits within
    CTRL_CORE_SMA_SW_14 and CTRL_CORE_SMA_SW_15 registers an additional signal can be
    mapped to several device pads. In other words, for these pads there are up to 17 possible signal
    combinations although not all of them are really implemented. These registers control McASP2 and
    McASP3 signal multiplexing. If a bit is set to 0x1, function 17 is selected for the corresponding pad. In that
    case the MUXMODE field of the corresponding CTRL_CORE_PAD_x register must be set to 0xF. If a bit
    is set to 0x0, function 17 is not selected.

    Thanks,

    Alex