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MCASP3 can't generate DMA interrupt

Hi Sir,

Processor is DRA78X,PDK is 4.3.05.

We use MCASP3 as rx,mcasp1 as tx in our project,both them use DSP1 EDMA, mcasp1 tx can generate edma callback generate,but mcasp3 rx can't generate edma callback.

I attach the mcasp3/dsp1 irq/dsp1 edma registers,please help us to check it.

Best Regards,

He Weibing

/*MCASP3*/
C66xx_DSP1: GEL Output: 0x48470000 	C66xx_DSP1: GEL Output: 	= 0x44307B03
C66xx_DSP1: GEL Output: 0x48470004 	C66xx_DSP1: GEL Output: 	= 0x00000001
C66xx_DSP1: GEL Output: 0x48470008 	C66xx_DSP1: GEL Output: 	= 0x00000000
C66xx_DSP1: GEL Output: 0x4847000C 	C66xx_DSP1: GEL Output: 	= 0x00000000
C66xx_DSP1: GEL Output: 0x48470010 	C66xx_DSP1: GEL Output: 	= 0x00000000
C66xx_DSP1: GEL Output: 0x48470014 	C66xx_DSP1: GEL Output: 	= 0xE0000001
C66xx_DSP1: GEL Output: 0x48470018 	C66xx_DSP1: GEL Output: 	= 0x00000000
C66xx_DSP1: GEL Output: 0x4847001C 	C66xx_DSP1: GEL Output: 	= 0xA0000008
C66xx_DSP1: GEL Output: 0x48470020 	C66xx_DSP1: GEL Output: 	= 0x00000000
C66xx_DSP1: GEL Output: 0x48470024 	C66xx_DSP1: GEL Output: 	= 0x00000000
C66xx_DSP1: GEL Output: 0x48470028 	C66xx_DSP1: GEL Output: 	= 0x00000000
C66xx_DSP1: GEL Output: 0x4847002C 	C66xx_DSP1: GEL Output: 	= 0x00000000
C66xx_DSP1: GEL Output: 0x48470030 	C66xx_DSP1: GEL Output: 	= 0x0000C291
C66xx_DSP1: GEL Output: 0x48470034 	C66xx_DSP1: GEL Output: 	= 0x00000000
C66xx_DSP1: GEL Output: 0x48470038 	C66xx_DSP1: GEL Output: 	= 0x00000001
C66xx_DSP1: GEL Output: 0x4847003C 	C66xx_DSP1: GEL Output: 	= 0x00000000
C66xx_DSP1: GEL Output: 0x48470040 	C66xx_DSP1: GEL Output: 	= 0x00000000
C66xx_DSP1: GEL Output: 0x48470044 	C66xx_DSP1: GEL Output: 	= 0x0000001F
C66xx_DSP1: GEL Output: 0x48470048 	C66xx_DSP1: GEL Output: 	= 0x00000000
C66xx_DSP1: GEL Output: 0x4847004C 	C66xx_DSP1: GEL Output: 	= 0x00000000
C66xx_DSP1: GEL Output: 0x48470050 	C66xx_DSP1: GEL Output: 	= 0x00000000
C66xx_DSP1: GEL Output: 0x48470054 	C66xx_DSP1: GEL Output: 	= 0x00000000
C66xx_DSP1: GEL Output: 0x48470058 	C66xx_DSP1: GEL Output: 	= 0x00000000
C66xx_DSP1: GEL Output: 0x4847005C 	C66xx_DSP1: GEL Output: 	= 0x00000000
C66xx_DSP1: GEL Output: 0x48470060 	C66xx_DSP1: GEL Output: 	= 0x0000001F
C66xx_DSP1: GEL Output: 0x48470064 	C66xx_DSP1: GEL Output: 	= 0xFFFFFFFF
C66xx_DSP1: GEL Output: 0x48470068 	C66xx_DSP1: GEL Output: 	= 0x000180F0
C66xx_DSP1: GEL Output: 0x4847006C 	C66xx_DSP1: GEL Output: 	= 0x00000113
C66xx_DSP1: GEL Output: 0x48470070 	C66xx_DSP1: GEL Output: 	= 0x000000A6
C66xx_DSP1: GEL Output: 0x48470074 	C66xx_DSP1: GEL Output: 	= 0x00008000
C66xx_DSP1: GEL Output: 0x48470078 	C66xx_DSP1: GEL Output: 	= 0x00000003
C66xx_DSP1: GEL Output: 0x4847007C 	C66xx_DSP1: GEL Output: 	= 0x00000003
C66xx_DSP1: GEL Output: 0x48470080 	C66xx_DSP1: GEL Output: 	= 0x00000104
C66xx_DSP1: GEL Output: 0x48470084 	C66xx_DSP1: GEL Output: 	= 0x00000000
C66xx_DSP1: GEL Output: 0x48470088 	C66xx_DSP1: GEL Output: 	= 0xAC000000
C66xx_DSP1: GEL Output: 0x4847008C 	C66xx_DSP1: GEL Output: 	= 0x00000000
C66xx_DSP1: GEL Output: 0x48470090 	C66xx_DSP1: GEL Output: 	= 0x00000000
C66xx_DSP1: GEL Output: 0x48470094 	C66xx_DSP1: GEL Output: 	= 0x00000000
C66xx_DSP1: GEL Output: 0x48470098 	C66xx_DSP1: GEL Output: 	= 0x00000000
C66xx_DSP1: GEL Output: 0x4847009C 	C66xx_DSP1: GEL Output: 	= 0x00000000
C66xx_DSP1: GEL Output: 0x484700A0 	C66xx_DSP1: GEL Output: 	= 0x0000001F
C66xx_DSP1: GEL Output: 0x484700A4 	C66xx_DSP1: GEL Output: 	= 0xFFFFFFFF
C66xx_DSP1: GEL Output: 0x484700A8 	C66xx_DSP1: GEL Output: 	= 0x00000000
C66xx_DSP1: GEL Output: 0x484700AC 	C66xx_DSP1: GEL Output: 	= 0x00000002
C66xx_DSP1: GEL Output: 0x484700B0 	C66xx_DSP1: GEL Output: 	= 0x00180023
C66xx_DSP1: GEL Output: 0x484700B4 	C66xx_DSP1: GEL Output: 	= 0x00188046
C66xx_DSP1: GEL Output: 0x484700B8 	C66xx_DSP1: GEL Output: 	= 0x00000001
C66xx_DSP1: GEL Output: 0x484700BC 	C66xx_DSP1: GEL Output: 	= 0x00000000
C66xx_DSP1: GEL Output: 0x484700C0 	C66xx_DSP1: GEL Output: 	= 0x0000010C
C66xx_DSP1: GEL Output: 0x484700C4 	C66xx_DSP1: GEL Output: 	= 0x0000017F
C66xx_DSP1: GEL Output: 0x484700C8 	C66xx_DSP1: GEL Output: 	= 0x00000000
C66xx_DSP1: GEL Output: 0x484700CC 	C66xx_DSP1: GEL Output: 	= 0x00000000


/*DSP1 IRQ*/
C66xx_DSP1: GEL Output: 0x4A002948 	C66xx_DSP1: GEL Output: 	= 0x00020001
C66xx_DSP1: GEL Output: 0x4A00294C 	C66xx_DSP1: GEL Output: 	= 0x00040003
C66xx_DSP1: GEL Output: 0x4A002950 	C66xx_DSP1: GEL Output: 	= 0x00060005
C66xx_DSP1: GEL Output: 0x4A002954 	C66xx_DSP1: GEL Output: 	= 0x00080007
C66xx_DSP1: GEL Output: 0x4A002958 	C66xx_DSP1: GEL Output: 	= 0x000A0009
C66xx_DSP1: GEL Output: 0x4A00295C 	C66xx_DSP1: GEL Output: 	= 0x000C000B
C66xx_DSP1: GEL Output: 0x4A002960 	C66xx_DSP1: GEL Output: 	= 0x000E000D
C66xx_DSP1: GEL Output: 0x4A002964 	C66xx_DSP1: GEL Output: 	= 0x0010000F
C66xx_DSP1: GEL Output: 0x4A002968 	C66xx_DSP1: GEL Output: 	= 0x00120011
C66xx_DSP1: GEL Output: 0x4A00296C 	C66xx_DSP1: GEL Output: 	= 0x00140013
C66xx_DSP1: GEL Output: 0x4A002970 	C66xx_DSP1: GEL Output: 	= 0x00160015
C66xx_DSP1: GEL Output: 0x4A002974 	C66xx_DSP1: GEL Output: 	= 0x00180017
C66xx_DSP1: GEL Output: 0x4A002978 	C66xx_DSP1: GEL Output: 	= 0x001A0019
C66xx_DSP1: GEL Output: 0x4A00297C 	C66xx_DSP1: GEL Output: 	= 0x001C001B
C66xx_DSP1: GEL Output: 0x4A002980 	C66xx_DSP1: GEL Output: 	= 0x001E0068
C66xx_DSP1: GEL Output: 0x4A002984 	C66xx_DSP1: GEL Output: 	= 0x0020001F
C66xx_DSP1: GEL Output: 0x4A002988 	C66xx_DSP1: GEL Output: 	= 0x00220021
C66xx_DSP1: GEL Output: 0x4A00298C 	C66xx_DSP1: GEL Output: 	= 0x00240023
C66xx_DSP1: GEL Output: 0x4A002990 	C66xx_DSP1: GEL Output: 	= 0x00260025
C66xx_DSP1: GEL Output: 0x4A002994 	C66xx_DSP1: GEL Output: 	= 0x00ED0027
C66xx_DSP1: GEL Output: 0x4A002998 	C66xx_DSP1: GEL Output: 	= 0x002A011C
C66xx_DSP1: GEL Output: 0x4A00299C 	C66xx_DSP1: GEL Output: 	= 0x002C002B
C66xx_DSP1: GEL Output: 0x4A0029A0 	C66xx_DSP1: GEL Output: 	= 0x002E002D
C66xx_DSP1: GEL Output: 0x4A0029A4 	C66xx_DSP1: GEL Output: 	= 0x0030002F
C66xx_DSP1: GEL Output: 0x4A0029A8 	C66xx_DSP1: GEL Output: 	= 0x00320031
C66xx_DSP1: GEL Output: 0x4A0029AC 	C66xx_DSP1: GEL Output: 	= 0x00340033
C66xx_DSP1: GEL Output: 0x4A0029B0 	C66xx_DSP1: GEL Output: 	= 0x00360035
C66xx_DSP1: GEL Output: 0x4A0029B4 	C66xx_DSP1: GEL Output: 	= 0x003801C7
C66xx_DSP1: GEL Output: 0x4A0029B8 	C66xx_DSP1: GEL Output: 	= 0x003A0039
C66xx_DSP1: GEL Output: 0x4A0029BC 	C66xx_DSP1: GEL Output: 	= 0x003C003B
C66xx_DSP1: GEL Output: 0x4A0029C0 	C66xx_DSP1: GEL Output: 	= 0x003E003D
C66xx_DSP1: GEL Output: 0x4A0029C4 	C66xx_DSP1: GEL Output: 	= 0x0040003F

/*DSP1 EDMA DREQ*/
C66xx_DSP1: GEL Output: 0x4A002CF8 	C66xx_DSP1: GEL Output: 	= 0x00810080
C66xx_DSP1: GEL Output: 0x4A002CFC 	C66xx_DSP1: GEL Output: 	= 0x00830082
C66xx_DSP1: GEL Output: 0x4A002D00 	C66xx_DSP1: GEL Output: 	= 0x00850084
C66xx_DSP1: GEL Output: 0x4A002D04 	C66xx_DSP1: GEL Output: 	= 0x00870086
C66xx_DSP1: GEL Output: 0x4A002D08 	C66xx_DSP1: GEL Output: 	= 0x00890088
C66xx_DSP1: GEL Output: 0x4A002D0C 	C66xx_DSP1: GEL Output: 	= 0x008B008A
C66xx_DSP1: GEL Output: 0x4A002D10 	C66xx_DSP1: GEL Output: 	= 0x008D008C
C66xx_DSP1: GEL Output: 0x4A002D14 	C66xx_DSP1: GEL Output: 	= 0x008F008E
C66xx_DSP1: GEL Output: 0x4A002D18 	C66xx_DSP1: GEL Output: 	= 0x009B009A
C66xx_DSP1: GEL Output: 0x4A002D1C 	C66xx_DSP1: GEL Output: 	= 0x009D00EA

  • Hi He,

    It looks like you have McASP3 Rx event properly mapped in DSP1 crossbar.

    By the way, the DSP1 IRQ crossbar is only optinally used for error interrupts, so this setting should not affect DMA callbacks during normal run-time operation.

    Did you also update the following:

    • EDMA channel event map to enable the Rx event for this McASP instance.  By default, only DSP1 EDMA events 0 and 1 are enabled, all others are masked.
    • McASP3 instance rxDmaEventNumber (through calls to Mcasp_socGetInitCfg/Mcasp_socSetInitCfg).  By default this is set to System EDMA instance.

    Thanks,
    Stephen

  • Hi, Weibing:

    based on your hardware, DRA78x, McASP3 acts as I2S master, 48kHz sample rate, 22.576M sysclk2 input

    Here is a mistake in configuration:

    C66xx_DSP1: GEL Output: 0x48470070 C66xx_DSP1: GEL Output: = 0x000000A6 

    C66xx_DSP1: GEL Output: 0x48470074 C66xx_DSP1: GEL Output: = 0x00008000

    1. the divider 6 : this should not be the case.
    2. HCLKRM : should not be 1 (please refer to TRM, Receive Clock Generator Block Diagram

    Please fix these and update the status.

    Thanks.

  • Hi,

    With one more changes in 

    C66xx_DSP1: GEL Output: 0x484700B0 C66xx_DSP1: GEL Output: = 0x00180023

    modify to use ASYNC = 1, 

    problem sovled.

  • Hi Stephen,

    Many thanks for your help.

    Why the DSP1 IRQ crossbar only used for error interrupts?

    I don't find any DSP1 TPCC region XX interrput map to DSP1_INTC, but the DSP EDMA interrput also occurs, could you tell me the reason? Thanks you very much!

    Best Regards,

    He Weibing

  • Hi He,

    Sorry, let me clarify my last statement.  In general, yes, interrupt XBAR is required for EDMA interrupts.  However, this is performed by EDMA LLD and does not require application or McASP LLD to setup.

    In the case of DSP1 EDMA -> DSP1_INTC routing, default mapping of DSP1_IRQ_16 through DSP1_IRQ_20 contain the DSP1 EDMA CC interrupts.  This may not be clear by looking at the DSP1_INTC table in the TRM, but if you look at section 4.3.4 DSP Interrupt Requests and especially figure 4.5, it is more clear that the DSP1 EDMA interrupts are internally routed to the DSP1_INTC and don't require any further configuration.

    Thanks,
    Stephen

  • Many thanks,this issue is fixed.