TMS320C6678: TMS320C6678: Hyperlink remote interrupts

Daniel,

As I mentioned in another E2E, the TI Hyperlink driver doesn't support interrupt except error interrupt, the interrupt code example only floats in some E2E forum posts. I pointed a test code I adapted from C6670 to C6678 and was able to run on C6678 in loopback mode earlier this year, I believe the code can generate more than 1 interrupts (may be simple, just i_0), so you should be able to find out most of your answers. 

About generating i_0 and i_63 and how to distinguish them, please read the Hyperlink user guide  2.7.5.and 2.7.6 and 2.8, and try the code. I believe there just a few registers you need to poke and examine. I can also find some time to read the doc and try and give you feedback in a few days.

Regards, Eric  

Hi Eric,

   I don't need code already written. My expectations is to have only a datasheet that is clear and without mistakes, which seems to be not the case for TI. I don't think it is normal to find how it is designed a hardware by playing with registers and trying to clarify the confusions from manuals.

    Thank you for your support.

/Daniel

Daniel,

Thanks for your comments! The Hyperlink is a complicated peripheral, it has many features in design but not discussed in great details in the user guide. We don't have any plan to extensively update this as it is an old device and a not commonly used peripheral, further update will be cosmetics if any.

The software inside processor SDK RTOS covers most part of the functionality and I agree the interrupt part is missing and leaves my questions for usage. Unfortunately we don't have plan to add more code examples. 

Let me know how you want to proceed this ticket. If you have a design with this chip and peripheral, we can still try the interrupt part of code.  

Regards, Eric

Hi,

   In the user guide it says "HyperLink provides three types of transactions: read, write, and interrupt events."

    I would like to know if the interrupts events could be software triggered from one board to another (can be used the Generate Soft Interrupt Value Register to trigger an event to a remote board ?), if events could be distinguished by some IDs when remote receive its (could I detect on evmB what ivector was used on evmA when I was triggered?), if events could address a specific remote coreID and if the events could be handled using the VUSR_INT_O 

  Control Register[intvec] -  Interrupt Vector. This field indicates which bit in the Interrupt Pending/Set Register is set for HyperLink module.

  Q: Can be set in this Pending/Set Register bits for other peripherals? For what can I use if I use bit0 versus bit31 in that register?

  Control Register[int2cfg] -  Interrupt to Configuration Register. When this bit is set, the Interrupt Pending/Set Register is written directly with the status contained in interrupt packets. 

  Q: How is controlled the value/status from interrupt packet from sender side?

 Control Register[intenable] -  Interrupt Enable. This bit causes HyperLink module status interrupts to be posted to the Interrupt Pending/Set Register

 Q: With what could help me to have set in the Interrupt Pending/Set Register the values of the statuses from module status interrupts?

Interrupt Priority Vector Status/Clear Register[intstat] - When read, this field displays the vector that is mapped to the highest priority interrupt bit that is pending from the Interrupt Status/Clear Register

Q: From where it comes this priority and how it is used?

Interrupt Status/Clear Register[intclr] - This field indicates the unmasked status of each interrupt. 

Q: Statuses of which interrupts - generated how ? Having 32 bits it means we have 32 interrupts? Are we speaking about software or hardware interrupts?

/Daniel.