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66AK2H06: IPU and IPD questions

Part Number: 66AK2H06

Hi,

I have a few questions from my customer about internal pull-up(IPU) and internal pull-down(IPD).

Q1) How to enable / disable IPU/IPD at each pin?
I could not find any registers for this purpose.
IPU/IPD are enabled all the time?

Q2) If answer to Q1 is “Yes”.
IPU/IPD are enabled even the pin is configured as output?
For example, EMIF pins are input/output/HiZ based on control signal truth table.
IPU/IPD are enabled regardless I/O mode?
(ideally IPU/IPD should be enabled only when HiZ)



Thanks and regards,
Koichiro Tashiro

  • Hi Koichiro,

    There is no software control (register) for the internal pullup and pulldown resistors on the device pads. See the datasheet:

    Section 4.3 Terminal Functions:
     "Internal 100-μA pulldown or pullup is provided for this terminal. In most systems, a 1-kΩ resistor can be used to oppose the IPD/IPU. For more detailed information on pulldown/pullup resistors and situations in which external pulldown/pullup resistors are required, see Hardware Design Guide for KeyStone II Devices."

    Section 4.4 Pullup/Pulldown Resistors

    Section 10.2.1DeviceConfigurationat Device Reset:

      "If a configuration pin mus tbe routed out from the device and it is not driven (Hi-Zstate), the internal pullup/pulldown (IPU/IPD) resistor should not be relied upon.TI recommends the use of an external pullup/pulldown resistor. For more detailed information on pullup/pulldown resistors and situations in which external pullup/pulldown resistors are required, see Section4.4."

    Best Regards,
    Yordan

  • Hi Yordan,

    So the IPU/IPD are enabled all the time during power-up sequence / under reset / normal operation?
    In customer’s system, FPGA is connected to EMIF16 and there are weak pull-up on FPGA side.
    On the other side, EMIF16 data bus has weak pull-down.
    Customer wants to keep the bus Hi state.

    According to datasheet table 5.5, the weak pull-down on 66AK2H06 is -170uA(min) and -50uA(max)
    FPGA side pull-up is 34uA(min) and 220uA(max).
    In the worst case combination, 66AK2H06 side is -170uA and FPGA side is 34uA.
    Under this scenario, adding 1kOhm external pull-up with 136uA (=170uA-34uA) current flow results in;
    1.8V – (1kOhm * 136uA) = 1.664V on the net. This is over Voh and the net is kept Hi.
    Is my understanding correct?

    Thanks and regards,
    Koichiro Tashiro

  • Hi Koichiro,

    Yes, your understanding is correct.

    As per the datasheet, the min value of Voh is 1.35V, so 1.664 should be accepted as high level. However 1.35 is Voh min value, I believe the TYP value is 1.8V. 

    Best Regards,
    Yordan

  • Hi Yordan,

    Yordan Kovachev said:

    Yes, your understanding is correct.



    This means below my comment is also correct?
    > So the IPU/IPD are enabled all the time during power-up sequence / under reset / normal operation?

    Thanks and regards,
    Koichiro Tashiro

  • Yordan,

    Could you answer my last question?

    Thanks and regards,
    Koichiro Tashiro

  • Hi,


    Sorry for the delay.
    Yes, you are correct. The IPD/IPU column in table Table4-2. Terminal Functions— Signals and Control by Function shows the state: Up or Down.

    Best Regards,
    Yordan