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AM5726: Kernel boot hangs

Part Number: AM5726
Other Parts Discussed in Thread: AM5728, , BEAGLEBOARD-X15, DRA752

Hello

I have a custom board based on beagle-x15/ti-evm.

I have make some modifications on U-boot, for example my custom board dont have an EEPROM to detect the board.

If I start the board I get some u-boot messages and it seems look it want to start the kernel but it stuck.

U-Boot SPL 2019.01 (Oct 16 2019 - 17:50:53 +0200)
DRA752-GP ES2.0
Trying to boot from MMC1
no pinctrl state for default mode
no pinctrl state for default mode
Loading Environment from FAT... *** Warning - bad CRC, using default environment

Loading Environment from MMC... Card did not respond to voltage select!
*** Warning - No block device, using default environment



U-Boot 2019.01 (Oct 16 2019 - 17:50:53 +0200)

CPU  : DRA752-GP ES2.0
Model: TI AM5728 BeagleBoard-X15
Board: SEC4 
DRAM:  1 GiB
Size of DRAM is 1024 MB

beagle_x
MMC:   OMAP SD/MMC: 0, OMAP SD/MMC: 1
Loading Environment from FAT... *** Warning - bad CRC, using default environment

Loading Environment from MMC... Card did not respond to voltage select!
*** Warning - No block device, using default environment

 *** -> This Board is unknown

late init

late init 2a

Card did not respond to voltage select!
invalid mmc device
late init 2b

end of late init

Net:   Could not get PHY for ethernet@48484000: addr 1

Warning: ethernet@48484000 using MAC address from ROM
eth0: ethernet@48484000
Hit any key to stop autoboot:  0 
switch to partitions #0, OK
mmc0 is current device
SD/MMC found on device 0
** Unable to read file boot.scr **
1490 bytes read in 2 ms (727.5 KiB/s)
Loaded env from uEnv.txt
Importing environment from mmc0 ...
Running uenvcmd ...
1 bytes read in 1 ms (1000 Bytes/s)
Already setup.
switch to partitions #0, OK
mmc0 is current device
SD/MMC found on device 0
4211200 bytes read in 190 ms (21.1 MiB/s)
133193 bytes read in 8 ms (15.9 MiB/s)
## Flattened Device Tree blob at 88000000
   Booting using the fdt blob at 0x88000000
   Loading Device Tree to 8ffdc000, end 8ffff848 ... OK

Starting kernel ...

The printenv:

=> printenv
arch=arm
args_mmc=run finduuid;setenv bootargs console=${console} ${optargs} root=PARTUUID=${uuid} rw rootfstype=${mmcrootfstype}
baudrate=115200
board=am57xx
board_name=beagle_x15
board_rev=0.0
board_serial=0000
boot_fdt=try
boot_fit=0
bootargs=androidboot.serialno=${serial#} console=ttyS2,115200 androidboot.console=ttyS2 androidboot.hardware=beagle_x15board
bootcmd=if test ${dofastboot} -eq 1; then echo Boot fastboot requested, resetting dofastboot ...;setenv dofastboot 0; saveenv;echo Booting
bootdelay=2
bootdir=/boot
bootenvfile=uEnv.txt
bootfile=zImage
bootm_size=0x10000000
bootpart=0:2
bootscript=echo Running bootscript from mmc${mmcdev} ...; source ${loadaddr}
console=ttyO2,115200n8
cpu=armv7
dfu_alt_info_emmc=rawemmc raw 0 3751936;boot part 1 1;rootfs part 1 2;MLO fat 1 1;MLO.raw raw 0x100 0x200;u-boot.img.raw raw 0x300 0x1000;1
dfu_alt_info_mmc=boot part 0 1;rootfs part 0 2;MLO fat 0 1;MLO.raw raw 0x100 0x200;u-boot.img.raw raw 0x300 0x1000;u-env.raw raw 0x1300 0x1
dfu_alt_info_qspi=MLO raw 0x0 0x040000;u-boot.img raw 0x040000 0x0100000;u-boot-spl-os raw 0x140000 0x080000;u-boot-env raw 0x1C0000 0x0100
dfu_alt_info_ram=kernel ram 0x80200000 0x4000000;fdt ram 0x80f80000 0x80000;ramdisk ram 0x81000000 0x4000000
dfu_bufsiz=0x10000
dofastboot=0
emmc_android_boot=echo Trying to boot Android from eMMC ...; run update_to_fit; setenv eval_bootargs setenv bootargs $bootargs; run eval_b;
emmc_linux_boot=echo Trying to boot Linux from eMMC ...; setenv mmcdev 1; setenv bootpart 1:2; setenv mmcroot /dev/mmcblk0p2 rw; run mmcbo;
envboot=mmc dev ${mmcdev}; if mmc rescan; then echo SD/MMC found on device ${mmcdev};if run loadbootscript; then run bootscript;else if ru;
ethaddr=18:62:e4:6f:58:2c
fastboot.board_rev=0.0
fastboot.cpu=DRA752
fastboot.secure=GP
fdt_addr_r=0x88000000
fdtaddr=0x88000000
fdtcontroladdr=bdf25650
fdtfile=undefined
findfdt=if test $board_name = omap5_uevm; then setenv fdtfile omap5-uevm.dtb; fi; if test $board_name = dra7xx; then setenv fdtfile dra7-e
finduuid=part uuid mmc ${bootpart} uuid
fit_bootfile=fitImage
fit_loadaddr=0x90000000
get_overlaystring=for overlay in $overlay_files;do;setenv overlaystring ${overlaystring}'#'${overlay};done;
importbootenv=echo Importing environment from mmc${mmcdev} ...; env import -t ${loadaddr} ${filesize}
kernel_addr_r=0x82000000
loadaddr=0x82000000
loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenvfile}
loadbootscript=load mmc ${mmcdev} ${loadaddr} boot.scr
loadfdt=load ${devtype} ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}
loadfit=run args_mmc; run run_fit;
loadimage=load ${devtype} ${bootpart} ${loadaddr} ${bootdir}/${bootfile}
mmcboot=mmc dev ${mmcdev}; setenv devnum ${mmcdev}; setenv devtype mmc; if mmc rescan; then echo SD/MMC found on device ${mmcdev};if run l;
mmcdev=0
mmcloados=run args_mmc; if test ${boot_fdt} = yes || test ${boot_fdt} = try; then if run loadfdt; then bootz ${loadaddr} - ${fdtaddr}; els;
mmcrootfstype=ext4 rootwait
netargs=setenv bootargs console=${console} ${optargs} root=/dev/nfs nfsroot=${serverip}:${rootpath},${nfsopts} rw ip=dhcp
netboot=echo Booting from network ...; setenv autoload no; dhcp; run netloadimage; run netloadfdt; run netargs; bootz ${loadaddr} - ${fdta}
netloadfdt=tftp ${fdtaddr} ${fdtfile}
netloadimage=tftp ${loadaddr} ${bootfile}
nfsopts=nolock
partitions=uuid_disk=${uuid_gpt_disk};name=bootloader,start=384K,size=1792K,uuid=${uuid_gpt_bootloader};name=rootfs,start=2688K,size=-,uui}
partitions_android=uuid_disk=${uuid_gpt_disk};name=xloader,start=128K,size=256K,uuid=${uuid_gpt_xloader};name=bootloader,size=2048K,uuid=$}
pxefile_addr_r=0x80100000
ramdisk_addr_r=0x88080000
rdaddr=0x88080000
rootpath=/export/rootfs
run_fit=bootm ${fit_loadaddr}#${fdtfile}${overlaystring}
scriptaddr=0x80000000
serial#=0b00f0133c4e08e2
soc=omap5
static_ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off
stderr=serial@48020000
stdin=serial@48020000
stdout=serial@48020000
update_to_fit=setenv loadaddr ${fit_loadaddr}; setenv bootfile ${fit_bootfile}
usbtty=cdc_acm
vendor=ti
ver=U-Boot 2019.01 (Oct 16 2019 - 17:50:53 +0200)
vram=16M

Environment size: 7419/131067 bytes

  • Hello rekoe,

    Please, refer to this post.

    Best regards,
    Kemal

  • Hello Kemal,

    Can you help me now on the Kernel-boot step?

    Best regards
    rekoe

  • Please, refer to this post.

  • Hello Kemal,

    Can you please help me with the Kernel-Hang/Panic?

    Now I have rebuild the Kernel with "debug support":
    make distclean
    make tisdk_am57xx-evm-rt_defconfig
    make menuconfig
    -> DEBUG_LL [=y]
    -> DEBUG_OMAP4UART3 [=y]
    -> EARLY_PRINTK [=y]
    -> DEBUG_UART_PHYS [=0x48020000]  
    -> DEBUG_UART_VIRT [=0xfa020000]
    make -j8 zImage

    In U-boot "u-boot/board/ti/am57xx/board.c" of I have dropped the board recognation-routine and some other stuff.
    I have modified the "mux_data.h" and the DTS in "arch/arm/dts/am57xx-beagle-x15.dts".
    I have copied the "zImage" and "arch/arm/dts/am57xx-beagle-x15.dtb" to the boot partition on MMC device.

    If I start manuell the "zImage" and get a kernel-panic:

    manual Instructions during u-boot:

    -> setenv bootargs console=ttyO2,115200 earlyprintk loglevel=3 mem=0x40000000 loglevel=7
    -> load mmc 0:1 0x88000000 sec4.dtb
    -> load mmc 0:1 0x82000000 zImage
    -> bootz 0x82000000 - 0x88000000

     

    Here is UART3 Output:

    U-Boot SPL 2019.01 (Oct 18 2019 - 16:55:06 +0200)
    DRA752-GP ES2.0
    Trying to boot from MMC1
    no pinctrl state for default mode
    no pinctrl state for default mode
    Loading Environment from FAT... *** Warning - bad CRC, using default environment
    
    Loading Environment from MMC... Card did not respond to voltage select!
    *** Warning - No block device, using default environment
    
    
    
    U-Boot 2019.01 (Oct 18 2019 - 16:55:06 +0200)
    
    CPU  : DRA752-GP ES2.0
    Model: TI AM5726 sec4
    Board: SEC4 
    DRAM:  1 GiB
    Size of DRAM is 1024 MB
    
    beagle_x
    MMC:   OMAP SD/MMC: 0
    Loading Environment from FAT... *** Warning - bad CRC, using default environment
    
    Loading Environment from MMC... MMC Device 1 not found
    *** Warning - No MMC card found, using default environment
    
     *** -> This Board is unknown
    
    late init
    
    late init 2a
    
    invalid mmc device
    late init 2b
    
    end of late init
    
    Net:   No ethernet found.
    Hit any key to stop autoboot:  0 
    => 
    => setenv bootargs console=ttyO2,115200 earlyprintk loglevel=3 mem=0x40000000 loglevel=7
    => load mmc 0:1 0x88000000 sec4.dtb
    128072 bytes read in 7 ms (17.4 MiB/s)
    => load mmc 0:1 0x82000000 zImage
    4203008 bytes read in 188 ms (21.3 MiB/s)
    => bootz 0x82000000 - 0x88000000
    ## Flattened Device Tree blob at 88000000
       Booting using the fdt blob at 0x88000000
       Loading Device Tree to 8ffdd000, end 8ffff447 ... OK
    
    Starting kernel ...
    
    [    0.000000] Booting Linux on physical CPU 0x0
    [    0.000000] Linux version 4.19.38-rt19 (rene@ubuntu) (gcc version 8.3.0 (GNU Toolchain for the A-profile Archite9
    [    0.000000] CPU: ARMv7 Processor [412fc0f2] revision 2 (ARMv7), cr=30c5387d
    [    0.000000] CPU: div instructions available: patching division code
    [    0.000000] CPU: PIPT / VIPT nonaliasing data cache, PIPT instruction cache
    [    0.000000] OF: fdt: Machine model: TI AM5726 sec4
    [    0.000000] bootconsole [earlycon0] enabled
    [    0.000000] Memory policy: Data cache writealloc
    [    0.000000] efi: Getting EFI parameters from FDT:
    [    0.000000] efi: UEFI not found.
    [    0.000000] cma: Reserved 24 MiB at 0x00000000be400000
    [    0.000000] OMAP4: Map 0x00000000bfd00000 to (ptrval) for dram barrier
    [    0.000000] DRA752 ES2.0
    [    0.000000] random: get_random_bytes called from start_kernel+0xb0/0x480 with crng_init=0
    [    0.000000] percpu: Embedded 15 pages/cpu s32288 r8192 d20960 u61440
    [    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 259648
    [    0.000000] Kernel command line: console=ttyO2,115200 earlyprintk loglevel=3 mem=0x40000000 loglevel=7
    [    0.000000] Dentry cache hash table entries: 131072 (order: 8, 1048576 bytes)
    [    0.000000] Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
    [    0.000000] Memory: 994888K/1045504K available (8192K kernel code, 329K rwdata, 2644K rodata, 2048K init, 275K b)
    [    0.000000] Virtual kernel memory layout:
    [    0.000000]     vector  : 0xffff0000 - 0xffff1000   (   4 kB)
    [    0.000000]     fixmap  : 0xffc00000 - 0xfff00000   (3072 kB)
    [    0.000000]     vmalloc : 0xf0800000 - 0xff800000   ( 240 MB)
    [    0.000000]     lowmem  : 0xc0000000 - 0xf0000000   ( 768 MB)
    [    0.000000]     pkmap   : 0xbfe00000 - 0xc0000000   (   2 MB)
    [    0.000000]     modules : 0xbf000000 - 0xbfe00000   (  14 MB)
    [    0.000000]       .text : 0x(ptrval) - 0x(ptrval)   (10208 kB)
    [    0.000000]       .init : 0x(ptrval) - 0x(ptrval)   (2048 kB)
    [    0.000000]       .data : 0x(ptrval) - 0x(ptrval)   ( 330 kB)
    [    0.000000]        .bss : 0x(ptrval) - 0x(ptrval)   ( 276 kB)
    [    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1
    [    0.000000] rcu: Preemptible hierarchical RCU implementation.
    [    0.000000] rcu:     RCU priority boosting: priority 1 delay 500 ms.
    [    0.000000]  No expedited grace period (rcu_normal_after_boot).
    [    0.000000]  Tasks RCU enabled.
    [    0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
    [    0.000000] GIC: Using split EOI/Deactivate mode
    [    0.000000] ti_dt_clocks_register: missing clkctrl nodes, please update your dts.
    [    0.000000] OMAP clockevent source: timer1 at 32786 Hz
    [    0.000000] arch_timer: cp15 timer(s) running at 6.14MHz (phys).
    [    0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x16af5adb9, max_idle_ns: 44079520s
    [    0.000005] sched_clock: 56 bits at 6MHz, resolution 162ns, wraps every 4398046511023ns
    [    0.000012] Switching to timer-based delay loop, resolution 162ns
    [    0.000334] clocksource: 32k_counter: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 58327039986419 ns
    [    0.000337] OMAP clocksource: 32k_counter at 32768 Hz
    [    0.000742] Console: colour dummy device 80x30
    [    0.259629] WARNING: Your 'console=ttyO2' has been replaced by 'ttyS2'
    [    0.259632] This ensures that you still see kernel messages. Please
    [    0.259634] update your kernel commandline.
    [    0.259655] Calibrating delay loop (skipped), value calculated using timer frequency.. 12.29 BogoMIPS (lpj=61475)
    [    0.259663] pid_max: default: 32768 minimum: 301
    [    0.259798] Mount-cache hash table entries: 2048 (order: 1, 8192 bytes)
    [    0.259806] Mountpoint-cache hash table entries: 2048 (order: 1, 8192 bytes)
    [    0.260546] CPU: Testing write buffer coherency: ok
    [    0.260575] CPU0: Spectre v2: using ICIALLU workaround
    [    0.260816] /cpus/cpu@0 missing clock-frequency property
    [    0.323138] /cpus/cpu@1 missing clock-frequency property
    [    0.328588] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
    [    0.390201] Setting up static identity map for 0x80200000 - 0x80200060
    [    0.410175] rcu: Hierarchical SRCU implementation.
    [    0.470688] EFI services will not be available.
    [    0.490309] smp: Bringing up secondary CPUs ...
    [    0.610718] CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
    [    0.610721] CPU1: Spectre v2: using ICIALLU workaround
    [    0.610850] smp: Brought up 1 node, 2 CPUs
    [    0.626137] SMP: Total of 2 processors activated (24.59 BogoMIPS).
    [    0.632479] CPU: All CPU(s) started in HYP mode.
    [    0.637212] CPU: Virtualization extensions available.
    [    0.643069] devtmpfs: initialized
    [    0.680743] VFP support v0.3: implementor 41 architecture 4 part 30 variant f rev 0
    [    0.688926] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
    [    0.699021] futex hash table entries: 512 (order: 3, 32768 bytes)
    [    0.705830] pinctrl core: initialized pinctrl subsystem
    [    0.712018] DMI not present or invalid.
    [    0.716404] NET: Registered protocol family 16
    [    0.723660] DMA: preallocated 256 KiB pool for atomic coherent allocations
    [    0.731625] omap_hwmod: l3_main_2 using broken dt data from ocp
    [    0.756507] omap_hwmod: dma_system: no dt node
    [    0.761090] ------------[ cut here ]------------
    [    0.765837] WARNING: CPU: 0 PID: 1 at arch/arm/mach-omap2/omap_hwmod.c:2409 _init.constprop.22+0x1b0/0x4dc
    [    0.775754] omap_hwmod: dma_system: doesn't have mpu register target base
    [    0.782719] Modules linked in:
    [    0.785861] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.19.38-rt19 #1
    [    0.785864] Hardware name: Generic DRA74X (Flattened Device Tree)
    [    0.785866] Backtrace: 
    [    0.785881] [<c020c748>] (dump_backtrace) from [<c020ca80>] (show_stack+0x18/0x1c)
    [    0.785887]  r7:c0bb657c r6:60000013 r5:00000000 r4:c10505a4
    [    0.785897] [<c020ca68>] (show_stack) from [<c09a0684>] (dump_stack+0x90/0xa4)
    [    0.785905] [<c09a05f4>] (dump_stack) from [<c022d1a0>] (__warn+0xdc/0xf8)
    [    0.785910]  r7:c0bb657c r6:00000009 r5:00000000 r4:ef09dddc
    [    0.785916] [<c022d0c4>] (__warn) from [<c022cdbc>] (warn_slowpath_fmt+0x50/0x6c)
    [    0.785922]  r9:c0e48824 r8:00000000 r7:c10150f8 r6:00000000 r5:c0bb6b64 r4:c1007488
    [    0.785930] [<c022cd70>] (warn_slowpath_fmt) from [<c0e0cad0>] (_init.constprop.22+0x1b0/0x4dc)
    [    0.785934]  r3:c0bb7008 r2:c0bb6b64
    [    0.785938]  r5:00000000 r4:c10150c0
    [    0.785947] [<c0e0c920>] (_init.constprop.22) from [<c0e0cf2c>] (__omap_hwmod_setup_all+0x48/0x134)
    [    0.785953]  r10:c0e58320 r9:c0e48824 r8:00000000 r7:c0e0cee4 r6:ffffe000 r5:c100c728
    [    0.785955]  r4:c10150c0
    [    0.785964] [<c0e0cee4>] (__omap_hwmod_setup_all) from [<c02023fc>] (do_one_initcall+0x84/0x1b0)
    [    0.785967]  r5:c1007488 r4:c10525c0
    [    0.785975] [<c0202378>] (do_one_initcall) from [<c0e01048>] (kernel_init_freeable+0x214/0x2a8)
    [    0.785980]  r8:c0e48844 r7:c0e004f0 r6:c10525c0 r5:c10525c0 r4:00000003
    [    0.785988] [<c0e00e34>] (kernel_init_freeable) from [<c09b4c98>] (kernel_init+0x10/0x118)
    [    0.785993]  r10:00000000 r9:00000000 r8:00000000 r7:00000000 r6:00000000 r5:c09b4c88
    [    0.785996]  r4:00000000
    [    0.786003] [<c09b4c88>] (kernel_init) from [<c02010e0>] (ret_from_fork+0x14/0x34)
    [    0.786006] Exception stack(0xef09dfb0 to 0xef09dff8)
    [    0.786011] dfa0:                                     00000000 00000000 00000000 00000000
    [    0.786016] dfc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
    [    0.786020] dfe0: 00000000 00000000 00000000 00000000 00000013 00000000
    [    0.786024]  r5:c09b4c88 r4:00000000
    [    0.786027] ---[ end trace 0000000000000001 ]---
    [    0.994426] omap_hwmod: gpu: no dt node
    [    0.998359] ------------[ cut here ]------------
    [    1.003135] WARNING: CPU: 0 PID: 1 at arch/arm/mach-omap2/omap_hwmod.c:2409 _init.constprop.22+0x1b0/0x4dc
    [    1.013046] omap_hwmod: gpu: doesn't have mpu register target base
    [    1.019384] Modules linked in:
    [    1.022529] CPU: 0 PID: 1 Comm: swapper/0 Tainted: G        W         4.19.38-rt19 #1
    [    1.022531] Hardware name: Generic DRA74X (Flattened Device Tree)
    [    1.022534] Backtrace: 
    [    1.022544] [<c020c748>] (dump_backtrace) from [<c020ca80>] (show_stack+0x18/0x1c)
    [    1.022550]  r7:c0bb657c r6:60000013 r5:00000000 r4:c10505a4
    [    1.022558] [<c020ca68>] (show_stack) from [<c09a0684>] (dump_stack+0x90/0xa4)
    [    1.022565] [<c09a05f4>] (dump_stack) from [<c022d1a0>] (__warn+0xdc/0xf8)
    [    1.022570]  r7:c0bb657c r6:00000009 r5:00000000 r4:ef09dddc
    [    1.022575] [<c022d0c4>] (__warn) from [<c022cdbc>] (warn_slowpath_fmt+0x50/0x6c)
    [    1.022581]  r9:c0e48824 r8:00000000 r7:c101427c r6:00000000 r5:c0bb6b64 r4:c1007488
    [    1.022589] [<c022cd70>] (warn_slowpath_fmt) from [<c0e0cad0>] (_init.constprop.22+0x1b0/0x4dc)
    [    1.022593]  r3:c0bb8c00 r2:c0bb6b64
    [    1.022596]  r5:00000000 r4:c1014244
    [    1.022605] [<c0e0c920>] (_init.constprop.22) from [<c0e0cf2c>] (__omap_hwmod_setup_all+0x48/0x134)
    [    1.022610]  r10:c0e58320 r9:c0e48824 r8:00000000 r7:c0e0cee4 r6:ffffe000 r5:c100c728
    [    1.022612]  r4:c1014244
    [    1.022620] [<c0e0cee4>] (__omap_hwmod_setup_all) from [<c02023fc>] (do_one_initcall+0x84/0x1b0)
    [    1.022624]  r5:c1007488 r4:c10525c0
    [    1.022630] [<c0202378>] (do_one_initcall) from [<c0e01048>] (kernel_init_freeable+0x214/0x2a8)
    [    1.022635]  r8:c0e48844 r7:c0e004f0 r6:c10525c0 r5:c10525c0 r4:00000003
    [    1.022643] [<c0e00e34>] (kernel_init_freeable) from [<c09b4c98>] (kernel_init+0x10/0x118)
    [    1.022648]  r10:00000000 r9:00000000 r8:00000000 r7:00000000 r6:00000000 r5:c09b4c88
    [    1.022650]  r4:00000000
    [    1.022657] [<c09b4c88>] (kernel_init) from [<c02010e0>] (ret_from_fork+0x14/0x34)
    [    1.022661] Exception stack(0xef09dfb0 to 0xef09dff8)
    [    1.022664] dfa0:                                     00000000 00000000 00000000 00000000
    [    1.022670] dfc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
    [    1.022674] dfe0: 00000000 00000000 00000000 00000000 00000013 00000000
    [    1.022677]  r5:c09b4c88 r4:00000000
    [    1.022680] ---[ end trace 0000000000000002 ]---
    [    1.218178] omap_hwmod: hdq1w: no dt node
    [    1.222288] ------------[ cut here ]------------
    [    1.227028] WARNING: CPU: 0 PID: 1 at arch/arm/mach-omap2/omap_hwmod.c:2409 _init.constprop.22+0x1b0/0x4dc
    [    1.236927] omap_hwmod: hdq1w: doesn't have mpu register target base
    [    1.243447] Modules linked in:
    [    1.246587] CPU: 0 PID: 1 Comm: swapper/0 Tainted: G        W         4.19.38-rt19 #1
    [    1.246589] Hardware name: Generic DRA74X (Flattened Device Tree)
    [    1.246591] Backtrace: 
    [    1.246601] [<c020c748>] (dump_backtrace) from [<c020ca80>] (show_stack+0x18/0x1c)
    [    1.246607]  r7:c0bb657c r6:60000013 r5:00000000 r4:c10505a4
    [    1.246614] [<c020ca68>] (show_stack) from [<c09a0684>] (dump_stack+0x90/0xa4)
    [    1.246621] [<c09a05f4>] (dump_stack) from [<c022d1a0>] (__warn+0xdc/0xf8)
    [    1.246625]  r7:c0bb657c r6:00000009 r5:00000000 r4:ef09dddc
    [    1.246631] [<c022d0c4>] (__warn) from [<c022cdbc>] (warn_slowpath_fmt+0x50/0x6c)
    [    1.246636]  r9:c0e48824 r8:00000000 r7:c10141c0 r6:00000000 r5:c0bb6b64 r4:c1007488
    [    1.246644] [<c022cd70>] (warn_slowpath_fmt) from [<c0e0cad0>] (_init.constprop.22+0x1b0/0x4dc)
    [    1.246648]  r3:c0bb8be8 r2:c0bb6b64
    [    1.246651]  r5:00000000 r4:c1014188
    [    1.246659] [<c0e0c920>] (_init.constprop.22) from [<c0e0cf2c>] (__omap_hwmod_setup_all+0x48/0x134)
    [    1.246665]  r10:c0e58320 r9:c0e48824 r8:00000000 r7:c0e0cee4 r6:ffffe000 r5:c100c728
    [    1.246667]  r4:c1014188
    [    1.246675] [<c0e0cee4>] (__omap_hwmod_setup_all) from [<c02023fc>] (do_one_initcall+0x84/0x1b0)
    [    1.246678]  r5:c1007488 r4:c10525c0
    [    1.246685] [<c0202378>] (do_one_initcall) from [<c0e01048>] (kernel_init_freeable+0x214/0x2a8)
    [    1.246690]  r8:c0e48844 r7:c0e004f0 r6:c10525c0 r5:c10525c0 r4:00000003
    [    1.246698] [<c0e00e34>] (kernel_init_freeable) from [<c09b4c98>] (kernel_init+0x10/0x118)
    [    1.246703]  r10:00000000 r9:00000000 r8:00000000 r7:00000000 r6:00000000 r5:c09b4c88
    [    1.246705]  r4:00000000
    [    1.246712] [<c09b4c88>] (kernel_init) from [<c02010e0>] (ret_from_fork+0x14/0x34)
    [    1.246716] Exception stack(0xef09dfb0 to 0xef09dff8)
    [    1.246720] dfa0:                                     00000000 00000000 00000000 00000000
    [    1.246725] dfc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
    [    1.246730] dfe0: 00000000 00000000 00000000 00000000 00000013 00000000
    [    1.246733]  r5:c09b4c88 r4:00000000
    [    1.246736] ---[ end trace 0000000000000003 ]---
    [    1.471038] omap_hwmod: smartreflex_core: no dt node
    [    1.476131] ------------[ cut here ]------------
    [    1.480873] WARNING: CPU: 0 PID: 1 at arch/arm/mach-omap2/omap_hwmod.c:2409 _init.constprop.22+0x1b0/0x4dc
    [    1.490775] omap_hwmod: smartreflex_core: doesn't have mpu register target base
    [    1.498267] Modules linked in:
    [    1.501407] CPU: 0 PID: 1 Comm: swapper/0 Tainted: G        W         4.19.38-rt19 #1
    [    1.501410] Hardware name: Generic DRA74X (Flattened Device Tree)
    [    1.501412] Backtrace: 
    [    1.501422] [<c020c748>] (dump_backtrace) from [<c020ca80>] (show_stack+0x18/0x1c)
    [    1.501427]  r7:c0bb657c r6:60000013 r5:00000000 r4:c10505a4
    [    1.501435] [<c020ca68>] (show_stack) from [<c09a0684>] (dump_stack+0x90/0xa4)
    [    1.501442] [<c09a05f4>] (dump_stack) from [<c022d1a0>] (__warn+0xdc/0xf8)
    [    1.501447]  r7:c0bb657c r6:00000009 r5:00000000 r4:ef09dddc
    [    1.501453] [<c022d0c4>] (__warn) from [<c022cdbc>] (warn_slowpath_fmt+0x50/0x6c)
    [    1.501458]  r9:c0e48824 r8:00000000 r7:c10122a4 r6:00000000 r5:c0bb6b64 r4:c1007488
    [    1.501466] [<c022cd70>] (warn_slowpath_fmt) from [<c0e0cad0>] (_init.constprop.22+0x1b0/0x4dc)
    [    1.501469]  r3:c0bb8734 r2:c0bb6b64
    [    1.501472]  r5:00000000 r4:c101226c
    [    1.501481] [<c0e0c920>] (_init.constprop.22) from [<c0e0cf2c>] (__omap_hwmod_setup_all+0x48/0x134)
    [    1.501486]  r10:c0e58320 r9:c0e48824 r8:00000000 r7:c0e0cee4 r6:ffffe000 r5:c100c728
    [    1.501488]  r4:c101226c
    [    1.501497] [<c0e0cee4>] (__omap_hwmod_setup_all) from [<c02023fc>] (do_one_initcall+0x84/0x1b0)
    [    1.501500]  r5:c1007488 r4:c10525c0
    [    1.501506] [<c0202378>] (do_one_initcall) from [<c0e01048>] (kernel_init_freeable+0x214/0x2a8)
    [    1.501511]  r8:c0e48844 r7:c0e004f0 r6:c10525c0 r5:c10525c0 r4:00000003
    [    1.501519] [<c0e00e34>] (kernel_init_freeable) from [<c09b4c98>] (kernel_init+0x10/0x118)
    [    1.501524]  r10:00000000 r9:00000000 r8:00000000 r7:00000000 r6:00000000 r5:c09b4c88
    [    1.501526]  r4:00000000
    [    1.501533] [<c09b4c88>] (kernel_init) from [<c02010e0>] (ret_from_fork+0x14/0x34)
    [    1.501536] Exception stack(0xef09dfb0 to 0xef09dff8)
    [    1.501541] dfa0:                                     00000000 00000000 00000000 00000000
    [    1.501545] dfc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
    [    1.501550] dfe0: 00000000 00000000 00000000 00000000 00000013 00000000
    [    1.501553]  r5:c09b4c88 r4:00000000
    [    1.501586] ---[ end trace 0000000000000004 ]---
    [    1.697117] omap_hwmod: smartreflex_mpu: no dt node
    [    1.702129] ------------[ cut here ]------------
    [    1.706869] WARNING: CPU: 0 PID: 1 at arch/arm/mach-omap2/omap_hwmod.c:2409 _init.constprop.22+0x1b0/0x4dc
    [    1.716771] omap_hwmod: smartreflex_mpu: doesn't have mpu register target base
    [    1.724192] Modules linked in:
    [    1.727335] CPU: 0 PID: 1 Comm: swapper/0 Tainted: G        W         4.19.38-rt19 #1
    [    1.727337] Hardware name: Generic DRA74X (Flattened Device Tree)
    [    1.727339] Backtrace: 
    [    1.727349] [<c020c748>] (dump_backtrace) from [<c020ca80>] (show_stack+0x18/0x1c)
    [    1.727355]  r7:c0bb657c r6:60000013 r5:00000000 r4:c10505a4
    [    1.727362] [<c020ca68>] (show_stack) from [<c09a0684>] (dump_stack+0x90/0xa4)
    [    1.727368] [<c09a05f4>] (dump_stack) from [<c022d1a0>] (__warn+0xdc/0xf8)
    [    1.727373]  r7:c0bb657c r6:00000009 r5:00000000 r4:ef09dddc
    [    1.727378] [<c022d0c4>] (__warn) from [<c022cdbc>] (warn_slowpath_fmt+0x50/0x6c)
    [    1.727384]  r9:c0e48824 r8:00000000 r7:c101221c r6:00000000 r5:c0bb6b64 r4:c1007488
    [    1.727392] [<c022cd70>] (warn_slowpath_fmt) from [<c0e0cad0>] (_init.constprop.22+0x1b0/0x4dc)
    [    1.727395]  r3:c0bb8724 r2:c0bb6b64
    [    1.727398]  r5:00000000 r4:c10121e4
    [    1.727407] [<c0e0c920>] (_init.constprop.22) from [<c0e0cf2c>] (__omap_hwmod_setup_all+0x48/0x134)
    [    1.727412]  r10:c0e58320 r9:c0e48824 r8:00000000 r7:c0e0cee4 r6:ffffe000 r5:c100c728
    [    1.727414]  r4:c10121e4
    [    1.727422] [<c0e0cee4>] (__omap_hwmod_setup_all) from [<c02023fc>] (do_one_initcall+0x84/0x1b0)
    [    1.727426]  r5:c1007488 r4:c10525c0
    [    1.727432] [<c0202378>] (do_one_initcall) from [<c0e01048>] (kernel_init_freeable+0x214/0x2a8)
    [    1.727437]  r8:c0e48844 r7:c0e004f0 r6:c10525c0 r5:c10525c0 r4:00000003
    [    1.727445] [<c0e00e34>] (kernel_init_freeable) from [<c09b4c98>] (kernel_init+0x10/0x118)
    [    1.727450]  r10:00000000 r9:00000000 r8:00000000 r7:00000000 r6:00000000 r5:c09b4c88
    [    1.727452]  r4:00000000
    [    1.727459] [<c09b4c88>] (kernel_init) from [<c02010e0>] (ret_from_fork+0x14/0x34)
    [    1.727463] Exception stack(0xef09dfb0 to 0xef09dff8)
    [    1.727467] dfa0:                                     00000000 00000000 00000000 00000000
    [    1.727472] dfc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
    [    1.727476] dfe0: 00000000 00000000 00000000 00000000 00000013 00000000
    [    1.727479]  r5:c09b4c88 r4:00000000
    [    1.727482] ---[ end trace 0000000000000005 ]---
    [    1.944194] omap_hwmod: vpe: no dt node
    [    1.948127] ------------[ cut here ]------------
    [    1.952870] WARNING: CPU: 0 PID: 1 at arch/arm/mach-omap2/omap_hwmod.c:2409 _init.constprop.22+0x1b0/0x4dc
    [    1.962770] omap_hwmod: vpe: doesn't have mpu register target base
    [    1.969103] Modules linked in:
    [    1.972243] CPU: 0 PID: 1 Comm: swapper/0 Tainted: G        W         4.19.38-rt19 #1
    [    1.972246] Hardware name: Generic DRA74X (Flattened Device Tree)
    [    1.972248] Backtrace: 
    [    1.972258] [<c020c748>] (dump_backtrace) from [<c020ca80>] (show_stack+0x18/0x1c)
    [    1.972263]  r7:c0bb657c r6:60000013 r5:00000000 r4:c10505a4
    [    1.972271] [<c020ca68>] (show_stack) from [<c09a0684>] (dump_stack+0x90/0xa4)
    [    1.972277] [<c09a05f4>] (dump_stack) from [<c022d1a0>] (__warn+0xdc/0xf8)
    [    1.972282]  r7:c0bb657c r6:00000009 r5:00000000 r4:ef09dddc
    [    1.972287] [<c022d0c4>] (__warn) from [<c022cdbc>] (warn_slowpath_fmt+0x50/0x6c)
    [    1.972293]  r9:c0e48824 r8:00000000 r7:c1015a6c r6:00000000 r5:c0bb6b64 r4:c1007488
    [    1.972301] [<c022cd70>] (warn_slowpath_fmt) from [<c0e0cad0>] (_init.constprop.22+0x1b0/0x4dc)
    [    1.972305]  r3:c0bb8e90 r2:c0bb6b64
    [    1.972307]  r5:00000000 r4:c1015a34
    [    1.972316] [<c0e0c920>] (_init.constprop.22) from [<c0e0cf2c>] (__omap_hwmod_setup_all+0x48/0x134)
    [    1.972322]  r10:c0e58320 r9:c0e48824 r8:00000000 r7:c0e0cee4 r6:ffffe000 r5:c100c728
    [    1.972324]  r4:c1015a34
    [    1.972332] [<c0e0cee4>] (__omap_hwmod_setup_all) from [<c02023fc>] (do_one_initcall+0x84/0x1b0)
    [    1.972335]  r5:c1007488 r4:c10525c0
    [    1.972342] [<c0202378>] (do_one_initcall) from [<c0e01048>] (kernel_init_freeable+0x214/0x2a8)
    [    1.972346]  r8:c0e48844 r7:c0e004f0 r6:c10525c0 r5:c10525c0 r4:00000003
    [    1.972354] [<c0e00e34>] (kernel_init_freeable) from [<c09b4c98>] (kernel_init+0x10/0x118)
    [    1.972359]  r10:00000000 r9:00000000 r8:00000000 r7:00000000 r6:00000000 r5:c09b4c88
    [    1.972361]  r4:00000000
    [    1.972368] [<c09b4c88>] (kernel_init) from [<c02010e0>] (ret_from_fork+0x14/0x34)
    [    1.972371] Exception stack(0xef09dfb0 to 0xef09dff8)
    [    1.972376] dfa0:                                     00000000 00000000 00000000 00000000
    [    1.972380] dfc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
    [    1.972385] dfe0: 00000000 00000000 00000000 00000000 00000013 00000000
    [    1.972388]  r5:c09b4c88 r4:00000000
    [    1.972391] ---[ end trace 0000000000000006 ]---
    [    2.168060] omap_hwmod: vip1: no dt node
    [    2.172078] ------------[ cut here ]------------
    [    2.176820] WARNING: CPU: 0 PID: 1 at arch/arm/mach-omap2/omap_hwmod.c:2409 _init.constprop.22+0x1b0/0x4dc
    [    2.186721] omap_hwmod: vip1: doesn't have mpu register target base
    [    2.193144] Modules linked in:
    [    2.196283] CPU: 0 PID: 1 Comm: swapper/0 Tainted: G        W         4.19.38-rt19 #1
    [    2.196286] Hardware name: Generic DRA74X (Flattened Device Tree)
    [    2.196288] Backtrace: 
    [    2.196299] [<c020c748>] (dump_backtrace) from [<c020ca80>] (show_stack+0x18/0x1c)
    [    2.196305]  r7:c0bb657c r6:60000013 r5:00000000 r4:c10505a4
    [    2.196312] [<c020ca68>] (show_stack) from [<c09a0684>] (dump_stack+0x90/0xa4)
    [    2.196319] [<c09a05f4>] (dump_stack) from [<c022d1a0>] (__warn+0xdc/0xf8)
    [    2.196324]  r7:c0bb657c r6:00000009 r5:00000000 r4:ef09dddc
    [    2.196329] [<c022d0c4>] (__warn) from [<c022cdbc>] (warn_slowpath_fmt+0x50/0x6c)
    [    2.196334]  r9:c0e48824 r8:00000000 r7:c10159b0 r6:00000000 r5:c0bb6b64 r4:c1007488
    [    2.196342] [<c022cd70>] (warn_slowpath_fmt) from [<c0e0cad0>] (_init.constprop.22+0x1b0/0x4dc)
    [    2.196345]  r3:c0bb8e74 r2:c0bb6b64
    [    2.196348]  r5:00000000 r4:c1015978
    [    2.196357] [<c0e0c920>] (_init.constprop.22) from [<c0e0cf2c>] (__omap_hwmod_setup_all+0x48/0x134)
    [    2.196362]  r10:c0e58320 r9:c0e48824 r8:00000000 r7:c0e0cee4 r6:ffffe000 r5:c100c728
    [    2.196364]  r4:c1015978
    [    2.196372] [<c0e0cee4>] (__omap_hwmod_setup_all) from [<c02023fc>] (do_one_initcall+0x84/0x1b0)
    [    2.196375]  r5:c1007488 r4:c10525c0
    [    2.196382] [<c0202378>] (do_one_initcall) from [<c0e01048>] (kernel_init_freeable+0x214/0x2a8)
    [    2.196386]  r8:c0e48844 r7:c0e004f0 r6:c10525c0 r5:c10525c0 r4:00000003
    [    2.196394] [<c0e00e34>] (kernel_init_freeable) from [<c09b4c98>] (kernel_init+0x10/0x118)
    [    2.196399]  r10:00000000 r9:00000000 r8:00000000 r7:00000000 r6:00000000 r5:c09b4c88
    [    2.196401]  r4:00000000
    [    2.196408] [<c09b4c88>] (kernel_init) from [<c02010e0>] (ret_from_fork+0x14/0x34)
    [    2.196411] Exception stack(0xef09dfb0 to 0xef09dff8)
    [    2.196415] dfa0:                                     00000000 00000000 00000000 00000000
    [    2.196420] dfc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
    [    2.196425] dfe0: 00000000 00000000 00000000 00000000 00000013 00000000
    [    2.196428]  r5:c09b4c88 r4:00000000
    [    2.196431] ---[ end trace 0000000000000007 ]---
    [    2.398886] omap_hwmod: vip2: no dt node
    [    2.402910] ------------[ cut here ]------------
    [    2.407651] WARNING: CPU: 0 PID: 1 at arch/arm/mach-omap2/omap_hwmod.c:2409 _init.constprop.22+0x1b0/0x4dc
    [    2.417550] omap_hwmod: vip2: doesn't have mpu register target base
    [    2.423974] Modules linked in:
    [    2.427114] CPU: 0 PID: 1 Comm: swapper/0 Tainted: G        W         4.19.38-rt19 #1
    [    2.427117] Hardware name: Generic DRA74X (Flattened Device Tree)
    [    2.427119] Backtrace: 
    [    2.427129] [<c020c748>] (dump_backtrace) from [<c020ca80>] (show_stack+0x18/0x1c)
    [    2.427135]  r7:c0bb657c r6:60000013 r5:00000000 r4:c10505a4
    [    2.427142] [<c020ca68>] (show_stack) from [<c09a0684>] (dump_stack+0x90/0xa4)
    [    2.427149] [<c09a05f4>] (dump_stack) from [<c022d1a0>] (__warn+0xdc/0xf8)
    [    2.427153]  r7:c0bb657c r6:00000009 r5:00000000 r4:ef09dddc
    [    2.427159] [<c022d0c4>] (__warn) from [<c022cdbc>] (warn_slowpath_fmt+0x50/0x6c)
    [    2.427164]  r9:c0e48824 r8:00000000 r7:c101592c r6:00000000 r5:c0bb6b64 r4:c1007488
    [    2.427172] [<c022cd70>] (warn_slowpath_fmt) from [<c0e0cad0>] (_init.constprop.22+0x1b0/0x4dc)
    [    2.427176]  r3:c0bb8e6c r2:c0bb6b64
    [    2.427178]  r5:00000000 r4:c10158f4
    [    2.427187] [<c0e0c920>] (_init.constprop.22) from [<c0e0cf2c>] (__omap_hwmod_setup_all+0x48/0x134)
    [    2.427193]  r10:c0e58320 r9:c0e48824 r8:00000000 r7:c0e0cee4 r6:ffffe000 r5:c100c728
    [    2.427195]  r4:c10158f4
    [    2.427203] [<c0e0cee4>] (__omap_hwmod_setup_all) from [<c02023fc>] (do_one_initcall+0x84/0x1b0)
    [    2.427207]  r5:c1007488 r4:c10525c0
    [    2.427213] [<c0202378>] (do_one_initcall) from [<c0e01048>] (kernel_init_freeable+0x214/0x2a8)
    [    2.427217]  r8:c0e48844 r7:c0e004f0 r6:c10525c0 r5:c10525c0 r4:00000003
    [    2.427225] [<c0e00e34>] (kernel_init_freeable) from [<c09b4c98>] (kernel_init+0x10/0x118)
    [    2.427230]  r10:00000000 r9:00000000 r8:00000000 r7:00000000 r6:00000000 r5:c09b4c88
    [    2.427233]  r4:00000000
    [    2.427240] [<c09b4c88>] (kernel_init) from [<c02010e0>] (ret_from_fork+0x14/0x34)
    [    2.427243] Exception stack(0xef09dfb0 to 0xef09dff8)
    [    2.427248] dfa0:                                     00000000 00000000 00000000 00000000
    [    2.427252] dfc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
    [    2.427257] dfe0: 00000000 00000000 00000000 00000000 00000013 00000000
    [    2.427260]  r5:c09b4c88 r4:00000000
    [    2.427263] ---[ end trace 0000000000000008 ]---
    [    2.622878] omap_hwmod: vip3: no dt node
    [    2.626898] ------------[ cut here ]------------
    [    2.631638] WARNING: CPU: 0 PID: 1 at arch/arm/mach-omap2/omap_hwmod.c:2409 _init.constprop.22+0x1b0/0x4dc
    [    2.641552] omap_hwmod: vip3: doesn't have mpu register target base
    [    2.647994] Modules linked in:
    [    2.651135] CPU: 0 PID: 1 Comm: swapper/0 Tainted: G        W         4.19.38-rt19 #1
    [    2.651140] Hardware name: Generic DRA74X (Flattened Device Tree)
    [    2.651141] Backtrace: 
    [    2.651151] [<c020c748>] (dump_backtrace) from [<c020ca80>] (show_stack+0x18/0x1c)
    [    2.651157]  r7:c0bb657c r6:60000013 r5:00000000 r4:c10505a4
    [    2.651164] [<c020ca68>] (show_stack) from [<c09a0684>] (dump_stack+0x90/0xa4)
    [    2.651170] [<c09a05f4>] (dump_stack) from [<c022d1a0>] (__warn+0xdc/0xf8)
    [    2.651175]  r7:c0bb657c r6:00000009 r5:00000000 r4:ef09dddc
    [    2.651181] [<c022d0c4>] (__warn) from [<c022cdbc>] (warn_slowpath_fmt+0x50/0x6c)
    [    2.651186]  r9:c0e48824 r8:00000000 r7:c10158a8 r6:00000000 r5:c0bb6b64 r4:c1007488
    [    2.651194] [<c022cd70>] (warn_slowpath_fmt) from [<c0e0cad0>] (_init.constprop.22+0x1b0/0x4dc)
    [    2.651197]  r3:c0bb8e64 r2:c0bb6b64
    [    2.651200]  r5:00000000 r4:c1015870
    [    2.651208] [<c0e0c920>] (_init.constprop.22) from [<c0e0cf2c>] (__omap_hwmod_setup_all+0x48/0x134)
    [    2.651214]  r10:c0e58320 r9:c0e48824 r8:00000000 r7:c0e0cee4 r6:ffffe000 r5:c100c728
    [    2.651216]  r4:c1015870
    [    2.651224] [<c0e0cee4>] (__omap_hwmod_setup_all) from [<c02023fc>] (do_one_initcall+0x84/0x1b0)
    [    2.651227]  r5:c1007488 r4:c10525c0
    [    2.651234] [<c0202378>] (do_one_initcall) from [<c0e01048>] (kernel_init_freeable+0x214/0x2a8)
    [    2.651238]  r8:c0e48844 r7:c0e004f0 r6:c10525c0 r5:c10525c0 r4:00000003
    [    2.651246] [<c0e00e34>] (kernel_init_freeable) from [<c09b4c98>] (kernel_init+0x10/0x118)
    [    2.651251]  r10:00000000 r9:00000000 r8:00000000 r7:00000000 r6:00000000 r5:c09b4c88
    [    2.651253]  r4:00000000
    [    2.651260] [<c09b4c88>] (kernel_init) from [<c02010e0>] (ret_from_fork+0x14/0x34)
    [    2.651263] Exception stack(0xef09dfb0 to 0xef09dff8)
    [    2.651267] dfa0:                                     00000000 00000000 00000000 00000000
    [    2.651272] dfc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
    [    2.651276] dfe0: 00000000 00000000 00000000 00000000 00000013 00000000
    [    2.651279]  r5:c09b4c88 r4:00000000
    [    2.651282] ---[ end trace 0000000000000009 ]---
    [    2.937158] Unhandled fault: asynchronous external abort (0x1211) at 0x00000000
    [    2.937162] pgd = (ptrval)
    [    2.937164] [00000000] *pgd=80000080004003, *pmd=00000000
    [    2.937176] Internal error: : 1211 [#1] PREEMPT SMP ARM
    [    2.937178] Modules linked in:
    [    2.937186] CPU: 0 PID: 1 Comm: swapper/0 Tainted: G        W         4.19.38-rt19 #1
    [    2.937188] Hardware name: Generic DRA74X (Flattened Device Tree)
    [    2.937196] PC is at _enable_sysc+0x5c/0x25c
    [    2.937200] LR is at _enable_sysc+0x48/0x25c
    [    2.937204] pc : [<c021d908>]    lr : [<c021d8f4>]    psr: 40000013
    [    2.937207] sp : ef09de38  ip : ef09de38  fp : ef09de64
    [    2.937210] r10: c0e58320  r9 : c0e48824  r8 : 00000000
    [    2.937213] r7 : c1012900  r6 : 00000000  r5 : c1007488  r4 : c10123e8
    [    2.937216] r3 : c101246c  r2 : c101248c  r1 : 00000078  r0 : c10123e8
    [    2.937221] Flags: nZcv  IRQs on  FIQs on  Mode SVC_32  ISA ARM  Segment user
    [    2.937225] Control: 30c5387d  Table: 80003000  DAC: fffffffd
    [    2.937229] Process swapper/0 (pid: 1, stack limit = 0x(ptrval))
    [    2.937232] Stack: (0xef09de38 to 0xef09e000)
    [    2.937236] de20:                                                       c0224e90 c09b9e08
    [    2.937241] de40: ef09de64 ff23978d c10123e8 c1052c10 00000000 c1012900 ef09de8c ef09de68
    [    2.937246] de60: c021dc60 c021d8b8 c10123e8 c100ff70 c10123e8 c101240c c1007488 c1012420
    [    2.937252] de80: ef09debc ef09de90 c021e184 c021db14 ef09debc ef09dea0 00000008 ff23978d
    [    2.937257] dea0: c10123e8 c100c728 ffffe000 c0e0cee4 ef09ded4 ef09dec0 c0e0d004 c021dfd0
    [    2.937262] dec0: c10525c0 c1007488 ef09df4c ef09ded8 c02023fc c0e0cef0 00000000 c0bbb460
    [    2.937267] dee0: c0bbb440 c0bbb400 c0bc6a5c c1007488 00000000 c0bbb418 00000002 00000002
    [    2.937272] df00: 00000000 c0bb11e8 c0e004f0 c0c933f0 c1018960 efffcabb efffcac4 ff23978d
    [    2.937277] df20: c027ff88 ff23978d c10525c0 00000003 c10525c0 c10525c0 c0e004f0 c0e48844
    [    2.937282] df40: ef09df94 ef09df50 c0e01048 c0202384 00000002 00000002 00000000 c0e004f0
    [    2.937287] df60: c0c933f0 000000d1 c09b9e5c 00000000 c09b4c88 00000000 00000000 00000000
    [    2.937292] df80: 00000000 00000000 ef09dfac ef09df98 c09b4c98 c0e00e40 00000000 c09b4c88
    [    2.937297] dfa0: 00000000 ef09dfb0 c02010e0 c09b4c94 00000000 00000000 00000000 00000000
    [    2.937301] dfc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
    [    2.937306] dfe0: 00000000 00000000 00000000 00000000 00000013 00000000 00000000 00000000
    [    2.937307] Backtrace: 
    [    2.937316] [<c021d8ac>] (_enable_sysc) from [<c021dc60>] (_enable+0x158/0x284)
    [    2.937322]  r7:c1012900 r6:00000000 r5:c1052c10 r4:c10123e8
    [    2.937329] [<c021db08>] (_enable) from [<c021e184>] (_setup.part.16+0x1c0/0x4e0)
    [    2.937334]  r7:c1012420 r6:c1007488 r5:c101240c r4:c10123e8
    [    2.937343] [<c021dfc4>] (_setup.part.16) from [<c0e0d004>] (__omap_hwmod_setup_all+0x120/0x134)
    [    2.937347]  r7:c0e0cee4 r6:ffffe000 r5:c100c728 r4:c10123e8
    [    2.937356] [<c0e0cee4>] (__omap_hwmod_setup_all) from [<c02023fc>] (do_one_initcall+0x84/0x1b0)
    [    2.937359]  r5:c1007488 r4:c10525c0
    [    2.937366] [<c0202378>] (do_one_initcall) from [<c0e01048>] (kernel_init_freeable+0x214/0x2a8)
    [    2.937370]  r8:c0e48844 r7:c0e004f0 r6:c10525c0 r5:c10525c0 r4:00000003
    [    2.937378] [<c0e00e34>] (kernel_init_freeable) from [<c09b4c98>] (kernel_init+0x10/0x118)
    [    2.937384]  r10:00000000 r9:00000000 r8:00000000 r7:00000000 r6:00000000 r5:c09b4c88
    [    2.937386]  r4:00000000
    [    2.937393] [<c09b4c88>] (kernel_init) from [<c02010e0>] (ret_from_fork+0x14/0x34)
    [    2.937397] Exception stack(0xef09dfb0 to 0xef09dff8)
    [    2.937401] dfa0:                                     00000000 00000000 00000000 00000000
    [    2.937406] dfc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
    [    2.937410] dfe0: 00000000 00000000 00000000 00000000 00000013 00000000
    [    2.937413]  r5:c09b4c88 r4:00000000
    [    2.937420] Code: e3130080 1a000067 e5943004 e1a00004 (e5942044) 
    [    3.302369] ---[ end trace 000000000000000a ]---
    [    3.302436] Kernel panic - not syncing: Attempted to kill init! exitcode=0x0000000b
    [    3.302436] 
    [    3.302446] CPU1: stopping
    [    3.302452] CPU: 1 PID: 0 Comm: swapper/1 Tainted: G      D W         4.19.38-rt19 #1
    [    3.302454] Hardware name: Generic DRA74X (Flattened Device Tree)
    [    3.302456] Backtrace: 
    [    3.302467] [<c020c748>] (dump_backtrace) from [<c020ca80>] (show_stack+0x18/0x1c)
    [    3.302473]  r7:fa212000 r6:60000193 r5:00000000 r4:c10505a4
    [    3.302481] [<c020ca68>] (show_stack) from [<c09a0684>] (dump_stack+0x90/0xa4)
    [    3.302489] [<c09a05f4>] (dump_stack) from [<c020f1b8>] (handle_IPI+0x1bc/0x22c)
    [    3.302494]  r7:fa212000 r6:00000001 r5:00000000 r4:c1052840
    [    3.302505] [<c020effc>] (handle_IPI) from [<c05522a0>] (gic_handle_irq+0x94/0x98)
    [    3.302509]  r6:fa21200c r5:c102707c r4:c100796c
    [    3.302517] [<c055220c>] (gic_handle_irq) from [<c02019f8>] (__irq_svc+0x58/0xa0)
    [    3.302520] Exception stack(0xef0e3f28 to 0xef0e3f70)
    [    3.302525] 3f20:                   00000000 000007bc 00000000 c021a140 ffffe000 c10074bc
    [    3.302531] 3f40: c1007504 00000002 00000001 c10521d6 c0bbbc84 ef0e3f84 ef0e3f88 ef0e3f78
    [    3.302534] 3f60: c0208bf8 c0208bfc 60000013 ffffffff
    [    3.302540]  r9:ef0e2000 r8:00000001 r7:ef0e3f5c r6:ffffffff r5:60000013 r4:c0208bfc
    [    3.302550] [<c0208bbc>] (arch_cpu_idle) from [<c09b9870>] (default_idle_call+0x34/0x40)
    [    3.302558] [<c09b983c>] (default_idle_call) from [<c025b928>] (do_idle+0x110/0x180)
    [    3.302565] [<c025b818>] (do_idle) from [<c025bc84>] (cpu_startup_entry+0x20/0x24)
    [    3.302571]  r10:00000000 r9:412fc0f2 r8:80007000 r7:c1052848 r6:00000001 r5:ef0e2000
    [    3.302574]  r4:00000086 r3:ef0e2000
    [    3.302581] [<c025bc64>] (cpu_startup_entry) from [<c020ed54>] (secondary_start_kernel+0x178/0x180)
    [    3.302587] [<c020ebdc>] (secondary_start_kernel) from [<8020210c>] (0x8020210c)
    [    3.302592]  r7:c1052848 r6:30c0387d r5:00000000 r4:af05e880
    

     

     

    Here is the recompiled  DTS from DTB:

    /dts-v1/;
    
    / {
    	#address-cells = <0x2>;
    	#size-cells = <0x2>;
    	compatible = "ti,am572x-beagle-x15", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7";
    	interrupt-parent = <0x1>;
    	model = "TI AM5726 sec4";
    
    	chosen {
    		stdout-path = "/ocp/serial@48020000";
    		tick-timer = "/ocp/timer@48032000";
    	};
    
    	aliases {
    		i2c0 = "/ocp/i2c@48070000";
    		i2c1 = "/ocp/i2c@48072000";
    		i2c2 = "/ocp/i2c@48060000";
    		i2c3 = "/ocp/i2c@4807a000";
    		i2c4 = "/ocp/i2c@4807c000";
    		serial0 = "/ocp/serial@4806a000";
    		serial1 = "/ocp/serial@4806c000";
    		serial2 = "/ocp/serial@48020000";
    		serial3 = "/ocp/serial@4806e000";
    		serial4 = "/ocp/serial@48066000";
    		serial5 = "/ocp/serial@48068000";
    		serial6 = "/ocp/serial@48420000";
    		serial7 = "/ocp/serial@48422000";
    		serial8 = "/ocp/serial@48424000";
    		serial9 = "/ocp/serial@4ae2b000";
    		ethernet0 = "/ocp/ethernet@48484000/slave@48480200";
    		ethernet1 = "/ocp/ethernet@48484000/slave@48480300";
    		d_can0 = "/ocp/can@481cc000";
    		d_can1 = "/ocp/can@481d0000";
    		spi0 = "/ocp/qspi@4b300000";
    		usb0 = "/ocp/omap_dwc3_1@48880000/usb@48890000";
    		usb1 = "/ocp/omap_dwc3_2@488c0000/usb@488d0000";
    	};
    
    	timer {
    		compatible = "arm,armv7-timer";
    		interrupts = <0x1 0xd 0x308 0x1 0xe 0x308 0x1 0xb 0x308 0x1 0xa 0x308>;
    		interrupt-parent = <0x2>;
    	};
    
    	interrupt-controller@48211000 {
    		compatible = "arm,cortex-a15-gic";
    		interrupt-controller;
    		#interrupt-cells = <0x3>;
    		reg = <0x0 0x48211000 0x0 0x1000 0x0 0x48212000 0x0 0x2000 0x0 0x48214000 0x0 0x2000 0x0 0x48216000 0x0 0x2000>;
    		interrupts = <0x1 0x9 0x304>;
    		interrupt-parent = <0x2>;
    		phandle = <0x2>;
    	};
    
    	interrupt-controller@48281000 {
    		compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
    		interrupt-controller;
    		#interrupt-cells = <0x3>;
    		reg = <0x0 0x48281000 0x0 0x1000>;
    		interrupt-parent = <0x2>;
    		phandle = <0x7>;
    	};
    
    	cpus {
    		#address-cells = <0x1>;
    		#size-cells = <0x0>;
    
    		cpu@0 {
    			device_type = "cpu";
    			compatible = "arm,cortex-a15";
    			reg = <0x0>;
    			operating-points-v2 = <0x3>;
    			clocks = <0x4>;
    			clock-names = "cpu";
    			clock-latency = <0x493e0>;
    			cooling-min-level = <0x0>;
    			cooling-max-level = <0x2>;
    			#cooling-cells = <0x2>;
    			cpu0-supply = <0x5>;
    			voltage-tolerance = <0x1>;
    			phandle = <0xee>;
    		};
    
    		cpu@1 {
    			device_type = "cpu";
    			compatible = "arm,cortex-a15";
    			reg = <0x1>;
    			operating-points-v2 = <0x3>;
    		};
    	};
    
    	opp-table {
    		compatible = "operating-points-v2-ti-cpu";
    		syscon = <0x6>;
    		opp-shared;
    		phandle = <0x3>;
    
    		opp_nom-1000000000 {
    			opp-hz = <0x0 0x3b9aca00>;
    			opp-microvolt = <0x102ca0 0xcf850 0x118c30>;
    			opp-supported-hw = <0xff 0x1>;
    			opp-suspend;
    		};
    
    		opp_od-1176000000 {
    			opp-hz = <0x0 0x46185600>;
    			opp-microvolt = <0x11b340 0xd8108 0x11b340>;
    			opp-supported-hw = <0xff 0x2>;
    		};
    	};
    
    	soc {
    		compatible = "ti,omap-infra";
    
    		mpu {
    			compatible = "ti,omap5-mpu";
    			ti,hwmods = "mpu";
    		};
    	};
    
    	ocp {
    		compatible = "ti,dra7-l3-noc", "simple-bus";
    		#address-cells = <0x1>;
    		#size-cells = <0x1>;
    		ranges = <0x0 0x0 0x0 0xc0000000>;
    		ti,hwmods = "l3_main_1", "l3_main_2";
    		reg = <0x0 0x44000000 0x0 0x1000000 0x0 0x45000000 0x0 0x1000>;
    		interrupts-extended = <0x1 0x0 0x4 0x4 0x7 0x0 0xa 0x4>;
    		u-boot,dm-spl;
    
    		l4@4a000000 {
    			compatible = "ti,dra7-l4-cfg", "simple-bus";
    			#address-cells = <0x1>;
    			#size-cells = <0x1>;
    			ranges = <0x0 0x4a000000 0x22c000>;
    			u-boot,dm-spl;
    			phandle = <0xf1>;
    
    			scm@2000 {
    				compatible = "ti,dra7-scm-core", "simple-bus";
    				reg = <0x2000 0x2000>;
    				#address-cells = <0x1>;
    				#size-cells = <0x1>;
    				ranges = <0x0 0x2000 0x2000>;
    				u-boot,dm-spl;
    				phandle = <0xf2>;
    
    				scm_conf@0 {
    					compatible = "syscon", "simple-bus";
    					reg = <0x0 0x1400>;
    					#address-cells = <0x1>;
    					#size-cells = <0x1>;
    					ranges = <0x0 0x0 0x1400>;
    					u-boot,dm-spl;
    					phandle = <0x8>;
    
    					pbias_regulator@e00 {
    						compatible = "ti,pbias-dra7", "ti,pbias-omap";
    						reg = <0xe00 0x4>;
    						syscon = <0x8>;
    						phandle = <0xf3>;
    
    						pbias_mmc_omap5 {
    							regulator-name = "pbias_mmc_omap5";
    							regulator-min-microvolt = <0x1b7740>;
    							regulator-max-microvolt = <0x325aa0>;
    							phandle = <0xb4>;
    						};
    					};
    
    					clocks {
    						#address-cells = <0x1>;
    						#size-cells = <0x0>;
    						phandle = <0xf4>;
    
    						dss_deshdcp_clk@558 {
    							#clock-cells = <0x0>;
    							compatible = "ti,gate-clock";
    							clocks = <0x9>;
    							ti,bit-shift = <0x0>;
    							reg = <0x558>;
    							phandle = <0xf5>;
    						};
    
    						ehrpwm0_tbclk@558 {
    							#clock-cells = <0x0>;
    							compatible = "ti,gate-clock";
    							clocks = <0xa>;
    							ti,bit-shift = <0x14>;
    							reg = <0x558>;
    							phandle = <0xe8>;
    						};
    
    						ehrpwm1_tbclk@558 {
    							#clock-cells = <0x0>;
    							compatible = "ti,gate-clock";
    							clocks = <0xa>;
    							ti,bit-shift = <0x15>;
    							reg = <0x558>;
    							phandle = <0xe9>;
    						};
    
    						ehrpwm2_tbclk@558 {
    							#clock-cells = <0x0>;
    							compatible = "ti,gate-clock";
    							clocks = <0xa>;
    							ti,bit-shift = <0x16>;
    							reg = <0x558>;
    							phandle = <0xea>;
    						};
    
    						sys_32k_ck {
    							#clock-cells = <0x0>;
    							compatible = "ti,mux-clock";
    							clocks = <0xb 0xc 0xc 0xc>;
    							ti,bit-shift = <0x8>;
    							reg = <0x6c4>;
    							phandle = <0x50>;
    						};
    					};
    				};
    
    				pinmux@1400 {
    					compatible = "ti,dra7-padconf", "pinctrl-single";
    					reg = <0x1400 0x468>;
    					#address-cells = <0x1>;
    					#size-cells = <0x0>;
    					#pinctrl-cells = <0x1>;
    					#interrupt-cells = <0x1>;
    					interrupt-controller;
    					pinctrl-single,register-width = <0x20>;
    					pinctrl-single,function-mask = <0x3fffffff>;
    					phandle = <0xb0>;
    
    					mmc1_pins_default {
    						pinctrl-single,pins = <0x354 0x60000 0x358 0x60000 0x35c 0x60000 0x360 0x60000 0x364 0x60000 0x368 0x60000>;
    						phandle = <0xb5>;
    					};
    
    					mmc1_pins_sdr12 {
    						pinctrl-single,pins = <0x354 0x60000 0x358 0x60000 0x35c 0x60000 0x360 0x60000 0x364 0x60000 0x368 0x60000>;
    						phandle = <0xf6>;
    					};
    
    					mmc1_pins_hs {
    						pinctrl-single,pins = <0x354 0x601b0 0x358 0x601b0 0x35c 0x601b0 0x360 0x601b0 0x364 0x601b0 0x368 0x601b0>;
    						phandle = <0xb7>;
    					};
    
    					mmc1_pins_sdr25 {
    						pinctrl-single,pins = <0x354 0x601b0 0x358 0x601b0 0x35c 0x601b0 0x360 0x601b0 0x364 0x601b0 0x368 0x601b0>;
    						phandle = <0xf7>;
    					};
    
    					mmc1_pins_sdr50 {
    						pinctrl-single,pins = <0x354 0x601a0 0x358 0x601a0 0x35c 0x601a0 0x360 0x601a0 0x364 0x601a0 0x368 0x601a0>;
    						phandle = <0xf8>;
    					};
    
    					mmc1_pins_ddr50 {
    						pinctrl-single,pins = <0x354 0x60100 0x358 0x60100 0x35c 0x60100 0x360 0x60100 0x364 0x60100 0x368 0x60100>;
    						phandle = <0xf9>;
    					};
    
    					mmc1_pins_sdr104 {
    						pinctrl-single,pins = <0x354 0x60100 0x358 0x60100 0x35c 0x60100 0x360 0x60100 0x364 0x60100 0x368 0x60100>;
    						phandle = <0xfa>;
    					};
    
    					mmc2_pins_default {
    						pinctrl-single,pins = <0x9c 0x60001 0xb0 0x60001 0xa0 0x60001 0xa4 0x60001 0xa8 0x60001 0xac 0x60001 0x8c 0x60001 0x90 0x60001 0x94 0x60001 0x98 0x60001>;
    						phandle = <0xfb>;
    					};
    
    					mmc2_pins_hs {
    						pinctrl-single,pins = <0x9c 0x60001 0xb0 0x60001 0xa0 0x60001 0xa4 0x60001 0xa8 0x60001 0xac 0x60001 0x8c 0x60001 0x90 0x60001 0x94 0x60001 0x98 0x60001>;
    						phandle = <0xfc>;
    					};
    
    					mmc2_pins_ddr_3_3v_rev11 {
    						pinctrl-single,pins = <0x9c 0x60101 0xb0 0x60101 0xa0 0x60101 0xa4 0x60101 0xa8 0x60101 0xac 0x60101 0x8c 0x60101 0x90 0x60101 0x94 0x60101 0x98 0x60101>;
    						phandle = <0xfd>;
    					};
    
    					mmc2_pins_ddr_1_8v_rev11 {
    						pinctrl-single,pins = <0x9c 0x60101 0xb0 0x60101 0xa0 0x60101 0xa4 0x60101 0xa8 0x60101 0xac 0x60101 0x8c 0x60101 0x90 0x60101 0x94 0x60101 0x98 0x60101>;
    						phandle = <0xfe>;
    					};
    
    					mmc2_pins_ddr_rev20 {
    						pinctrl-single,pins = <0x9c 0x60001 0xb0 0x60001 0xa0 0x60001 0xa4 0x60001 0xa8 0x60001 0xac 0x60001 0x8c 0x60001 0x90 0x60001 0x94 0x60001 0x98 0x60001>;
    						phandle = <0xff>;
    					};
    
    					mmc2_pins_hs200 {
    						pinctrl-single,pins = <0x9c 0x60101 0xb0 0x60101 0xa0 0x60101 0xa4 0x60101 0xa8 0x60101 0xac 0x60101 0x8c 0x60101 0x90 0x60101 0x94 0x60101 0x98 0x60101>;
    						phandle = <0x100>;
    					};
    
    					mmc4_pins_default {
    						pinctrl-single,pins = <0x3e8 0x60103 0x3ec 0x60103 0x3f0 0x60103 0x3f4 0x60103 0x3f8 0x60103 0x3fc 0x60103>;
    						phandle = <0x101>;
    					};
    
    					mmc4_pins_hs {
    						pinctrl-single,pins = <0x3e8 0x60103 0x3ec 0x60103 0x3f0 0x60103 0x3f4 0x60103 0x3f8 0x60103 0x3fc 0x60103>;
    						phandle = <0x102>;
    					};
    
    					mmc3_pins_default {
    						pinctrl-single,pins = <0x37c 0x60000 0x380 0x60000 0x384 0x60000 0x388 0x60000 0x38c 0x60000 0x390 0x60000>;
    						phandle = <0x103>;
    					};
    
    					mmc3_pins_hs {
    						pinctrl-single,pins = <0x37c 0x60000 0x380 0x60000 0x384 0x60000 0x388 0x60000 0x38c 0x60000 0x390 0x60000>;
    						phandle = <0x104>;
    					};
    
    					mmc3_pins_sdr12 {
    						pinctrl-single,pins = <0x37c 0x60000 0x380 0x60000 0x384 0x60000 0x388 0x60000 0x38c 0x60000 0x390 0x60000>;
    						phandle = <0x105>;
    					};
    
    					mmc3_pins_sdr25 {
    						pinctrl-single,pins = <0x37c 0x60000 0x380 0x60000 0x384 0x60000 0x388 0x60000 0x38c 0x60000 0x390 0x60000>;
    						phandle = <0x106>;
    					};
    
    					mmc3_pins_sdr50 {
    						pinctrl-single,pins = <0x37c 0x60100 0x380 0x60100 0x384 0x60100 0x388 0x60100 0x38c 0x60100 0x390 0x60100>;
    						phandle = <0x107>;
    					};
    
    					mmc4_pins_sdr12 {
    						pinctrl-single,pins = <0x3e8 0x60103 0x3ec 0x60103 0x3f0 0x60103 0x3f4 0x60103 0x3f8 0x60103 0x3fc 0x60103>;
    						phandle = <0x108>;
    					};
    
    					mmc4_pins_sdr25 {
    						pinctrl-single,pins = <0x3e8 0x60103 0x3ec 0x60103 0x3f0 0x60103 0x3f4 0x60103 0x3f8 0x60103 0x3fc 0x60103>;
    						phandle = <0x109>;
    					};
    				};
    
    				scm_conf@1c04 {
    					compatible = "syscon";
    					reg = <0x1c04 0x20>;
    					#syscon-cells = <0x2>;
    					phandle = <0xaa>;
    				};
    
    				scm_conf@1c24 {
    					compatible = "syscon";
    					reg = <0x1c24 0x24>;
    					phandle = <0xbc>;
    				};
    
    				dma-router@b78 {
    					compatible = "ti,dra7-dma-crossbar";
    					reg = <0xb78 0xfc>;
    					#dma-cells = <0x1>;
    					dma-requests = <0xcd>;
    					ti,dma-safe-map = <0x0>;
    					dma-masters = <0xd>;
    					phandle = <0xaf>;
    				};
    
    				dma-router@c78 {
    					compatible = "ti,dra7-dma-crossbar";
    					reg = <0xc78 0x7c>;
    					#dma-cells = <0x2>;
    					dma-requests = <0xcc>;
    					ti,dma-safe-map = <0x0>;
    					dma-masters = <0xe>;
    					phandle = <0xcd>;
    				};
    			};
    
    			cm_core_aon@5000 {
    				compatible = "ti,dra7-cm-core-aon";
    				reg = <0x5000 0x2000>;
    				phandle = <0x10a>;
    
    				clocks {
    					#address-cells = <0x1>;
    					#size-cells = <0x0>;
    					phandle = <0x10b>;
    
    					atl_clkin0_ck {
    						#clock-cells = <0x0>;
    						compatible = "ti,dra7-atl-clock";
    						clocks = <0xf>;
    						phandle = <0x43>;
    					};
    
    					atl_clkin1_ck {
    						#clock-cells = <0x0>;
    						compatible = "ti,dra7-atl-clock";
    						clocks = <0xf>;
    						phandle = <0x42>;
    					};
    
    					atl_clkin2_ck {
    						#clock-cells = <0x0>;
    						compatible = "ti,dra7-atl-clock";
    						clocks = <0xf>;
    						phandle = <0x41>;
    					};
    
    					atl_clkin3_ck {
    						#clock-cells = <0x0>;
    						compatible = "ti,dra7-atl-clock";
    						clocks = <0xf>;
    						phandle = <0x40>;
    					};
    
    					hdmi_clkin_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x0>;
    						phandle = <0x2f>;
    					};
    
    					mlb_clkin_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x0>;
    						phandle = <0xa5>;
    					};
    
    					mlbp_clkin_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x0>;
    						phandle = <0xa6>;
    					};
    
    					pciesref_acs_clk_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x5f5e100>;
    						phandle = <0x5a>;
    					};
    
    					ref_clkin0_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x0>;
    						phandle = <0x45>;
    					};
    
    					ref_clkin1_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x0>;
    						phandle = <0x46>;
    					};
    
    					ref_clkin2_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x0>;
    						phandle = <0x47>;
    					};
    
    					ref_clkin3_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x0>;
    						phandle = <0x48>;
    					};
    
    					rmii_clk_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x0>;
    						phandle = <0x71>;
    					};
    
    					sdvenc_clkin_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x0>;
    						phandle = <0x10c>;
    					};
    
    					secure_32k_clk_src_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x8000>;
    						phandle = <0x8f>;
    					};
    
    					sys_clk32_crystal_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x8000>;
    						phandle = <0xb>;
    					};
    
    					sys_clk32_pseudo_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x10>;
    						clock-mult = <0x1>;
    						clock-div = <0x262>;
    						phandle = <0xc>;
    					};
    
    					virt_12000000_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0xb71b00>;
    						phandle = <0x7f>;
    					};
    
    					virt_13000000_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0xc65d40>;
    						phandle = <0x10d>;
    					};
    
    					virt_16800000_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x1005900>;
    						phandle = <0x81>;
    					};
    
    					virt_19200000_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x124f800>;
    						phandle = <0x82>;
    					};
    
    					virt_20000000_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x1312d00>;
    						phandle = <0x80>;
    					};
    
    					virt_26000000_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x18cba80>;
    						phandle = <0x83>;
    					};
    
    					virt_27000000_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x19bfcc0>;
    						phandle = <0x84>;
    					};
    
    					virt_38400000_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x249f000>;
    						phandle = <0x85>;
    					};
    
    					sys_clkin2 {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x1588800>;
    						phandle = <0x44>;
    					};
    
    					usb_otg_clkin_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x0>;
    						phandle = <0x8c>;
    					};
    
    					video1_clkin_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x0>;
    						phandle = <0x39>;
    					};
    
    					video1_m2_clkin_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x0>;
    						phandle = <0x2e>;
    					};
    
    					video2_clkin_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x0>;
    						phandle = <0x3a>;
    					};
    
    					video2_m2_clkin_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x0>;
    						phandle = <0x2d>;
    					};
    
    					dpll_abe_ck@1e0 {
    						#clock-cells = <0x0>;
    						compatible = "ti,omap4-dpll-m4xen-clock";
    						clocks = <0x11 0x12>;
    						reg = <0x1e0 0x1e4 0x1ec 0x1e8>;
    						phandle = <0x13>;
    					};
    
    					dpll_abe_x2_ck {
    						#clock-cells = <0x0>;
    						compatible = "ti,omap4-dpll-x2-clock";
    						clocks = <0x13>;
    						phandle = <0x14>;
    					};
    
    					dpll_abe_m2x2_ck@1f0 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x14>;
    						ti,max-div = <0x1f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x1f0>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0x15>;
    					};
    
    					abe_clk@108 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x15>;
    						ti,max-div = <0x4>;
    						reg = <0x108>;
    						ti,index-power-of-two;
    						phandle = <0x87>;
    					};
    
    					dpll_abe_m2_ck@1f0 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x13>;
    						ti,max-div = <0x1f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x1f0>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0x6f>;
    					};
    
    					dpll_abe_m3x2_ck@1f4 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x14>;
    						ti,max-div = <0x1f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x1f4>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0x16>;
    					};
    
    					dpll_core_byp_mux@12c {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x10 0x16>;
    						ti,bit-shift = <0x17>;
    						reg = <0x12c>;
    						phandle = <0x17>;
    					};
    
    					dpll_core_ck@120 {
    						#clock-cells = <0x0>;
    						compatible = "ti,omap4-dpll-core-clock";
    						clocks = <0x10 0x17>;
    						reg = <0x120 0x124 0x12c 0x128>;
    						phandle = <0x18>;
    					};
    
    					dpll_core_x2_ck {
    						#clock-cells = <0x0>;
    						compatible = "ti,omap4-dpll-x2-clock";
    						clocks = <0x18>;
    						phandle = <0x19>;
    					};
    
    					dpll_core_h12x2_ck@13c {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x19>;
    						ti,max-div = <0x3f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x13c>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0x1a>;
    					};
    
    					mpu_dpll_hs_clk_div {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x1a>;
    						clock-mult = <0x1>;
    						clock-div = <0x1>;
    						phandle = <0x1b>;
    					};
    
    					dpll_mpu_ck@160 {
    						#clock-cells = <0x0>;
    						compatible = "ti,omap5-mpu-dpll-clock";
    						clocks = <0x10 0x1b>;
    						reg = <0x160 0x164 0x16c 0x168>;
    						phandle = <0x4>;
    					};
    
    					dpll_mpu_m2_ck@170 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x4>;
    						ti,max-div = <0x1f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x170>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0x1c>;
    					};
    
    					mpu_dclk_div {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x1c>;
    						clock-mult = <0x1>;
    						clock-div = <0x1>;
    						phandle = <0x93>;
    					};
    
    					dsp_dpll_hs_clk_div {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x1a>;
    						clock-mult = <0x1>;
    						clock-div = <0x1>;
    						phandle = <0x1d>;
    					};
    
    					dpll_dsp_byp_mux@240 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x10 0x1d>;
    						ti,bit-shift = <0x17>;
    						reg = <0x240>;
    						phandle = <0x1e>;
    					};
    
    					dpll_dsp_ck@234 {
    						#clock-cells = <0x0>;
    						compatible = "ti,omap4-dpll-clock";
    						clocks = <0x10 0x1e>;
    						reg = <0x234 0x238 0x240 0x23c>;
    						assigned-clocks = <0x1f>;
    						assigned-clock-rates = <0x23c34600>;
    						phandle = <0x1f>;
    					};
    
    					dpll_dsp_m2_ck@244 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x1f>;
    						ti,max-div = <0x1f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x244>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						assigned-clocks = <0x20>;
    						assigned-clock-rates = <0x23c34600>;
    						phandle = <0x20>;
    					};
    
    					iva_dpll_hs_clk_div {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x1a>;
    						clock-mult = <0x1>;
    						clock-div = <0x1>;
    						phandle = <0x21>;
    					};
    
    					dpll_iva_byp_mux@1ac {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x10 0x21>;
    						ti,bit-shift = <0x17>;
    						reg = <0x1ac>;
    						phandle = <0x22>;
    					};
    
    					dpll_iva_ck@1a0 {
    						#clock-cells = <0x0>;
    						compatible = "ti,omap4-dpll-clock";
    						clocks = <0x10 0x22>;
    						reg = <0x1a0 0x1a4 0x1ac 0x1a8>;
    						assigned-clocks = <0x23>;
    						assigned-clock-rates = <0x45707d40>;
    						phandle = <0x23>;
    					};
    
    					dpll_iva_m2_ck@1b0 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x23>;
    						ti,max-div = <0x1f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x1b0>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						assigned-clocks = <0x24>;
    						assigned-clock-rates = <0x17257f16>;
    						phandle = <0x24>;
    					};
    
    					iva_dclk {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x24>;
    						clock-mult = <0x1>;
    						clock-div = <0x1>;
    						phandle = <0x95>;
    					};
    
    					dpll_gpu_byp_mux@2e4 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x10 0x16>;
    						ti,bit-shift = <0x17>;
    						reg = <0x2e4>;
    						phandle = <0x25>;
    					};
    
    					dpll_gpu_ck@2d8 {
    						#clock-cells = <0x0>;
    						compatible = "ti,omap4-dpll-clock";
    						clocks = <0x10 0x25>;
    						reg = <0x2d8 0x2dc 0x2e4 0x2e0>;
    						assigned-clocks = <0x26>;
    						assigned-clock-rates = <0x4c1d7940>;
    						phandle = <0x26>;
    					};
    
    					dpll_gpu_m2_ck@2e8 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x26>;
    						ti,max-div = <0x1f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x2e8>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						assigned-clocks = <0x27>;
    						assigned-clock-rates = <0x195f286b>;
    						phandle = <0x27>;
    					};
    
    					dpll_core_m2_ck@130 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x18>;
    						ti,max-div = <0x1f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x130>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0x28>;
    					};
    
    					core_dpll_out_dclk_div {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x28>;
    						clock-mult = <0x1>;
    						clock-div = <0x1>;
    						phandle = <0x97>;
    					};
    
    					dpll_ddr_byp_mux@21c {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x10 0x16>;
    						ti,bit-shift = <0x17>;
    						reg = <0x21c>;
    						phandle = <0x29>;
    					};
    
    					dpll_ddr_ck@210 {
    						#clock-cells = <0x0>;
    						compatible = "ti,omap4-dpll-clock";
    						clocks = <0x10 0x29>;
    						reg = <0x210 0x214 0x21c 0x218>;
    						phandle = <0x2a>;
    					};
    
    					dpll_ddr_m2_ck@220 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x2a>;
    						ti,max-div = <0x1f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x220>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0x89>;
    					};
    
    					dpll_gmac_byp_mux@2b4 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x10 0x16>;
    						ti,bit-shift = <0x17>;
    						reg = <0x2b4>;
    						phandle = <0x2b>;
    					};
    
    					dpll_gmac_ck@2a8 {
    						#clock-cells = <0x0>;
    						compatible = "ti,omap4-dpll-clock";
    						clocks = <0x10 0x2b>;
    						reg = <0x2a8 0x2ac 0x2b4 0x2b0>;
    						phandle = <0x2c>;
    					};
    
    					dpll_gmac_m2_ck@2b8 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x2c>;
    						ti,max-div = <0x1f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x2b8>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0x8a>;
    					};
    
    					video2_dclk_div {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x2d>;
    						clock-mult = <0x1>;
    						clock-div = <0x1>;
    						phandle = <0x99>;
    					};
    
    					video1_dclk_div {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x2e>;
    						clock-mult = <0x1>;
    						clock-div = <0x1>;
    						phandle = <0x9a>;
    					};
    
    					hdmi_dclk_div {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x2f>;
    						clock-mult = <0x1>;
    						clock-div = <0x1>;
    						phandle = <0x9b>;
    					};
    
    					per_dpll_hs_clk_div {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x16>;
    						clock-mult = <0x1>;
    						clock-div = <0x2>;
    						phandle = <0x5e>;
    					};
    
    					usb_dpll_hs_clk_div {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x16>;
    						clock-mult = <0x1>;
    						clock-div = <0x3>;
    						phandle = <0x62>;
    					};
    
    					eve_dpll_hs_clk_div {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x1a>;
    						clock-mult = <0x1>;
    						clock-div = <0x1>;
    						phandle = <0x30>;
    					};
    
    					dpll_eve_byp_mux@290 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x10 0x30>;
    						ti,bit-shift = <0x17>;
    						reg = <0x290>;
    						phandle = <0x31>;
    					};
    
    					dpll_eve_ck@284 {
    						#clock-cells = <0x0>;
    						compatible = "ti,omap4-dpll-clock";
    						clocks = <0x10 0x31>;
    						reg = <0x284 0x288 0x290 0x28c>;
    						phandle = <0x32>;
    					};
    
    					dpll_eve_m2_ck@294 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x32>;
    						ti,max-div = <0x1f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x294>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0x33>;
    					};
    
    					eve_dclk_div {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x33>;
    						clock-mult = <0x1>;
    						clock-div = <0x1>;
    						phandle = <0xa4>;
    					};
    
    					dpll_core_h13x2_ck@140 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x19>;
    						ti,max-div = <0x3f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x140>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0x10e>;
    					};
    
    					dpll_core_h14x2_ck@144 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x19>;
    						ti,max-div = <0x3f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x144>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0x72>;
    					};
    
    					dpll_core_h22x2_ck@154 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x19>;
    						ti,max-div = <0x3f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x154>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0x3b>;
    					};
    
    					dpll_core_h23x2_ck@158 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x19>;
    						ti,max-div = <0x3f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x158>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0x7e>;
    					};
    
    					dpll_core_h24x2_ck@15c {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x19>;
    						ti,max-div = <0x3f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x15c>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0x10f>;
    					};
    
    					dpll_ddr_x2_ck {
    						#clock-cells = <0x0>;
    						compatible = "ti,omap4-dpll-x2-clock";
    						clocks = <0x2a>;
    						phandle = <0x34>;
    					};
    
    					dpll_ddr_h11x2_ck@228 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x34>;
    						ti,max-div = <0x3f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x228>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0x110>;
    					};
    
    					dpll_dsp_x2_ck {
    						#clock-cells = <0x0>;
    						compatible = "ti,omap4-dpll-x2-clock";
    						clocks = <0x1f>;
    						phandle = <0x35>;
    					};
    
    					dpll_dsp_m3x2_ck@248 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x35>;
    						ti,max-div = <0x1f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x248>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						assigned-clocks = <0x36>;
    						assigned-clock-rates = <0x17d78400>;
    						phandle = <0x36>;
    					};
    
    					dpll_gmac_x2_ck {
    						#clock-cells = <0x0>;
    						compatible = "ti,omap4-dpll-x2-clock";
    						clocks = <0x2c>;
    						phandle = <0x37>;
    					};
    
    					dpll_gmac_h11x2_ck@2c0 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x37>;
    						ti,max-div = <0x3f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x2c0>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0x38>;
    					};
    
    					dpll_gmac_h12x2_ck@2c4 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x37>;
    						ti,max-div = <0x3f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x2c4>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0x111>;
    					};
    
    					dpll_gmac_h13x2_ck@2c8 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x37>;
    						ti,max-div = <0x3f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x2c8>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0x112>;
    					};
    
    					dpll_gmac_m3x2_ck@2bc {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x37>;
    						ti,max-div = <0x1f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x2bc>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0x113>;
    					};
    
    					gmii_m_clk_div {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x38>;
    						clock-mult = <0x1>;
    						clock-div = <0x2>;
    						phandle = <0x114>;
    					};
    
    					hdmi_clk2_div {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x2f>;
    						clock-mult = <0x1>;
    						clock-div = <0x1>;
    						phandle = <0x4e>;
    					};
    
    					hdmi_div_clk {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x2f>;
    						clock-mult = <0x1>;
    						clock-div = <0x1>;
    						phandle = <0x54>;
    					};
    
    					l3_iclk_div@100 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						ti,max-div = <0x2>;
    						ti,bit-shift = <0x4>;
    						reg = <0x100>;
    						clocks = <0x1a>;
    						ti,index-power-of-two;
    						phandle = <0x9>;
    					};
    
    					l4_root_clk_div {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x9>;
    						clock-mult = <0x1>;
    						clock-div = <0x2>;
    						phandle = <0xa>;
    					};
    
    					video1_clk2_div {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x39>;
    						clock-mult = <0x1>;
    						clock-div = <0x1>;
    						phandle = <0x4c>;
    					};
    
    					video1_div_clk {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x39>;
    						clock-mult = <0x1>;
    						clock-div = <0x1>;
    						phandle = <0x52>;
    					};
    
    					video2_clk2_div {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x3a>;
    						clock-mult = <0x1>;
    						clock-div = <0x1>;
    						phandle = <0x4d>;
    					};
    
    					video2_div_clk {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x3a>;
    						clock-mult = <0x1>;
    						clock-div = <0x1>;
    						phandle = <0x53>;
    					};
    
    					ipu1_gfclk_mux@520 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x15 0x3b>;
    						ti,bit-shift = <0x18>;
    						reg = <0x520>;
    						assigned-clocks = <0x3c>;
    						assigned-clock-parents = <0x3b>;
    						phandle = <0x3c>;
    					};
    
    					mcasp1_ahclkr_mux@550 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x3d 0x3e 0x3f 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4a>;
    						ti,bit-shift = <0x1c>;
    						reg = <0x550>;
    						phandle = <0xd0>;
    					};
    
    					mcasp1_ahclkx_mux@550 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x3d 0x3e 0x3f 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4a>;
    						ti,bit-shift = <0x18>;
    						reg = <0x550>;
    						phandle = <0xcf>;
    					};
    
    					mcasp1_aux_gfclk_mux@550 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x4b 0x4c 0x4d 0x4e>;
    						ti,bit-shift = <0x16>;
    						reg = <0x550>;
    						phandle = <0xce>;
    					};
    
    					timer5_gfclk_mux@558 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x4f 0x50 0x44 0x45 0x46 0x47 0x48 0x51 0x52 0x53 0x54 0x55>;
    						ti,bit-shift = <0x18>;
    						reg = <0x558>;
    						phandle = <0x115>;
    					};
    
    					timer6_gfclk_mux@560 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x4f 0x50 0x44 0x45 0x46 0x47 0x48 0x51 0x52 0x53 0x54 0x55>;
    						ti,bit-shift = <0x18>;
    						reg = <0x560>;
    						phandle = <0x116>;
    					};
    
    					timer7_gfclk_mux@568 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x4f 0x50 0x44 0x45 0x46 0x47 0x48 0x51 0x52 0x53 0x54 0x55>;
    						ti,bit-shift = <0x18>;
    						reg = <0x568>;
    						phandle = <0x117>;
    					};
    
    					timer8_gfclk_mux@570 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x4f 0x50 0x44 0x45 0x46 0x47 0x48 0x51 0x52 0x53 0x54 0x55>;
    						ti,bit-shift = <0x18>;
    						reg = <0x570>;
    						phandle = <0x118>;
    					};
    
    					uart6_gfclk_mux@580 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x56 0x57>;
    						ti,bit-shift = <0x18>;
    						reg = <0x580>;
    						phandle = <0x119>;
    					};
    
    					dummy_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x0>;
    						phandle = <0x11a>;
    					};
    				};
    
    				clockdomains {
    					phandle = <0x11b>;
    				};
    			};
    
    			cm_core@8000 {
    				compatible = "ti,dra7-cm-core";
    				reg = <0x8000 0x3000>;
    				phandle = <0x11c>;
    
    				clocks {
    					#address-cells = <0x1>;
    					#size-cells = <0x0>;
    					phandle = <0x11d>;
    
    					dpll_pcie_ref_ck@200 {
    						#clock-cells = <0x0>;
    						compatible = "ti,omap4-dpll-clock";
    						clocks = <0x10 0x10>;
    						reg = <0x200 0x204 0x20c 0x208>;
    						phandle = <0x58>;
    					};
    
    					dpll_pcie_ref_m2ldo_ck@210 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x58>;
    						ti,max-div = <0x1f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x210>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0x59>;
    					};
    
    					apll_pcie_in_clk_mux@4ae06118 {
    						compatible = "ti,mux-clock";
    						clocks = <0x59 0x5a>;
    						#clock-cells = <0x0>;
    						reg = <0x21c 0x4>;
    						ti,bit-shift = <0x7>;
    						phandle = <0x5b>;
    					};
    
    					apll_pcie_ck@21c {
    						#clock-cells = <0x0>;
    						compatible = "ti,dra7-apll-clock";
    						clocks = <0x5b 0x58>;
    						reg = <0x21c 0x220>;
    						phandle = <0x5c>;
    					};
    
    					optfclk_pciephy1_32khz@4a0093b0 {
    						compatible = "ti,gate-clock";
    						clocks = <0x50>;
    						#clock-cells = <0x0>;
    						reg = <0x13b0>;
    						ti,bit-shift = <0x8>;
    						phandle = <0xbd>;
    					};
    
    					optfclk_pciephy2_32khz@4a0093b8 {
    						compatible = "ti,gate-clock";
    						clocks = <0x50>;
    						#clock-cells = <0x0>;
    						reg = <0x13b8>;
    						ti,bit-shift = <0x8>;
    						phandle = <0xc0>;
    					};
    
    					optfclk_pciephy_div@4a00821c {
    						compatible = "ti,divider-clock";
    						clocks = <0x5c>;
    						#clock-cells = <0x0>;
    						reg = <0x21c>;
    						ti,dividers = <0x2 0x1>;
    						ti,bit-shift = <0x8>;
    						ti,max-div = <0x2>;
    						phandle = <0x5d>;
    					};
    
    					optfclk_pciephy1_clk@4a0093b0 {
    						compatible = "ti,gate-clock";
    						clocks = <0x5c>;
    						#clock-cells = <0x0>;
    						reg = <0x13b0>;
    						ti,bit-shift = <0x9>;
    						phandle = <0xbe>;
    					};
    
    					optfclk_pciephy2_clk@4a0093b8 {
    						compatible = "ti,gate-clock";
    						clocks = <0x5c>;
    						#clock-cells = <0x0>;
    						reg = <0x13b8>;
    						ti,bit-shift = <0x9>;
    						phandle = <0xc1>;
    					};
    
    					optfclk_pciephy1_div_clk@4a0093b0 {
    						compatible = "ti,gate-clock";
    						clocks = <0x5d>;
    						#clock-cells = <0x0>;
    						reg = <0x13b0>;
    						ti,bit-shift = <0xa>;
    						phandle = <0xbf>;
    					};
    
    					optfclk_pciephy2_div_clk@4a0093b8 {
    						compatible = "ti,gate-clock";
    						clocks = <0x5d>;
    						#clock-cells = <0x0>;
    						reg = <0x13b8>;
    						ti,bit-shift = <0xa>;
    						phandle = <0xc2>;
    					};
    
    					apll_pcie_clkvcoldo {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x5c>;
    						clock-mult = <0x1>;
    						clock-div = <0x1>;
    						phandle = <0x11e>;
    					};
    
    					apll_pcie_clkvcoldo_div {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x5c>;
    						clock-mult = <0x1>;
    						clock-div = <0x1>;
    						phandle = <0x11f>;
    					};
    
    					apll_pcie_m2_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x5c>;
    						clock-mult = <0x1>;
    						clock-div = <0x1>;
    						phandle = <0x8e>;
    					};
    
    					dpll_per_byp_mux@14c {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x10 0x5e>;
    						ti,bit-shift = <0x17>;
    						reg = <0x14c>;
    						phandle = <0x5f>;
    					};
    
    					dpll_per_ck@140 {
    						#clock-cells = <0x0>;
    						compatible = "ti,omap4-dpll-clock";
    						clocks = <0x10 0x5f>;
    						reg = <0x140 0x144 0x14c 0x148>;
    						phandle = <0x60>;
    					};
    
    					dpll_per_m2_ck@150 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x60>;
    						ti,max-div = <0x1f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x150>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0x61>;
    					};
    
    					func_96m_aon_dclk_div {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x61>;
    						clock-mult = <0x1>;
    						clock-div = <0x1>;
    						phandle = <0x9c>;
    					};
    
    					dpll_usb_byp_mux@18c {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x10 0x62>;
    						ti,bit-shift = <0x17>;
    						reg = <0x18c>;
    						phandle = <0x63>;
    					};
    
    					dpll_usb_ck@180 {
    						#clock-cells = <0x0>;
    						compatible = "ti,omap4-dpll-j-type-clock";
    						clocks = <0x10 0x63>;
    						reg = <0x180 0x184 0x18c 0x188>;
    						phandle = <0x64>;
    					};
    
    					dpll_usb_m2_ck@190 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x64>;
    						ti,max-div = <0x7f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x190>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0x67>;
    					};
    
    					dpll_pcie_ref_m2_ck@210 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x58>;
    						ti,max-div = <0x7f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x210>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0x8d>;
    					};
    
    					dpll_per_x2_ck {
    						#clock-cells = <0x0>;
    						compatible = "ti,omap4-dpll-x2-clock";
    						clocks = <0x60>;
    						phandle = <0x65>;
    					};
    
    					dpll_per_h11x2_ck@158 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x65>;
    						ti,max-div = <0x3f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x158>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0x66>;
    					};
    
    					dpll_per_h12x2_ck@15c {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x65>;
    						ti,max-div = <0x3f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x15c>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0x6a>;
    					};
    
    					dpll_per_h13x2_ck@160 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x65>;
    						ti,max-div = <0x3f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x160>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0x7c>;
    					};
    
    					dpll_per_h14x2_ck@164 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x65>;
    						ti,max-div = <0x3f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x164>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0x73>;
    					};
    
    					dpll_per_m2x2_ck@150 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x65>;
    						ti,max-div = <0x1f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x150>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0x57>;
    					};
    
    					dpll_usb_clkdcoldo {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x64>;
    						clock-mult = <0x1>;
    						clock-div = <0x1>;
    						phandle = <0x69>;
    					};
    
    					func_128m_clk {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x66>;
    						clock-mult = <0x1>;
    						clock-div = <0x2>;
    						phandle = <0x77>;
    					};
    
    					func_12m_fclk {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x57>;
    						clock-mult = <0x1>;
    						clock-div = <0x10>;
    						phandle = <0x120>;
    					};
    
    					func_24m_clk {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x61>;
    						clock-mult = <0x1>;
    						clock-div = <0x4>;
    						phandle = <0x3f>;
    					};
    
    					func_48m_fclk {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x57>;
    						clock-mult = <0x1>;
    						clock-div = <0x4>;
    						phandle = <0x56>;
    					};
    
    					func_96m_fclk {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x57>;
    						clock-mult = <0x1>;
    						clock-div = <0x2>;
    						phandle = <0x121>;
    					};
    
    					l3init_60m_fclk@104 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x67>;
    						reg = <0x104>;
    						ti,dividers = <0x1 0x8>;
    						phandle = <0x122>;
    					};
    
    					clkout2_clk@6b0 {
    						#clock-cells = <0x0>;
    						compatible = "ti,gate-clock";
    						clocks = <0x68>;
    						ti,bit-shift = <0x8>;
    						reg = <0x6b0>;
    						phandle = <0x123>;
    					};
    
    					l3init_960m_gfclk@6c0 {
    						#clock-cells = <0x0>;
    						compatible = "ti,gate-clock";
    						clocks = <0x69>;
    						ti,bit-shift = <0x8>;
    						reg = <0x6c0>;
    						phandle = <0x6e>;
    					};
    
    					dss_32khz_clk@1120 {
    						#clock-cells = <0x0>;
    						compatible = "ti,gate-clock";
    						clocks = <0x50>;
    						ti,bit-shift = <0xb>;
    						reg = <0x1120>;
    						phandle = <0x124>;
    					};
    
    					dss_48mhz_clk@1120 {
    						#clock-cells = <0x0>;
    						compatible = "ti,gate-clock";
    						clocks = <0x56>;
    						ti,bit-shift = <0x9>;
    						reg = <0x1120>;
    						phandle = <0xe6>;
    					};
    
    					dss_dss_clk@1120 {
    						#clock-cells = <0x0>;
    						compatible = "ti,gate-clock";
    						clocks = <0x6a>;
    						ti,bit-shift = <0x8>;
    						reg = <0x1120>;
    						ti,set-rate-parent;
    						phandle = <0xe3>;
    					};
    
    					dss_hdmi_clk@1120 {
    						#clock-cells = <0x0>;
    						compatible = "ti,gate-clock";
    						clocks = <0x6b>;
    						ti,bit-shift = <0xa>;
    						reg = <0x1120>;
    						phandle = <0xe7>;
    					};
    
    					dss_video1_clk@1120 {
    						#clock-cells = <0x0>;
    						compatible = "ti,gate-clock";
    						clocks = <0x6c>;
    						ti,bit-shift = <0xc>;
    						reg = <0x1120>;
    						phandle = <0xe4>;
    					};
    
    					dss_video2_clk@1120 {
    						#clock-cells = <0x0>;
    						compatible = "ti,gate-clock";
    						clocks = <0x6d>;
    						ti,bit-shift = <0xd>;
    						reg = <0x1120>;
    						phandle = <0xe5>;
    					};
    
    					gpio2_dbclk@1760 {
    						#clock-cells = <0x0>;
    						compatible = "ti,gate-clock";
    						clocks = <0x50>;
    						ti,bit-shift = <0x8>;
    						reg = <0x1760>;
    						phandle = <0x125>;
    					};
    
    					gpio3_dbclk@1768 {
    						#clock-cells = <0x0>;
    						compatible = "ti,gate-clock";
    						clocks = <0x50>;
    						ti,bit-shift = <0x8>;
    						reg = <0x1768>;
    						phandle = <0x126>;
    					};
    
    					gpio4_dbclk@1770 {
    						#clock-cells = <0x0>;
    						compatible = "ti,gate-clock";
    						clocks = <0x50>;
    						ti,bit-shift = <0x8>;
    						reg = <0x1770>;
    						phandle = <0x127>;
    					};
    
    					gpio5_dbclk@1778 {
    						#clock-cells = <0x0>;
    						compatible = "ti,gate-clock";
    						clocks = <0x50>;
    						ti,bit-shift = <0x8>;
    						reg = <0x1778>;
    						phandle = <0x128>;
    					};
    
    					gpio6_dbclk@1780 {
    						#clock-cells = <0x0>;
    						compatible = "ti,gate-clock";
    						clocks = <0x50>;
    						ti,bit-shift = <0x8>;
    						reg = <0x1780>;
    						phandle = <0x129>;
    					};
    
    					gpio7_dbclk@1810 {
    						#clock-cells = <0x0>;
    						compatible = "ti,gate-clock";
    						clocks = <0x50>;
    						ti,bit-shift = <0x8>;
    						reg = <0x1810>;
    						phandle = <0x12a>;
    					};
    
    					gpio8_dbclk@1818 {
    						#clock-cells = <0x0>;
    						compatible = "ti,gate-clock";
    						clocks = <0x50>;
    						ti,bit-shift = <0x8>;
    						reg = <0x1818>;
    						phandle = <0x12b>;
    					};
    
    					mmc1_clk32k@1328 {
    						#clock-cells = <0x0>;
    						compatible = "ti,gate-clock";
    						clocks = <0x50>;
    						ti,bit-shift = <0x8>;
    						reg = <0x1328>;
    						phandle = <0x12c>;
    					};
    
    					mmc2_clk32k@1330 {
    						#clock-cells = <0x0>;
    						compatible = "ti,gate-clock";
    						clocks = <0x50>;
    						ti,bit-shift = <0x8>;
    						reg = <0x1330>;
    						phandle = <0x12d>;
    					};
    
    					mmc3_clk32k@1820 {
    						#clock-cells = <0x0>;
    						compatible = "ti,gate-clock";
    						clocks = <0x50>;
    						ti,bit-shift = <0x8>;
    						reg = <0x1820>;
    						phandle = <0x12e>;
    					};
    
    					mmc4_clk32k@1828 {
    						#clock-cells = <0x0>;
    						compatible = "ti,gate-clock";
    						clocks = <0x50>;
    						ti,bit-shift = <0x8>;
    						reg = <0x1828>;
    						phandle = <0x12f>;
    					};
    
    					sata_ref_clk@1388 {
    						#clock-cells = <0x0>;
    						compatible = "ti,gate-clock";
    						clocks = <0x10>;
    						ti,bit-shift = <0x8>;
    						reg = <0x1388>;
    						phandle = <0xbb>;
    					};
    
    					usb_otg_ss1_refclk960m@13f0 {
    						#clock-cells = <0x0>;
    						compatible = "ti,gate-clock";
    						clocks = <0x6e>;
    						ti,bit-shift = <0x8>;
    						reg = <0x13f0>;
    						phandle = <0xc5>;
    					};
    
    					usb_otg_ss2_refclk960m@1340 {
    						#clock-cells = <0x0>;
    						compatible = "ti,gate-clock";
    						clocks = <0x6e>;
    						ti,bit-shift = <0x8>;
    						reg = <0x1340>;
    						phandle = <0xc8>;
    					};
    
    					usb_phy1_always_on_clk32k@640 {
    						#clock-cells = <0x0>;
    						compatible = "ti,gate-clock";
    						clocks = <0x50>;
    						ti,bit-shift = <0x8>;
    						reg = <0x640>;
    						phandle = <0xc4>;
    					};
    
    					usb_phy2_always_on_clk32k@688 {
    						#clock-cells = <0x0>;
    						compatible = "ti,gate-clock";
    						clocks = <0x50>;
    						ti,bit-shift = <0x8>;
    						reg = <0x688>;
    						phandle = <0xc7>;
    					};
    
    					usb_phy3_always_on_clk32k@698 {
    						#clock-cells = <0x0>;
    						compatible = "ti,gate-clock";
    						clocks = <0x50>;
    						ti,bit-shift = <0x8>;
    						reg = <0x698>;
    						phandle = <0xc9>;
    					};
    
    					atl_dpll_clk_mux@c00 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x50 0x39 0x3a 0x2f>;
    						ti,bit-shift = <0x18>;
    						reg = <0xc00>;
    						phandle = <0x70>;
    					};
    
    					atl_gfclk_mux@c00 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x9 0x6f 0x70>;
    						ti,bit-shift = <0x1a>;
    						reg = <0xc00>;
    						phandle = <0xf>;
    					};
    
    					rmii_50mhz_clk_mux@13d0 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x38 0x71>;
    						ti,bit-shift = <0x18>;
    						reg = <0x13d0>;
    						phandle = <0x130>;
    					};
    
    					gmac_rft_clk_mux@13d0 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x39 0x3a 0x6f 0x2f 0x9>;
    						ti,bit-shift = <0x19>;
    						reg = <0x13d0>;
    						phandle = <0xe1>;
    					};
    
    					gpu_core_gclk_mux@1220 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x72 0x73 0x27>;
    						ti,bit-shift = <0x18>;
    						reg = <0x1220>;
    						assigned-clocks = <0x74>;
    						assigned-clock-parents = <0x27>;
    						phandle = <0x74>;
    					};
    
    					gpu_hyd_gclk_mux@1220 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x72 0x73 0x27>;
    						ti,bit-shift = <0x1a>;
    						reg = <0x1220>;
    						assigned-clocks = <0x75>;
    						assigned-clock-parents = <0x27>;
    						phandle = <0x75>;
    					};
    
    					l3instr_ts_gclk_div@e50 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x76>;
    						ti,bit-shift = <0x18>;
    						reg = <0xe50>;
    						ti,dividers = <0x8 0x10 0x20>;
    						phandle = <0x131>;
    					};
    
    					mcasp2_ahclkr_mux@1860 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x3d 0x3e 0x3f 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4a>;
    						ti,bit-shift = <0x1c>;
    						reg = <0x1860>;
    						phandle = <0xd3>;
    					};
    
    					mcasp2_ahclkx_mux@1860 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x3d 0x3e 0x3f 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4a>;
    						ti,bit-shift = <0x18>;
    						reg = <0x1860>;
    						phandle = <0xd2>;
    					};
    
    					mcasp2_aux_gfclk_mux@1860 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x4b 0x4c 0x4d 0x4e>;
    						ti,bit-shift = <0x16>;
    						reg = <0x1860>;
    						phandle = <0xd1>;
    					};
    
    					mcasp3_ahclkx_mux@1868 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x3d 0x3e 0x3f 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4a>;
    						ti,bit-shift = <0x18>;
    						reg = <0x1868>;
    						phandle = <0xd5>;
    					};
    
    					mcasp3_aux_gfclk_mux@1868 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x4b 0x4c 0x4d 0x4e>;
    						ti,bit-shift = <0x16>;
    						reg = <0x1868>;
    						phandle = <0xd4>;
    					};
    
    					mcasp4_ahclkx_mux@1898 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x3d 0x3e 0x3f 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4a>;
    						ti,bit-shift = <0x18>;
    						reg = <0x1898>;
    						phandle = <0xd7>;
    					};
    
    					mcasp4_aux_gfclk_mux@1898 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x4b 0x4c 0x4d 0x4e>;
    						ti,bit-shift = <0x16>;
    						reg = <0x1898>;
    						phandle = <0xd6>;
    					};
    
    					mcasp5_ahclkx_mux@1878 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x3d 0x3e 0x3f 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4a>;
    						ti,bit-shift = <0x18>;
    						reg = <0x1878>;
    						phandle = <0xd9>;
    					};
    
    					mcasp5_aux_gfclk_mux@1878 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x4b 0x4c 0x4d 0x4e>;
    						ti,bit-shift = <0x16>;
    						reg = <0x1878>;
    						phandle = <0xd8>;
    					};
    
    					mcasp6_ahclkx_mux@1904 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x3d 0x3e 0x3f 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4a>;
    						ti,bit-shift = <0x18>;
    						reg = <0x1904>;
    						phandle = <0xdb>;
    					};
    
    					mcasp6_aux_gfclk_mux@1904 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x4b 0x4c 0x4d 0x4e>;
    						ti,bit-shift = <0x16>;
    						reg = <0x1904>;
    						phandle = <0xda>;
    					};
    
    					mcasp7_ahclkx_mux@1908 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x3d 0x3e 0x3f 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4a>;
    						ti,bit-shift = <0x18>;
    						reg = <0x1908>;
    						phandle = <0xdd>;
    					};
    
    					mcasp7_aux_gfclk_mux@1908 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x4b 0x4c 0x4d 0x4e>;
    						ti,bit-shift = <0x16>;
    						reg = <0x1908>;
    						phandle = <0xdc>;
    					};
    
    					mcasp8_ahclkx_mux@1890 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x3d 0x3e 0x3f 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4a>;
    						ti,bit-shift = <0x16>;
    						reg = <0x1890>;
    						phandle = <0xdf>;
    					};
    
    					mcasp8_aux_gfclk_mux@1890 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x4b 0x4c 0x4d 0x4e>;
    						ti,bit-shift = <0x18>;
    						reg = <0x1890>;
    						phandle = <0xde>;
    					};
    
    					mmc1_fclk_mux@1328 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x77 0x57>;
    						ti,bit-shift = <0x18>;
    						reg = <0x1328>;
    						phandle = <0x78>;
    					};
    
    					mmc1_fclk_div@1328 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x78>;
    						ti,bit-shift = <0x19>;
    						ti,max-div = <0x4>;
    						reg = <0x1328>;
    						ti,index-power-of-two;
    						phandle = <0x132>;
    					};
    
    					mmc2_fclk_mux@1330 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x77 0x57>;
    						ti,bit-shift = <0x18>;
    						reg = <0x1330>;
    						phandle = <0x79>;
    					};
    
    					mmc2_fclk_div@1330 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x79>;
    						ti,bit-shift = <0x19>;
    						ti,max-div = <0x4>;
    						reg = <0x1330>;
    						ti,index-power-of-two;
    						phandle = <0x133>;
    					};
    
    					mmc3_gfclk_mux@1820 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x56 0x57>;
    						ti,bit-shift = <0x18>;
    						reg = <0x1820>;
    						phandle = <0x7a>;
    					};
    
    					mmc3_gfclk_div@1820 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x7a>;
    						ti,bit-shift = <0x19>;
    						ti,max-div = <0x4>;
    						reg = <0x1820>;
    						ti,index-power-of-two;
    						phandle = <0x134>;
    					};
    
    					mmc4_gfclk_mux@1828 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x56 0x57>;
    						ti,bit-shift = <0x18>;
    						reg = <0x1828>;
    						phandle = <0x7b>;
    					};
    
    					mmc4_gfclk_div@1828 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x7b>;
    						ti,bit-shift = <0x19>;
    						ti,max-div = <0x4>;
    						reg = <0x1828>;
    						ti,index-power-of-two;
    						phandle = <0x135>;
    					};
    
    					qspi_gfclk_mux@1838 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x77 0x7c>;
    						ti,bit-shift = <0x18>;
    						reg = <0x1838>;
    						phandle = <0x7d>;
    					};
    
    					qspi_gfclk_div@1838 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x7d>;
    						ti,bit-shift = <0x19>;
    						ti,max-div = <0x4>;
    						reg = <0x1838>;
    						ti,index-power-of-two;
    						phandle = <0xba>;
    					};
    
    					timer10_gfclk_mux@1728 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x4f 0x50 0x44 0x45 0x46 0x47 0x48 0x51 0x52 0x53 0x54>;
    						ti,bit-shift = <0x18>;
    						reg = <0x1728>;
    						phandle = <0x136>;
    					};
    
    					timer11_gfclk_mux@1730 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x4f 0x50 0x44 0x45 0x46 0x47 0x48 0x51 0x52 0x53 0x54>;
    						ti,bit-shift = <0x18>;
    						reg = <0x1730>;
    						phandle = <0x137>;
    					};
    
    					timer13_gfclk_mux@17c8 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x4f 0x50 0x44 0x45 0x46 0x47 0x48 0x51 0x52 0x53 0x54>;
    						ti,bit-shift = <0x18>;
    						reg = <0x17c8>;
    						phandle = <0x138>;
    					};
    
    					timer14_gfclk_mux@17d0 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x4f 0x50 0x44 0x45 0x46 0x47 0x48 0x51 0x52 0x53 0x54>;
    						ti,bit-shift = <0x18>;
    						reg = <0x17d0>;
    						phandle = <0x139>;
    					};
    
    					timer15_gfclk_mux@17d8 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x4f 0x50 0x44 0x45 0x46 0x47 0x48 0x51 0x52 0x53 0x54>;
    						ti,bit-shift = <0x18>;
    						reg = <0x17d8>;
    						phandle = <0x13a>;
    					};
    
    					timer16_gfclk_mux@1830 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x4f 0x50 0x44 0x45 0x46 0x47 0x48 0x51 0x52 0x53 0x54>;
    						ti,bit-shift = <0x18>;
    						reg = <0x1830>;
    						phandle = <0x13b>;
    					};
    
    					timer2_gfclk_mux@1738 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x4f 0x50 0x44 0x45 0x46 0x47 0x48 0x51 0x52 0x53 0x54>;
    						ti,bit-shift = <0x18>;
    						reg = <0x1738>;
    						phandle = <0x13c>;
    					};
    
    					timer3_gfclk_mux@1740 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x4f 0x50 0x44 0x45 0x46 0x47 0x48 0x51 0x52 0x53 0x54>;
    						ti,bit-shift = <0x18>;
    						reg = <0x1740>;
    						phandle = <0x13d>;
    					};
    
    					timer4_gfclk_mux@1748 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x4f 0x50 0x44 0x45 0x46 0x47 0x48 0x51 0x52 0x53 0x54>;
    						ti,bit-shift = <0x18>;
    						reg = <0x1748>;
    						phandle = <0x13e>;
    					};
    
    					timer9_gfclk_mux@1750 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x4f 0x50 0x44 0x45 0x46 0x47 0x48 0x51 0x52 0x53 0x54>;
    						ti,bit-shift = <0x18>;
    						reg = <0x1750>;
    						phandle = <0x13f>;
    					};
    
    					uart1_gfclk_mux@1840 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x56 0x57>;
    						ti,bit-shift = <0x18>;
    						reg = <0x1840>;
    						phandle = <0x140>;
    					};
    
    					uart2_gfclk_mux@1848 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x56 0x57>;
    						ti,bit-shift = <0x18>;
    						reg = <0x1848>;
    						phandle = <0x141>;
    					};
    
    					uart3_gfclk_mux@1850 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x56 0x57>;
    						ti,bit-shift = <0x18>;
    						reg = <0x1850>;
    						phandle = <0x142>;
    					};
    
    					uart4_gfclk_mux@1858 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x56 0x57>;
    						ti,bit-shift = <0x18>;
    						reg = <0x1858>;
    						phandle = <0x143>;
    					};
    
    					uart5_gfclk_mux@1870 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x56 0x57>;
    						ti,bit-shift = <0x18>;
    						reg = <0x1870>;
    						phandle = <0x144>;
    					};
    
    					uart7_gfclk_mux@18d0 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x56 0x57>;
    						ti,bit-shift = <0x18>;
    						reg = <0x18d0>;
    						phandle = <0x145>;
    					};
    
    					uart8_gfclk_mux@18e0 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x56 0x57>;
    						ti,bit-shift = <0x18>;
    						reg = <0x18e0>;
    						phandle = <0x146>;
    					};
    
    					uart9_gfclk_mux@18e8 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x56 0x57>;
    						ti,bit-shift = <0x18>;
    						reg = <0x18e8>;
    						phandle = <0x147>;
    					};
    
    					vip1_gclk_mux@1020 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x9 0x7e>;
    						ti,bit-shift = <0x18>;
    						reg = <0x1020>;
    						phandle = <0x148>;
    					};
    
    					vip2_gclk_mux@1028 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x9 0x7e>;
    						ti,bit-shift = <0x18>;
    						reg = <0x1028>;
    						phandle = <0x149>;
    					};
    
    					vip3_gclk_mux@1030 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x9 0x7e>;
    						ti,bit-shift = <0x18>;
    						reg = <0x1030>;
    						phandle = <0x14a>;
    					};
    				};
    
    				clockdomains {
    					phandle = <0x14b>;
    
    					coreaon_clkdm {
    						compatible = "ti,clockdomain";
    						clocks = <0x64>;
    						phandle = <0x14c>;
    					};
    				};
    			};
    		};
    
    		l4@4ae00000 {
    			compatible = "ti,dra7-l4-wkup", "simple-bus";
    			#address-cells = <0x1>;
    			#size-cells = <0x1>;
    			ranges = <0x0 0x4ae00000 0x3f000>;
    			phandle = <0x14d>;
    
    			counter@4000 {
    				compatible = "ti,omap-counter32k";
    				reg = <0x4000 0x40>;
    				ti,hwmods = "counter_32k";
    				phandle = <0x14e>;
    			};
    
    			prm@6000 {
    				compatible = "ti,dra7-prm";
    				reg = <0x6000 0x3000>;
    				interrupts = <0x0 0x6 0x4>;
    				phandle = <0x14f>;
    
    				clocks {
    					#address-cells = <0x1>;
    					#size-cells = <0x0>;
    					phandle = <0x150>;
    
    					sys_clkin1@110 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x7f 0x80 0x81 0x82 0x83 0x84 0x85>;
    						reg = <0x110>;
    						ti,index-starts-at-one;
    						phandle = <0x10>;
    					};
    
    					abe_dpll_sys_clk_mux@118 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x10 0x44>;
    						reg = <0x118>;
    						phandle = <0x86>;
    					};
    
    					abe_dpll_bypass_clk_mux@114 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x86 0x50>;
    						reg = <0x114>;
    						phandle = <0x12>;
    					};
    
    					abe_dpll_clk_mux@10c {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x86 0x50>;
    						reg = <0x10c>;
    						phandle = <0x11>;
    					};
    
    					abe_24m_fclk@11c {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x15>;
    						reg = <0x11c>;
    						ti,dividers = <0x8 0x10>;
    						phandle = <0x3d>;
    					};
    
    					aess_fclk@178 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x87>;
    						reg = <0x178>;
    						ti,max-div = <0x2>;
    						phandle = <0x88>;
    					};
    
    					abe_giclk_div@174 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x88>;
    						reg = <0x174>;
    						ti,max-div = <0x2>;
    						phandle = <0x51>;
    					};
    
    					abe_lp_clk_div@1d8 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x15>;
    						reg = <0x1d8>;
    						ti,dividers = <0x10 0x20>;
    						phandle = <0xa7>;
    					};
    
    					abe_sys_clk_div@120 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x10>;
    						reg = <0x120>;
    						ti,max-div = <0x2>;
    						phandle = <0x3e>;
    					};
    
    					adc_gfclk_mux@1dc {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x10 0x44 0x50>;
    						reg = <0x1dc>;
    						phandle = <0x151>;
    					};
    
    					sys_clk1_dclk_div@1c8 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x10>;
    						ti,max-div = <0x40>;
    						reg = <0x1c8>;
    						ti,index-power-of-two;
    						phandle = <0x90>;
    					};
    
    					sys_clk2_dclk_div@1cc {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x44>;
    						ti,max-div = <0x40>;
    						reg = <0x1cc>;
    						ti,index-power-of-two;
    						phandle = <0x91>;
    					};
    
    					per_abe_x1_dclk_div@1bc {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x6f>;
    						ti,max-div = <0x40>;
    						reg = <0x1bc>;
    						ti,index-power-of-two;
    						phandle = <0x92>;
    					};
    
    					dsp_gclk_div@18c {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x20>;
    						ti,max-div = <0x40>;
    						reg = <0x18c>;
    						ti,index-power-of-two;
    						phandle = <0x94>;
    					};
    
    					gpu_dclk@1a0 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x27>;
    						ti,max-div = <0x40>;
    						reg = <0x1a0>;
    						ti,index-power-of-two;
    						phandle = <0x96>;
    					};
    
    					emif_phy_dclk_div@190 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x89>;
    						ti,max-div = <0x40>;
    						reg = <0x190>;
    						ti,index-power-of-two;
    						phandle = <0x98>;
    					};
    
    					gmac_250m_dclk_div@19c {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x8a>;
    						ti,max-div = <0x40>;
    						reg = <0x19c>;
    						ti,index-power-of-two;
    						phandle = <0x8b>;
    					};
    
    					gmac_main_clk {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x8b>;
    						clock-mult = <0x1>;
    						clock-div = <0x2>;
    						phandle = <0xe0>;
    					};
    
    					l3init_480m_dclk_div@1ac {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x67>;
    						ti,max-div = <0x40>;
    						reg = <0x1ac>;
    						ti,index-power-of-two;
    						phandle = <0x9d>;
    					};
    
    					usb_otg_dclk_div@184 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x8c>;
    						ti,max-div = <0x40>;
    						reg = <0x184>;
    						ti,index-power-of-two;
    						phandle = <0x9e>;
    					};
    
    					sata_dclk_div@1c0 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x10>;
    						ti,max-div = <0x40>;
    						reg = <0x1c0>;
    						ti,index-power-of-two;
    						phandle = <0x9f>;
    					};
    
    					pcie2_dclk_div@1b8 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x8d>;
    						ti,max-div = <0x40>;
    						reg = <0x1b8>;
    						ti,index-power-of-two;
    						phandle = <0xa0>;
    					};
    
    					pcie_dclk_div@1b4 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x8e>;
    						ti,max-div = <0x40>;
    						reg = <0x1b4>;
    						ti,index-power-of-two;
    						phandle = <0xa1>;
    					};
    
    					emu_dclk_div@194 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x10>;
    						ti,max-div = <0x40>;
    						reg = <0x194>;
    						ti,index-power-of-two;
    						phandle = <0xa2>;
    					};
    
    					secure_32k_dclk_div@1c4 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x8f>;
    						ti,max-div = <0x40>;
    						reg = <0x1c4>;
    						ti,index-power-of-two;
    						phandle = <0xa3>;
    					};
    
    					clkoutmux0_clk_mux@158 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x8b 0x99 0x9a 0x9b 0x9c 0x9d 0x9e 0x9f 0xa0 0xa1 0xa2 0xa3 0xa4>;
    						reg = <0x158>;
    						phandle = <0x55>;
    					};
    
    					clkoutmux1_clk_mux@15c {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x8b 0x99 0x9a 0x9b 0x9c 0x9d 0x9e 0x9f 0xa0 0xa1 0xa2 0xa3 0xa4>;
    						reg = <0x15c>;
    						phandle = <0x152>;
    					};
    
    					clkoutmux2_clk_mux@160 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x8b 0x99 0x9a 0x9b 0x9c 0x9d 0x9e 0x9f 0xa0 0xa1 0xa2 0xa3 0xa4>;
    						reg = <0x160>;
    						phandle = <0x68>;
    					};
    
    					custefuse_sys_gfclk_div {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x10>;
    						clock-mult = <0x1>;
    						clock-div = <0x2>;
    						phandle = <0x153>;
    					};
    
    					eve_clk@180 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x33 0x36>;
    						reg = <0x180>;
    						phandle = <0x154>;
    					};
    
    					hdmi_dpll_clk_mux@164 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x10 0x44>;
    						reg = <0x164>;
    						phandle = <0x6b>;
    					};
    
    					mlb_clk@134 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0xa5>;
    						ti,max-div = <0x40>;
    						reg = <0x134>;
    						ti,index-power-of-two;
    						phandle = <0x49>;
    					};
    
    					mlbp_clk@130 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0xa6>;
    						ti,max-div = <0x40>;
    						reg = <0x130>;
    						ti,index-power-of-two;
    						phandle = <0x4a>;
    					};
    
    					per_abe_x1_gfclk2_div@138 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x6f>;
    						ti,max-div = <0x40>;
    						reg = <0x138>;
    						ti,index-power-of-two;
    						phandle = <0x4b>;
    					};
    
    					timer_sys_clk_div@144 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x10>;
    						reg = <0x144>;
    						ti,max-div = <0x2>;
    						phandle = <0x4f>;
    					};
    
    					video1_dpll_clk_mux@168 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x10 0x44>;
    						reg = <0x168>;
    						phandle = <0x6c>;
    					};
    
    					video2_dpll_clk_mux@16c {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x10 0x44>;
    						reg = <0x16c>;
    						phandle = <0x6d>;
    					};
    
    					wkupaon_iclk_mux@108 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x10 0xa7>;
    						reg = <0x108>;
    						phandle = <0x76>;
    					};
    
    					gpio1_dbclk@1838 {
    						#clock-cells = <0x0>;
    						compatible = "ti,gate-clock";
    						clocks = <0x50>;
    						ti,bit-shift = <0x8>;
    						reg = <0x1838>;
    						phandle = <0x155>;
    					};
    
    					dcan1_sys_clk_mux@1888 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x10 0x44>;
    						ti,bit-shift = <0x18>;
    						reg = <0x1888>;
    						phandle = <0xe2>;
    					};
    
    					timer1_gfclk_mux@1840 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x4f 0x50 0x44 0x45 0x46 0x47 0x48 0x51 0x52 0x53 0x54>;
    						ti,bit-shift = <0x18>;
    						reg = <0x1840>;
    						phandle = <0x156>;
    					};
    
    					uart10_gfclk_mux@1880 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x56 0x57>;
    						ti,bit-shift = <0x18>;
    						reg = <0x1880>;
    						phandle = <0x157>;
    					};
    				};
    
    				clockdomains {
    					phandle = <0x158>;
    				};
    			};
    
    			scm_conf@c000 {
    				compatible = "syscon";
    				reg = <0xc000 0x1000>;
    				phandle = <0x6>;
    			};
    		};
    
    		axi@0 {
    			compatible = "simple-bus";
    			#size-cells = <0x1>;
    			#address-cells = <0x1>;
    			ranges = <0x51000000 0x51000000 0x3000 0x0 0x20000000 0x10000000>;
    
    			pcie@51000000 {
    				compatible = "ti,dra7-pcie";
    				reg = <0x51000000 0x2000 0x51002000 0x14c 0x1000 0x2000>;
    				reg-names = "rc_dbics", "ti_conf", "config";
    				interrupts = <0x0 0xe8 0x4 0x0 0xe9 0x4>;
    				#address-cells = <0x3>;
    				#size-cells = <0x2>;
    				device_type = "pci";
    				ranges = <0x81000000 0x0 0x0 0x3000 0x0 0x10000 0x82000000 0x0 0x20013000 0x13000 0x0 0xffed000>;
    				bus-range = <0x0 0xff>;
    				#interrupt-cells = <0x1>;
    				num-lanes = <0x1>;
    				linux,pci-domain = <0x0>;
    				ti,hwmods = "pcie1";
    				phys = <0xa8>;
    				phy-names = "pcie-phy0";
    				interrupt-map-mask = <0x0 0x0 0x0 0x7>;
    				interrupt-map = <0x0 0x0 0x0 0x1 0xa9 0x1 0x0 0x0 0x0 0x2 0xa9 0x2 0x0 0x0 0x0 0x3 0xa9 0x3 0x0 0x0 0x0 0x4 0xa9 0x4>;
    				status = "disabled";
    				phandle = <0x159>;
    
    				interrupt-controller {
    					interrupt-controller;
    					#address-cells = <0x0>;
    					#interrupt-cells = <0x1>;
    					phandle = <0xa9>;
    				};
    			};
    
    			pcie_ep@51000000 {
    				compatible = "ti,dra7-pcie-ep";
    				reg = <0x51000000 0x28 0x51002000 0x14c 0x51001000 0x28 0x1000 0x10000000>;
    				reg-names = "ep_dbics", "ti_conf", "ep_dbics2", "addr_space";
    				interrupts = <0x0 0xe8 0x4>;
    				num-lanes = <0x1>;
    				num-ib-windows = <0x4>;
    				num-ob-windows = <0x10>;
    				ti,hwmods = "pcie1";
    				phys = <0xa8>;
    				phy-names = "pcie-phy0";
    				ti,syscon-unaligned-access = <0xaa 0x14 0x2>;
    				status = "disabled";
    				phandle = <0x15a>;
    			};
    		};
    
    		axi@1 {
    			compatible = "simple-bus";
    			#size-cells = <0x1>;
    			#address-cells = <0x1>;
    			ranges = <0x51800000 0x51800000 0x3000 0x0 0x30000000 0x10000000>;
    			status = "disabled";
    
    			pcie@51800000 {
    				compatible = "ti,dra7-pcie";
    				reg = <0x51800000 0x2000 0x51802000 0x14c 0x1000 0x2000>;
    				reg-names = "rc_dbics", "ti_conf", "config";
    				interrupts = <0x0 0x163 0x4 0x0 0x164 0x4>;
    				#address-cells = <0x3>;
    				#size-cells = <0x2>;
    				device_type = "pci";
    				ranges = <0x81000000 0x0 0x0 0x3000 0x0 0x10000 0x82000000 0x0 0x30013000 0x13000 0x0 0xffed000>;
    				bus-range = <0x0 0xff>;
    				#interrupt-cells = <0x1>;
    				num-lanes = <0x1>;
    				linux,pci-domain = <0x1>;
    				ti,hwmods = "pcie2";
    				phys = <0xab>;
    				phy-names = "pcie-phy0";
    				interrupt-map-mask = <0x0 0x0 0x0 0x7>;
    				interrupt-map = <0x0 0x0 0x0 0x1 0xac 0x1 0x0 0x0 0x0 0x2 0xac 0x2 0x0 0x0 0x0 0x3 0xac 0x3 0x0 0x0 0x0 0x4 0xac 0x4>;
    
    				interrupt-controller {
    					interrupt-controller;
    					#address-cells = <0x0>;
    					#interrupt-cells = <0x1>;
    					phandle = <0xac>;
    				};
    			};
    		};
    
    		ocmcram@40300000 {
    			compatible = "mmio-sram";
    			reg = <0x40300000 0x80000>;
    			ranges = <0x0 0x40300000 0x80000>;
    			#address-cells = <0x1>;
    			#size-cells = <0x1>;
    			phandle = <0x15b>;
    
    			sram-hs@0 {
    				compatible = "ti,secure-ram";
    				reg = <0x0 0x0>;
    			};
    		};
    
    		ocmcram@40400000 {
    			status = "disabled";
    			compatible = "mmio-sram";
    			reg = <0x40400000 0x100000>;
    			ranges = <0x0 0x40400000 0x100000>;
    			#address-cells = <0x1>;
    			#size-cells = <0x1>;
    			phandle = <0x15c>;
    		};
    
    		ocmcram@40500000 {
    			status = "disabled";
    			compatible = "mmio-sram";
    			reg = <0x40500000 0x100000>;
    			ranges = <0x0 0x40500000 0x100000>;
    			#address-cells = <0x1>;
    			#size-cells = <0x1>;
    			phandle = <0x15d>;
    		};
    
    		bandgap@4a0021e0 {
    			reg = <0x4a0021e0 0xc 0x4a00232c 0xc 0x4a002380 0x2c 0x4a0023c0 0x3c 0x4a002564 0x8 0x4a002574 0x50>;
    			compatible = "ti,dra752-bandgap";
    			interrupts = <0x0 0x79 0x4>;
    			#thermal-sensor-cells = <0x1>;
    			u-boot,dm-spl;
    			phandle = <0xec>;
    		};
    
    		dsp_system@40d00000 {
    			compatible = "syscon";
    			reg = <0x40d00000 0x100>;
    			phandle = <0xb9>;
    		};
    
    		padconf@4844a000 {
    			compatible = "ti,dra7-iodelay";
    			reg = <0x4844a000 0xd1c>;
    			#address-cells = <0x1>;
    			#size-cells = <0x0>;
    			#pinctrl-cells = <0x2>;
    			phandle = <0x15e>;
    
    			mmc1_iodelay_ddr_rev11_conf {
    				pinctrl-pin-array = <0x618 0x23c 0x21c 0x620 0x5f5 0x0 0x624 0x0 0x258 0x628 0x0 0x0 0x62c 0x37 0x0 0x630 0x193 0x78 0x634 0x0 0x0 0x638 0x0 0x0 0x63c 0x17 0x3c 0x640 0x0 0x0 0x644 0x0 0x0 0x648 0x19 0x3c 0x64c 0x0 0x0 0x650 0x0 0x0 0x654 0x0 0x0 0x658 0x0 0x0 0x65c 0x0 0x0>;
    				phandle = <0x15f>;
    			};
    
    			mmc1_iodelay_ddr50_rev20_conf {
    				pinctrl-pin-array = <0x618 0x434 0x14a 0x620 0x4f7 0x0 0x624 0x2d2 0x0 0x628 0x0 0x0 0x62c 0x0 0x0 0x630 0x2ef 0x0 0x634 0x0 0x0 0x638 0x14 0x0 0x63c 0x100 0x0 0x640 0x0 0x0 0x644 0x0 0x0 0x648 0x107 0x0 0x64c 0x0 0x0 0x650 0x0 0x0 0x654 0x0 0x0 0x658 0x0 0x0 0x65c 0x0 0x0>;
    				phandle = <0x160>;
    			};
    
    			mmc1_iodelay_sdr104_rev11_conf {
    				pinctrl-pin-array = <0x620 0x427 0x11 0x628 0x0 0x0 0x62c 0x17 0x0 0x634 0x0 0x0 0x638 0x0 0x0 0x640 0x0 0x0 0x644 0x2 0x0 0x64c 0x0 0x0 0x650 0x0 0x0 0x658 0x0 0x0 0x65c 0x0 0x0>;
    				phandle = <0x161>;
    			};
    
    			mmc1_iodelay_sdr104_rev20_conf {
    				pinctrl-pin-array = <0x620 0x258 0x190 0x628 0x0 0x0 0x62c 0x0 0x0 0x634 0x0 0x0 0x638 0x1e 0x0 0x640 0x0 0x0 0x644 0x0 0x0 0x64c 0x0 0x0 0x650 0x0 0x0 0x658 0x0 0x0 0x65c 0x0 0x0>;
    				phandle = <0x162>;
    			};
    
    			mmc2_iodelay_hs200_rev11_conf {
    				pinctrl-pin-array = <0x190 0x26d 0x258 0x194 0x12c 0x0 0x1a8 0x2e3 0x258 0x1ac 0xf0 0x0 0x1b4 0x32c 0x258 0x1b8 0xf0 0x0 0x1c0 0x3ba 0x258 0x1c4 0x3c 0x0 0x1d0 0x53c 0x1a4 0x1d8 0x3a7 0x258 0x1dc 0x0 0x0 0x1e4 0x20d 0x258 0x1e8 0x78 0x0 0x1f0 0x2ff 0x258 0x1f4 0xe1 0x0 0x1fc 0x235 0x258 0x200 0x3c 0x0 0x364 0x3c9 0x258 0x368 0xb4 0x0>;
    				phandle = <0x163>;
    			};
    
    			mmc2_iodelay_hs200_rev20_conf {
    				pinctrl-pin-array = <0x190 0x112 0x0 0x194 0xa2 0x0 0x1a8 0x191 0x0 0x1ac 0x49 0x0 0x1b4 0x1d1 0x0 0x1b8 0x73 0x0 0x1c0 0x279 0x0 0x1c4 0x2f 0x0 0x1d0 0x3a7 0x118 0x1d8 0x26d 0x0 0x1dc 0x0 0x0 0x1e4 0xb7 0x0 0x1e8 0x0 0x0 0x1f0 0x1d3 0x0 0x1f4 0x0 0x0 0x1fc 0x106 0x0 0x200 0x2e 0x0 0x364 0x2ac 0x0 0x368 0x4c 0x0>;
    				phandle = <0x164>;
    			};
    
    			mmc2_iodelay_ddr_3_3v_rev11_conf {
    				pinctrl-pin-array = <0x18c 0x0 0x78 0x190 0x0 0x0 0x194 0xae 0x0 0x1a4 0x109 0x168 0x1a8 0x0 0x0 0x1ac 0xa8 0x0 0x1b0 0x0 0x78 0x1b4 0x0 0x0 0x1b8 0x88 0x0 0x1bc 0x0 0x78 0x1c0 0x0 0x0 0x1c4 0x0 0x0 0x1c8 0x11f 0x1a4 0x1d0 0x36f 0x0 0x1d4 0x90 0xf0 0x1d8 0x0 0x0 0x1dc 0x0 0x0 0x1e0 0x0 0x0 0x1e4 0x0 0x0 0x1e8 0x22 0x0 0x1ec 0x0 0x78 0x1f0 0x0 0x0 0x1f4 0x78 0x0 0x1f8 0x78 0xb4 0x1fc 0x0 0x0 0x200 0x0 0x0 0x360 0x0 0x0 0x364 0x0 0x0 0x368 0xb 0x0>;
    				phandle = <0x165>;
    			};
    
    			mmc2_iodelay_ddr_1_8v_rev11_conf {
    				pinctrl-pin-array = <0x18c 0x0 0x0 0x190 0x0 0x0 0x194 0xae 0x0 0x1a4 0x112 0xf0 0x1a8 0x0 0x0 0x1ac 0xa8 0x0 0x1b0 0x0 0x3c 0x1b4 0x0 0x0 0x1b8 0x88 0x0 0x1bc 0x0 0x3c 0x1c0 0x0 0x0 0x1c4 0x0 0x0 0x1c8 0x202 0x168 0x1d0 0x36f 0x0 0x1d4 0xbb 0x78 0x1d8 0x0 0x0 0x1dc 0x0 0x0 0x1e0 0x0 0x0 0x1e4 0x0 0x0 0x1e8 0x22 0x0 0x1ec 0x0 0x3c 0x1f0 0x0 0x0 0x1f4 0x78 0x0 0x1f8 0x79 0x3c 0x1fc 0x0 0x0 0x200 0x0 0x0 0x360 0x0 0x0 0x364 0x0 0x0 0x368 0xb 0x0>;
    				phandle = <0x166>;
    			};
    
    			mmc3_iodelay_manual1_conf {
    				pinctrl-pin-array = <0x678 0x196 0x0 0x680 0x293 0x0 0x684 0x0 0x0 0x688 0x0 0x0 0x68c 0x0 0x0 0x690 0x82 0x0 0x694 0x0 0x0 0x698 0x0 0x0 0x69c 0xa9 0x0 0x6a0 0x0 0x0 0x6a4 0x0 0x0 0x6a8 0x0 0x0 0x6ac 0x0 0x0 0x6b0 0x0 0x0 0x6b4 0x1c9 0x0 0x6b8 0x0 0x0 0x6bc 0x0 0x0>;
    				phandle = <0x167>;
    			};
    
    			mmc4_iodelay_ds_rev11_conf {
    				pinctrl-pin-array = <0x840 0x0 0x0 0x848 0x0 0x0 0x84c 0x60 0x0 0x850 0x0 0x0 0x854 0x0 0x0 0x870 0x246 0x0 0x874 0x0 0x0 0x878 0x0 0x0 0x87c 0x187 0x0 0x880 0x0 0x0 0x884 0x0 0x0 0x888 0x231 0x0 0x88c 0x0 0x0 0x890 0x0 0x0 0x894 0x24c 0x0 0x898 0x0 0x0 0x89c 0x0 0x0>;
    				phandle = <0x168>;
    			};
    
    			mmc4_iodelay_ds_rev20_conf {
    				pinctrl-pin-array = <0x840 0x0 0x0 0x848 0x0 0x0 0x84c 0x133 0x0 0x850 0x0 0x0 0x854 0x0 0x0 0x870 0x311 0x0 0x874 0x0 0x0 0x878 0x0 0x0 0x87c 0x265 0x0 0x880 0x0 0x0 0x884 0x0 0x0 0x888 0x2ab 0x0 0x88c 0x0 0x0 0x890 0x0 0x0 0x894 0x343 0x0 0x898 0x0 0x0 0x89c 0x0 0x0>;
    				phandle = <0x169>;
    			};
    
    			mmc4_iodelay_sdr12_hs_sdr25_rev11_conf {
    				pinctrl-pin-array = <0x840 0x0 0x0 0x848 0xa5b 0x0 0x84c 0x624 0x0 0x850 0x0 0x0 0x854 0x0 0x0 0x870 0x779 0x0 0x874 0x0 0x0 0x878 0x0 0x0 0x87c 0x6b9 0x0 0x880 0x0 0x0 0x884 0x0 0x0 0x888 0x763 0x0 0x88c 0x0 0x0 0x890 0x0 0x0 0x894 0x77f 0x0 0x898 0x0 0x0 0x89c 0x0 0x0>;
    				phandle = <0x16a>;
    			};
    
    			mmc4_iodelay_sdr12_hs_sdr25_rev20_conf {
    				pinctrl-pin-array = <0x840 0x0 0x0 0x848 0x47b 0x0 0x84c 0x72a 0x0 0x850 0x0 0x0 0x854 0x0 0x0 0x870 0x875 0x0 0x874 0x0 0x0 0x878 0x0 0x0 0x87c 0x789 0x40 0x880 0x0 0x0 0x884 0x0 0x0 0x888 0x78f 0x80 0x88c 0x0 0x0 0x890 0x0 0x0 0x894 0x87c 0x2c 0x898 0x0 0x0 0x89c 0x0 0x0>;
    				phandle = <0x16b>;
    			};
    		};
    
    		dma-controller@4a056000 {
    			compatible = "ti,omap4430-sdma";
    			reg = <0x4a056000 0x1000>;
    			interrupts = <0x0 0x7 0x4 0x0 0x8 0x4 0x0 0x9 0x4 0x0 0xa 0x4>;
    			#dma-cells = <0x1>;
    			dma-channels = <0x20>;
    			dma-requests = <0x7f>;
    			phandle = <0xd>;
    		};
    
    		edma@43300000 {
    			compatible = "ti,edma3-tpcc";
    			ti,hwmods = "tpcc";
    			reg = <0x43300000 0x100000>;
    			reg-names = "edma3_cc";
    			interrupts = <0x0 0x169 0x4 0x0 0x168 0x4 0x0 0x167 0x4>;
    			interrupt-names = "edma3_ccint", "edma3_mperr", "edma3_ccerrint";
    			dma-requests = <0x40>;
    			#dma-cells = <0x2>;
    			ti,tptcs = <0xad 0x7 0xae 0x0>;
    			phandle = <0xe>;
    		};
    
    		tptc@43400000 {
    			compatible = "ti,edma3-tptc";
    			ti,hwmods = "tptc0";
    			reg = <0x43400000 0x100000>;
    			interrupts = <0x0 0x172 0x4>;
    			interrupt-names = "edma3_tcerrint";
    			phandle = <0xad>;
    		};
    
    		tptc@43500000 {
    			compatible = "ti,edma3-tptc";
    			ti,hwmods = "tptc1";
    			reg = <0x43500000 0x100000>;
    			interrupts = <0x0 0x173 0x4>;
    			interrupt-names = "edma3_tcerrint";
    			phandle = <0xae>;
    		};
    
    		gpio@4ae10000 {
    			compatible = "ti,omap4-gpio";
    			reg = <0x4ae10000 0x200>;
    			interrupts = <0x0 0x18 0x4>;
    			ti,hwmods = "gpio1";
    			gpio-controller;
    			#gpio-cells = <0x2>;
    			interrupt-controller;
    			#interrupt-cells = <0x2>;
    			u-boot,dm-spl;
    			phandle = <0xb1>;
    		};
    
    		gpio@48055000 {
    			compatible = "ti,omap4-gpio";
    			reg = <0x48055000 0x200>;
    			interrupts = <0x0 0x19 0x4>;
    			ti,hwmods = "gpio2";
    			gpio-controller;
    			#gpio-cells = <0x2>;
    			interrupt-controller;
    			#interrupt-cells = <0x2>;
    			u-boot,dm-spl;
    			phandle = <0x16c>;
    		};
    
    		gpio@48057000 {
    			compatible = "ti,omap4-gpio";
    			reg = <0x48057000 0x200>;
    			interrupts = <0x0 0x1a 0x4>;
    			ti,hwmods = "gpio3";
    			gpio-controller;
    			#gpio-cells = <0x2>;
    			interrupt-controller;
    			#interrupt-cells = <0x2>;
    			u-boot,dm-spl;
    			phandle = <0x16d>;
    		};
    
    		gpio@48059000 {
    			compatible = "ti,omap4-gpio";
    			reg = <0x48059000 0x200>;
    			interrupts = <0x0 0x1b 0x4>;
    			ti,hwmods = "gpio4";
    			gpio-controller;
    			#gpio-cells = <0x2>;
    			interrupt-controller;
    			#interrupt-cells = <0x2>;
    			u-boot,dm-spl;
    			phandle = <0x16e>;
    		};
    
    		gpio@4805b000 {
    			compatible = "ti,omap4-gpio";
    			reg = <0x4805b000 0x200>;
    			interrupts = <0x0 0x1c 0x4>;
    			ti,hwmods = "gpio5";
    			gpio-controller;
    			#gpio-cells = <0x2>;
    			interrupt-controller;
    			#interrupt-cells = <0x2>;
    			u-boot,dm-spl;
    			phandle = <0x16f>;
    		};
    
    		gpio@4805d000 {
    			compatible = "ti,omap4-gpio";
    			reg = <0x4805d000 0x200>;
    			interrupts = <0x0 0x1d 0x4>;
    			ti,hwmods = "gpio6";
    			gpio-controller;
    			#gpio-cells = <0x2>;
    			interrupt-controller;
    			#interrupt-cells = <0x2>;
    			u-boot,dm-spl;
    			phandle = <0xb6>;
    		};
    
    		gpio@48051000 {
    			compatible = "ti,omap4-gpio";
    			reg = <0x48051000 0x200>;
    			interrupts = <0x0 0x1e 0x4>;
    			ti,hwmods = "gpio7";
    			gpio-controller;
    			#gpio-cells = <0x2>;
    			interrupt-controller;
    			#interrupt-cells = <0x2>;
    			u-boot,dm-spl;
    			phandle = <0x170>;
    		};
    
    		gpio@48053000 {
    			compatible = "ti,omap4-gpio";
    			reg = <0x48053000 0x200>;
    			interrupts = <0x0 0x74 0x4>;
    			ti,hwmods = "gpio8";
    			gpio-controller;
    			#gpio-cells = <0x2>;
    			interrupt-controller;
    			#interrupt-cells = <0x2>;
    			phandle = <0x171>;
    		};
    
    		serial@4806a000 {
    			compatible = "ti,dra742-uart", "ti,omap4-uart";
    			reg = <0x4806a000 0x100>;
    			interrupts-extended = <0x1 0x0 0x43 0x4>;
    			ti,hwmods = "uart1";
    			clock-frequency = <0x2dc6c00>;
    			status = "disabled";
    			dmas = <0xaf 0x31 0xaf 0x32>;
    			dma-names = "tx", "rx";
    			u-boot,dm-spl;
    			reg-shift = <0x2>;
    			phandle = <0x172>;
    		};
    
    		serial@4806c000 {
    			compatible = "ti,dra742-uart", "ti,omap4-uart";
    			reg = <0x4806c000 0x100>;
    			interrupts = <0x0 0x44 0x4>;
    			ti,hwmods = "uart2";
    			clock-frequency = <0x2dc6c00>;
    			status = "disabled";
    			dmas = <0xaf 0x33 0xaf 0x34>;
    			dma-names = "tx", "rx";
    			phandle = <0x173>;
    		};
    
    		serial@48020000 {
    			compatible = "ti,dra742-uart", "ti,omap4-uart";
    			reg = <0x48020000 0x100>;
    			interrupts = <0x0 0x45 0x4>;
    			ti,hwmods = "uart3";
    			clock-frequency = <0x2dc6c00>;
    			status = "okay";
    			dmas = <0xaf 0x35 0xaf 0x36>;
    			dma-names = "tx", "rx";
    			interrupts-extended = <0x1 0x0 0x45 0x4 0xb0 0x3f8>;
    			u-boot,dm-spl;
    			reg-shift = <0x2>;
    			phandle = <0x174>;
    		};
    
    		serial@4806e000 {
    			compatible = "ti,dra742-uart", "ti,omap4-uart";
    			reg = <0x4806e000 0x100>;
    			interrupts = <0x0 0x41 0x4>;
    			ti,hwmods = "uart4";
    			clock-frequency = <0x2dc6c00>;
    			status = "disabled";
    			dmas = <0xaf 0x37 0xaf 0x38>;
    			dma-names = "tx", "rx";
    			phandle = <0x175>;
    		};
    
    		serial@48066000 {
    			compatible = "ti,dra742-uart", "ti,omap4-uart";
    			reg = <0x48066000 0x100>;
    			interrupts = <0x0 0x64 0x4>;
    			ti,hwmods = "uart5";
    			clock-frequency = <0x2dc6c00>;
    			status = "disabled";
    			dmas = <0xaf 0x3f 0xaf 0x40>;
    			dma-names = "tx", "rx";
    			phandle = <0x176>;
    		};
    
    		serial@48068000 {
    			compatible = "ti,dra742-uart", "ti,omap4-uart";
    			reg = <0x48068000 0x100>;
    			interrupts = <0x0 0x65 0x4>;
    			ti,hwmods = "uart6";
    			clock-frequency = <0x2dc6c00>;
    			status = "disabled";
    			dmas = <0xaf 0x4f 0xaf 0x50>;
    			dma-names = "tx", "rx";
    			phandle = <0x177>;
    		};
    
    		serial@48420000 {
    			compatible = "ti,dra742-uart", "ti,omap4-uart";
    			reg = <0x48420000 0x100>;
    			interrupts = <0x0 0xda 0x4>;
    			ti,hwmods = "uart7";
    			clock-frequency = <0x2dc6c00>;
    			status = "disabled";
    			phandle = <0x178>;
    		};
    
    		serial@48422000 {
    			compatible = "ti,dra742-uart", "ti,omap4-uart";
    			reg = <0x48422000 0x100>;
    			interrupts = <0x0 0xdb 0x4>;
    			ti,hwmods = "uart8";
    			clock-frequency = <0x2dc6c00>;
    			status = "disabled";
    			phandle = <0x179>;
    		};
    
    		serial@48424000 {
    			compatible = "ti,dra742-uart", "ti,omap4-uart";
    			reg = <0x48424000 0x100>;
    			interrupts = <0x0 0xdc 0x4>;
    			ti,hwmods = "uart9";
    			clock-frequency = <0x2dc6c00>;
    			status = "disabled";
    			phandle = <0x17a>;
    		};
    
    		serial@4ae2b000 {
    			compatible = "ti,dra742-uart", "ti,omap4-uart";
    			reg = <0x4ae2b000 0x100>;
    			interrupts = <0x0 0xdd 0x4>;
    			ti,hwmods = "uart10";
    			clock-frequency = <0x2dc6c00>;
    			status = "disabled";
    			phandle = <0x17b>;
    		};
    
    		mailbox@4a0f4000 {
    			compatible = "ti,omap4-mailbox";
    			reg = <0x4a0f4000 0x200>;
    			interrupts = <0x0 0x15 0x4 0x0 0x87 0x4 0x0 0x86 0x4>;
    			ti,hwmods = "mailbox1";
    			#mbox-cells = <0x1>;
    			ti,mbox-num-users = <0x3>;
    			ti,mbox-num-fifos = <0x8>;
    			status = "disabled";
    			phandle = <0x17c>;
    		};
    
    		mailbox@4883a000 {
    			compatible = "ti,omap4-mailbox";
    			reg = <0x4883a000 0x200>;
    			interrupts = <0x0 0xed 0x4 0x0 0xee 0x4 0x0 0xef 0x4 0x0 0xf0 0x4>;
    			ti,hwmods = "mailbox2";
    			#mbox-cells = <0x1>;
    			ti,mbox-num-users = <0x4>;
    			ti,mbox-num-fifos = <0xc>;
    			status = "disabled";
    			phandle = <0x17d>;
    		};
    
    		mailbox@4883c000 {
    			compatible = "ti,omap4-mailbox";
    			reg = <0x4883c000 0x200>;
    			interrupts = <0x0 0xf1 0x4 0x0 0xf2 0x4 0x0 0xf3 0x4 0x0 0xf4 0x4>;
    			ti,hwmods = "mailbox3";
    			#mbox-cells = <0x1>;
    			ti,mbox-num-users = <0x4>;
    			ti,mbox-num-fifos = <0xc>;
    			status = "disabled";
    			phandle = <0x17e>;
    		};
    
    		mailbox@4883e000 {
    			compatible = "ti,omap4-mailbox";
    			reg = <0x4883e000 0x200>;
    			interrupts = <0x0 0xf5 0x4 0x0 0xf6 0x4 0x0 0xf7 0x4 0x0 0xf8 0x4>;
    			ti,hwmods = "mailbox4";
    			#mbox-cells = <0x1>;
    			ti,mbox-num-users = <0x4>;
    			ti,mbox-num-fifos = <0xc>;
    			status = "disabled";
    			phandle = <0x17f>;
    		};
    
    		mailbox@48840000 {
    			compatible = "ti,omap4-mailbox";
    			reg = <0x48840000 0x200>;
    			interrupts = <0x0 0xf9 0x4 0x0 0xfa 0x4 0x0 0xfb 0x4 0x0 0xfc 0x4>;
    			ti,hwmods = "mailbox5";
    			#mbox-cells = <0x1>;
    			ti,mbox-num-users = <0x4>;
    			ti,mbox-num-fifos = <0xc>;
    			status = "okay";
    			phandle = <0x180>;
    
    			mbox_ipu1_ipc3x {
    				ti,mbox-tx = <0x6 0x2 0x2>;
    				ti,mbox-rx = <0x4 0x2 0x2>;
    				status = "okay";
    				phandle = <0x181>;
    			};
    
    			mbox_dsp1_ipc3x {
    				ti,mbox-tx = <0x5 0x2 0x2>;
    				ti,mbox-rx = <0x1 0x2 0x2>;
    				status = "okay";
    				phandle = <0x182>;
    			};
    		};
    
    		mailbox@48842000 {
    			compatible = "ti,omap4-mailbox";
    			reg = <0x48842000 0x200>;
    			interrupts = <0x0 0xfd 0x4 0x0 0xfe 0x4 0x0 0xff 0x4 0x0 0x100 0x4>;
    			ti,hwmods = "mailbox6";
    			#mbox-cells = <0x1>;
    			ti,mbox-num-users = <0x4>;
    			ti,mbox-num-fifos = <0xc>;
    			status = "okay";
    			phandle = <0x183>;
    
    			mbox_ipu2_ipc3x {
    				ti,mbox-tx = <0x6 0x2 0x2>;
    				ti,mbox-rx = <0x4 0x2 0x2>;
    				status = "okay";
    				phandle = <0x184>;
    			};
    
    			mbox_dsp2_ipc3x {
    				ti,mbox-tx = <0x5 0x2 0x2>;
    				ti,mbox-rx = <0x1 0x2 0x2>;
    				status = "okay";
    				phandle = <0x185>;
    			};
    		};
    
    		mailbox@48844000 {
    			compatible = "ti,omap4-mailbox";
    			reg = <0x48844000 0x200>;
    			interrupts = <0x0 0x101 0x4 0x0 0x102 0x4 0x0 0x103 0x4 0x0 0x104 0x4>;
    			ti,hwmods = "mailbox7";
    			#mbox-cells = <0x1>;
    			ti,mbox-num-users = <0x4>;
    			ti,mbox-num-fifos = <0xc>;
    			status = "disabled";
    			phandle = <0x186>;
    		};
    
    		mailbox@48846000 {
    			compatible = "ti,omap4-mailbox";
    			reg = <0x48846000 0x200>;
    			interrupts = <0x0 0x105 0x4 0x0 0x106 0x4 0x0 0x107 0x4 0x0 0x108 0x4>;
    			ti,hwmods = "mailbox8";
    			#mbox-cells = <0x1>;
    			ti,mbox-num-users = <0x4>;
    			ti,mbox-num-fifos = <0xc>;
    			status = "disabled";
    			phandle = <0x187>;
    		};
    
    		mailbox@4885e000 {
    			compatible = "ti,omap4-mailbox";
    			reg = <0x4885e000 0x200>;
    			interrupts = <0x0 0x109 0x4 0x0 0x10a 0x4 0x0 0x10b 0x4 0x0 0x10c 0x4>;
    			ti,hwmods = "mailbox9";
    			#mbox-cells = <0x1>;
    			ti,mbox-num-users = <0x4>;
    			ti,mbox-num-fifos = <0xc>;
    			status = "disabled";
    			phandle = <0x188>;
    		};
    
    		mailbox@48860000 {
    			compatible = "ti,omap4-mailbox";
    			reg = <0x48860000 0x200>;
    			interrupts = <0x0 0x10d 0x4 0x0 0x10e 0x4 0x0 0x10f 0x4 0x0 0x110 0x4>;
    			ti,hwmods = "mailbox10";
    			#mbox-cells = <0x1>;
    			ti,mbox-num-users = <0x4>;
    			ti,mbox-num-fifos = <0xc>;
    			status = "disabled";
    			phandle = <0x189>;
    		};
    
    		mailbox@48862000 {
    			compatible = "ti,omap4-mailbox";
    			reg = <0x48862000 0x200>;
    			interrupts = <0x0 0x111 0x4 0x0 0x112 0x4 0x0 0x113 0x4 0x0 0x114 0x4>;
    			ti,hwmods = "mailbox11";
    			#mbox-cells = <0x1>;
    			ti,mbox-num-users = <0x4>;
    			ti,mbox-num-fifos = <0xc>;
    			status = "disabled";
    			phandle = <0x18a>;
    		};
    
    		mailbox@48864000 {
    			compatible = "ti,omap4-mailbox";
    			reg = <0x48864000 0x200>;
    			interrupts = <0x0 0x115 0x4 0x0 0x116 0x4 0x0 0x117 0x4 0x0 0x118 0x4>;
    			ti,hwmods = "mailbox12";
    			#mbox-cells = <0x1>;
    			ti,mbox-num-users = <0x4>;
    			ti,mbox-num-fifos = <0xc>;
    			status = "disabled";
    			phandle = <0x18b>;
    		};
    
    		mailbox@48802000 {
    			compatible = "ti,omap4-mailbox";
    			reg = <0x48802000 0x200>;
    			interrupts = <0x0 0x17b 0x4 0x0 0x17c 0x4 0x0 0x17d 0x4 0x0 0x17e 0x4>;
    			ti,hwmods = "mailbox13";
    			#mbox-cells = <0x1>;
    			ti,mbox-num-users = <0x4>;
    			ti,mbox-num-fifos = <0xc>;
    			status = "disabled";
    			phandle = <0x18c>;
    		};
    
    		timer@4ae18000 {
    			compatible = "ti,omap5430-timer";
    			reg = <0x4ae18000 0x80>;
    			interrupts = <0x0 0x20 0x4>;
    			ti,hwmods = "timer1";
    			ti,timer-alwon;
    			phandle = <0x18d>;
    		};
    
    		timer@48032000 {
    			compatible = "ti,omap5430-timer";
    			reg = <0x48032000 0x80>;
    			interrupts = <0x0 0x21 0x4>;
    			ti,hwmods = "timer2";
    			phandle = <0x18e>;
    		};
    
    		timer@48034000 {
    			compatible = "ti,omap5430-timer";
    			reg = <0x48034000 0x80>;
    			interrupts = <0x0 0x22 0x4>;
    			ti,hwmods = "timer3";
    			phandle = <0x18f>;
    		};
    
    		timer@48036000 {
    			compatible = "ti,omap5430-timer";
    			reg = <0x48036000 0x80>;
    			interrupts = <0x0 0x23 0x4>;
    			ti,hwmods = "timer4";
    			phandle = <0x190>;
    		};
    
    		timer@48820000 {
    			compatible = "ti,omap5430-timer";
    			reg = <0x48820000 0x80>;
    			interrupts = <0x0 0x24 0x4>;
    			ti,hwmods = "timer5";
    			phandle = <0x191>;
    		};
    
    		timer@48822000 {
    			compatible = "ti,omap5430-timer";
    			reg = <0x48822000 0x80>;
    			interrupts = <0x0 0x25 0x4>;
    			ti,hwmods = "timer6";
    			phandle = <0x192>;
    		};
    
    		timer@48824000 {
    			compatible = "ti,omap5430-timer";
    			reg = <0x48824000 0x80>;
    			interrupts = <0x0 0x26 0x4>;
    			ti,hwmods = "timer7";
    			phandle = <0x193>;
    		};
    
    		timer@48826000 {
    			compatible = "ti,omap5430-timer";
    			reg = <0x48826000 0x80>;
    			interrupts = <0x0 0x27 0x4>;
    			ti,hwmods = "timer8";
    			phandle = <0x194>;
    		};
    
    		timer@4803e000 {
    			compatible = "ti,omap5430-timer";
    			reg = <0x4803e000 0x80>;
    			interrupts = <0x0 0x28 0x4>;
    			ti,hwmods = "timer9";
    			phandle = <0x195>;
    		};
    
    		timer@48086000 {
    			compatible = "ti,omap5430-timer";
    			reg = <0x48086000 0x80>;
    			interrupts = <0x0 0x29 0x4>;
    			ti,hwmods = "timer10";
    			phandle = <0x196>;
    		};
    
    		timer@48088000 {
    			compatible = "ti,omap5430-timer";
    			reg = <0x48088000 0x80>;
    			interrupts = <0x0 0x2a 0x4>;
    			ti,hwmods = "timer11";
    			phandle = <0x197>;
    		};
    
    		timer@4ae20000 {
    			compatible = "ti,omap5430-timer";
    			reg = <0x4ae20000 0x80>;
    			interrupts = <0x0 0x5a 0x4>;
    			ti,hwmods = "timer12";
    			ti,timer-alwon;
    			ti,timer-secure;
    			phandle = <0x198>;
    		};
    
    		timer@48828000 {
    			compatible = "ti,omap5430-timer";
    			reg = <0x48828000 0x80>;
    			interrupts = <0x0 0x153 0x4>;
    			ti,hwmods = "timer13";
    			phandle = <0x199>;
    		};
    
    		timer@4882a000 {
    			compatible = "ti,omap5430-timer";
    			reg = <0x4882a000 0x80>;
    			interrupts = <0x0 0x154 0x4>;
    			ti,hwmods = "timer14";
    			phandle = <0x19a>;
    		};
    
    		timer@4882c000 {
    			compatible = "ti,omap5430-timer";
    			reg = <0x4882c000 0x80>;
    			interrupts = <0x0 0x155 0x4>;
    			ti,hwmods = "timer15";
    			phandle = <0x19b>;
    		};
    
    		timer@4882e000 {
    			compatible = "ti,omap5430-timer";
    			reg = <0x4882e000 0x80>;
    			interrupts = <0x0 0x156 0x4>;
    			ti,hwmods = "timer16";
    			phandle = <0x19c>;
    		};
    
    		wdt@4ae14000 {
    			compatible = "ti,omap3-wdt";
    			reg = <0x4ae14000 0x80>;
    			interrupts = <0x0 0x4b 0x4>;
    			ti,hwmods = "wd_timer2";
    			phandle = <0x19d>;
    		};
    
    		spinlock@4a0f6000 {
    			compatible = "ti,omap4-hwspinlock";
    			reg = <0x4a0f6000 0x1000>;
    			ti,hwmods = "spinlock";
    			#hwlock-cells = <0x1>;
    			phandle = <0x19e>;
    		};
    
    		dmm@4e000000 {
    			compatible = "ti,omap5-dmm";
    			reg = <0x4e000000 0x800>;
    			interrupts = <0x0 0x6c 0x4>;
    			ti,hwmods = "dmm";
    		};
    
    		i2c@48070000 {
    			compatible = "ti,omap4-i2c";
    			reg = <0x48070000 0x100>;
    			interrupts = <0x0 0x33 0x4>;
    			#address-cells = <0x1>;
    			#size-cells = <0x0>;
    			ti,hwmods = "i2c1";
    			status = "okay";
    			clock-frequency = <0x61a80>;
    			u-boot,dm-spl;
    			phandle = <0x19f>;
    
    			tps659038@58 {
    				compatible = "ti,tps659038";
    				reg = <0x58>;
    				interrupt-parent = <0xb1>;
    				interrupts = <0x0 0x8>;
    				#interrupt-cells = <0x2>;
    				interrupt-controller;
    				ti,system-power-controller;
    				ti,palmas-override-powerhold;
    				phandle = <0xb2>;
    
    				tps659038_pmic {
    					compatible = "ti,tps659038-pmic";
    
    					regulators {
    
    						smps12 {
    							regulator-name = "smps12";
    							regulator-min-microvolt = <0xcf850>;
    							regulator-max-microvolt = <0x1312d0>;
    							regulator-always-on;
    							regulator-boot-on;
    							phandle = <0x5>;
    						};
    
    						smps3 {
    							regulator-name = "smps3";
    							regulator-min-microvolt = <0x149970>;
    							regulator-max-microvolt = <0x149970>;
    							regulator-always-on;
    							regulator-boot-on;
    							phandle = <0xf0>;
    						};
    
    						smps45 {
    							regulator-name = "smps45";
    							regulator-min-microvolt = <0xcf850>;
    							regulator-max-microvolt = <0x1312d0>;
    							regulator-always-on;
    							regulator-boot-on;
    							phandle = <0x1a0>;
    						};
    
    						smps6 {
    							regulator-name = "smps6";
    							regulator-min-microvolt = <0xcf850>;
    							regulator-max-microvolt = <0x118c30>;
    							regulator-always-on;
    							regulator-boot-on;
    							phandle = <0x1a1>;
    						};
    
    						smps8 {
    							regulator-name = "smps8";
    							regulator-min-microvolt = <0x1b7740>;
    							regulator-max-microvolt = <0x1b7740>;
    							regulator-always-on;
    							regulator-boot-on;
    							phandle = <0x1a2>;
    						};
    
    						ldo1 {
    							regulator-name = "ldo1";
    							regulator-min-microvolt = <0x1b7740>;
    							regulator-max-microvolt = <0x325aa0>;
    							regulator-boot-on;
    							regulator-always-on;
    							phandle = <0xb8>;
    						};
    
    						ldo2 {
    							regulator-name = "ldo2";
    							regulator-min-microvolt = <0x325aa0>;
    							regulator-max-microvolt = <0x325aa0>;
    							regulator-always-on;
    							regulator-boot-on;
    							phandle = <0x1a3>;
    						};
    
    						ldo3 {
    							regulator-name = "ldo3";
    							regulator-min-microvolt = <0x1b7740>;
    							regulator-max-microvolt = <0x1b7740>;
    							regulator-always-on;
    							regulator-boot-on;
    							phandle = <0x1a4>;
    						};
    
    						ldo4 {
    							regulator-name = "ldo4";
    							regulator-min-microvolt = <0x1b7740>;
    							regulator-max-microvolt = <0x1b7740>;
    							regulator-always-on;
    							regulator-boot-on;
    							phandle = <0x1a5>;
    						};
    
    						ldo9 {
    							regulator-name = "ldo9";
    							regulator-min-microvolt = <0x100590>;
    							regulator-max-microvolt = <0x100590>;
    							regulator-always-on;
    							regulator-boot-on;
    							phandle = <0x1a6>;
    						};
    
    						ldoln {
    							regulator-name = "ldoln";
    							regulator-min-microvolt = <0x1b7740>;
    							regulator-max-microvolt = <0x1b7740>;
    							regulator-always-on;
    							regulator-boot-on;
    							phandle = <0x1a7>;
    						};
    
    						ldousb {
    							regulator-name = "ldousb";
    							regulator-min-microvolt = <0x325aa0>;
    							regulator-max-microvolt = <0x325aa0>;
    							regulator-boot-on;
    							phandle = <0xc6>;
    						};
    
    						regen1 {
    							regulator-name = "regen1";
    							regulator-boot-on;
    							regulator-always-on;
    							phandle = <0xef>;
    						};
    					};
    				};
    
    				tps659038_rtc {
    					compatible = "ti,palmas-rtc";
    					interrupt-parent = <0xb2>;
    					interrupts = <0x8 0x2>;
    					wakeup-source;
    					phandle = <0x1a8>;
    				};
    
    				tps659038_pwr_button {
    					compatible = "ti,palmas-pwrbutton";
    					interrupt-parent = <0xb2>;
    					interrupts = <0x1 0x2>;
    					wakeup-source;
    					ti,palmas-long-press-seconds = <0xc>;
    					phandle = <0x1a9>;
    				};
    
    				tps659038_gpio {
    					compatible = "ti,palmas-gpio";
    					gpio-controller;
    					#gpio-cells = <0x2>;
    					phandle = <0x1aa>;
    				};
    			};
    		};
    
    		i2c@48072000 {
    			compatible = "ti,omap4-i2c";
    			reg = <0x48072000 0x100>;
    			interrupts = <0x0 0x34 0x4>;
    			#address-cells = <0x1>;
    			#size-cells = <0x0>;
    			ti,hwmods = "i2c2";
    			status = "disabled";
    			phandle = <0x1ab>;
    		};
    
    		i2c@48060000 {
    			compatible = "ti,omap4-i2c";
    			reg = <0x48060000 0x100>;
    			interrupts = <0x0 0x38 0x4>;
    			#address-cells = <0x1>;
    			#size-cells = <0x0>;
    			ti,hwmods = "i2c3";
    			status = "okay";
    			clock-frequency = <0x61a80>;
    			phandle = <0x1ac>;
    
    			rtc@6f {
    				compatible = "microchip,mcp7941x";
    				reg = <0x6f>;
    				interrupts-extended = <0x1 0x0 0x2 0x1 0xb0 0x424>;
    				interrupt-names = "irq", "wakeup";
    				vcc-supply = <0xb3>;
    				wakeup-source;
    				phandle = <0x1ad>;
    			};
    		};
    
    		i2c@4807a000 {
    			compatible = "ti,omap4-i2c";
    			reg = <0x4807a000 0x100>;
    			interrupts = <0x0 0x39 0x4>;
    			#address-cells = <0x1>;
    			#size-cells = <0x0>;
    			ti,hwmods = "i2c4";
    			status = "disabled";
    			phandle = <0x1ae>;
    		};
    
    		i2c@4807c000 {
    			compatible = "ti,omap4-i2c";
    			reg = <0x4807c000 0x100>;
    			interrupts = <0x0 0x37 0x4>;
    			#address-cells = <0x1>;
    			#size-cells = <0x0>;
    			ti,hwmods = "i2c5";
    			status = "disabled";
    			phandle = <0x1af>;
    		};
    
    		mmc@4809c000 {
    			compatible = "ti,dra7-hsmmc", "ti,omap4-hsmmc";
    			reg = <0x4809c000 0x400>;
    			interrupts = <0x0 0x4e 0x4>;
    			ti,hwmods = "mmc1";
    			ti,dual-volt;
    			ti,needs-special-reset;
    			dmas = <0xaf 0x3d 0xaf 0x3e>;
    			dma-names = "tx", "rx";
    			status = "okay";
    			pbias-supply = <0xb4>;
    			max-frequency = <0xb71b000>;
    			pinctrl-names = "default", "hs";
    			pinctrl-0 = <0xb5>;
    			bus-width = <0x4>;
    			cd-gpios = <0xb6 0x1b 0x1>;
    			pinctrl-1 = <0xb7>;
    			vmmc-supply = <0xb8>;
    			u-boot,dm-spl;
    			phandle = <0x1b0>;
    		};
    
    		mmc@480b4000 {
    			compatible = "ti,dra7-hsmmc", "ti,omap4-hsmmc";
    			reg = <0x480b4000 0x400>;
    			interrupts = <0x0 0x51 0x4>;
    			ti,hwmods = "mmc2";
    			ti,needs-special-reset;
    			dmas = <0xaf 0x2f 0xaf 0x30>;
    			dma-names = "tx", "rx";
    			status = "disabled";
    			max-frequency = <0xb71b000>;
    			sd-uhs-sdr25;
    			sd-uhs-sdr12;
    			mmc-hs200-1_8v;
    			mmc-ddr-1_8v;
    			u-boot,dm-spl;
    			phandle = <0x1b1>;
    		};
    
    		mmc@480ad000 {
    			compatible = "ti,dra7-hsmmc", "ti,omap4-hsmmc";
    			reg = <0x480ad000 0x400>;
    			interrupts = <0x0 0x59 0x4>;
    			ti,hwmods = "mmc3";
    			ti,needs-special-reset;
    			dmas = <0xaf 0x4d 0xaf 0x4e>;
    			dma-names = "tx", "rx";
    			status = "disabled";
    			max-frequency = <0x3d09000>;
    			sd-uhs-sdr12;
    			sd-uhs-sdr25;
    			sd-uhs-sdr50;
    			phandle = <0x1b2>;
    		};
    
    		mmc@480d1000 {
    			compatible = "ti,dra7-hsmmc", "ti,omap4-hsmmc";
    			reg = <0x480d1000 0x400>;
    			interrupts = <0x0 0x5b 0x4>;
    			ti,hwmods = "mmc4";
    			ti,needs-special-reset;
    			dmas = <0xaf 0x39 0xaf 0x3a>;
    			dma-names = "tx", "rx";
    			status = "disabled";
    			max-frequency = <0xb71b000>;
    			sd-uhs-sdr12;
    			sd-uhs-sdr25;
    			phandle = <0x1b3>;
    		};
    
    		mmu@40d01000 {
    			compatible = "ti,dra7-dsp-iommu";
    			reg = <0x40d01000 0x100>;
    			interrupts = <0x0 0x17 0x4>;
    			ti,hwmods = "mmu0_dsp1";
    			#iommu-cells = <0x0>;
    			ti,syscon-mmuconfig = <0xb9 0x0>;
    			status = "disabled";
    			phandle = <0x1b4>;
    		};
    
    		mmu@40d02000 {
    			compatible = "ti,dra7-dsp-iommu";
    			reg = <0x40d02000 0x100>;
    			interrupts = <0x0 0x91 0x4>;
    			ti,hwmods = "mmu1_dsp1";
    			#iommu-cells = <0x0>;
    			ti,syscon-mmuconfig = <0xb9 0x1>;
    			status = "disabled";
    			phandle = <0x1b5>;
    		};
    
    		mmu@58882000 {
    			compatible = "ti,dra7-iommu";
    			reg = <0x58882000 0x100>;
    			interrupts = <0x0 0x18b 0x4>;
    			ti,hwmods = "mmu_ipu1";
    			#iommu-cells = <0x0>;
    			ti,iommu-bus-err-back;
    			status = "disabled";
    			phandle = <0x1b6>;
    		};
    
    		mmu@55082000 {
    			compatible = "ti,dra7-iommu";
    			reg = <0x55082000 0x100>;
    			interrupts = <0x0 0x18c 0x4>;
    			ti,hwmods = "mmu_ipu2";
    			#iommu-cells = <0x0>;
    			ti,iommu-bus-err-back;
    			status = "disabled";
    			phandle = <0x1b7>;
    		};
    
    		regulator-abb-mpu {
    			compatible = "ti,abb-v3";
    			regulator-name = "abb_mpu";
    			#address-cells = <0x0>;
    			#size-cells = <0x0>;
    			clocks = <0x10>;
    			ti,settling-time = <0x32>;
    			ti,clock-cycles = <0x10>;
    			reg = <0x4ae07ddc 0x4 0x4ae07de0 0x4 0x4ae06014 0x4 0x4a003b20 0xc 0x4ae0c158 0x4>;
    			reg-names = "setup-address", "control-address", "int-address", "efuse-address", "ldo-address";
    			ti,tranxdone-status-mask = <0x80>;
    			ti,ldovbb-override-mask = <0x400>;
    			ti,ldovbb-vset-mask = <0x1f>;
    			ti,abb_info = <0x102ca0 0x0 0x0 0x0 0x2000000 0x1f00000 0x11b340 0x0 0x4 0x0 0x2000000 0x1f00000 0x127690 0x0 0x8 0x0 0x2000000 0x1f00000>;
    			phandle = <0x1b8>;
    		};
    
    		regulator-abb-ivahd {
    			compatible = "ti,abb-v3";
    			regulator-name = "abb_ivahd";
    			#address-cells = <0x0>;
    			#size-cells = <0x0>;
    			clocks = <0x10>;
    			ti,settling-time = <0x32>;
    			ti,clock-cycles = <0x10>;
    			reg = <0x4ae07e34 0x4 0x4ae07e24 0x4 0x4ae06010 0x4 0x4a0025cc 0xc 0x4a002470 0x4>;
    			reg-names = "setup-address", "control-address", "int-address", "efuse-address", "ldo-address";
    			ti,tranxdone-status-mask = <0x40000000>;
    			ti,ldovbb-override-mask = <0x400>;
    			ti,ldovbb-vset-mask = <0x1f>;
    			ti,abb_info = <0x101918 0x0 0x0 0x0 0x2000000 0x1f00000 0x118c30 0x0 0x4 0x0 0x2000000 0x1f00000 0x1312d0 0x0 0x8 0x0 0x2000000 0x1f00000>;
    			phandle = <0x1b9>;
    		};
    
    		regulator-abb-dspeve {
    			compatible = "ti,abb-v3";
    			regulator-name = "abb_dspeve";
    			#address-cells = <0x0>;
    			#size-cells = <0x0>;
    			clocks = <0x10>;
    			ti,settling-time = <0x32>;
    			ti,clock-cycles = <0x10>;
    			reg = <0x4ae07e30 0x4 0x4ae07e20 0x4 0x4ae06010 0x4 0x4a0025e0 0xc 0x4a00246c 0x4>;
    			reg-names = "setup-address", "control-address", "int-address", "efuse-address", "ldo-address";
    			ti,tranxdone-status-mask = <0x20000000>;
    			ti,ldovbb-override-mask = <0x400>;
    			ti,ldovbb-vset-mask = <0x1f>;
    			ti,abb_info = <0x101918 0x0 0x0 0x0 0x2000000 0x1f00000 0x118c30 0x0 0x4 0x0 0x2000000 0x1f00000 0x1312d0 0x0 0x8 0x0 0x2000000 0x1f00000>;
    			phandle = <0x1ba>;
    		};
    
    		regulator-abb-gpu {
    			compatible = "ti,abb-v3";
    			regulator-name = "abb_gpu";
    			#address-cells = <0x0>;
    			#size-cells = <0x0>;
    			clocks = <0x10>;
    			ti,settling-time = <0x32>;
    			ti,clock-cycles = <0x10>;
    			reg = <0x4ae07de4 0x4 0x4ae07de8 0x4 0x4ae06010 0x4 0x4a003b08 0xc 0x4ae0c154 0x4>;
    			reg-names = "setup-address", "control-address", "int-address", "efuse-address", "ldo-address";
    			ti,tranxdone-status-mask = <0x10000000>;
    			ti,ldovbb-override-mask = <0x400>;
    			ti,ldovbb-vset-mask = <0x1f>;
    			ti,abb_info = <0x10a1d0 0x0 0x0 0x0 0x2000000 0x1f00000 0x127690 0x0 0x4 0x0 0x2000000 0x1f00000 0x138800 0x0 0x8 0x0 0x2000000 0x1f00000>;
    			phandle = <0x1bb>;
    		};
    
    		spi@48098000 {
    			compatible = "ti,omap4-mcspi";
    			reg = <0x48098000 0x200>;
    			interrupts = <0x0 0x3c 0x4>;
    			#address-cells = <0x1>;
    			#size-cells = <0x0>;
    			ti,hwmods = "mcspi1";
    			ti,spi-num-cs = <0x4>;
    			dmas = <0xaf 0x23 0xaf 0x24 0xaf 0x25 0xaf 0x26 0xaf 0x27 0xaf 0x28 0xaf 0x29 0xaf 0x2a>;
    			dma-names = "tx0", "rx0", "tx1", "rx1", "tx2", "rx2", "tx3", "rx3";
    			status = "disabled";
    			phandle = <0x1bc>;
    		};
    
    		spi@4809a000 {
    			compatible = "ti,omap4-mcspi";
    			reg = <0x4809a000 0x200>;
    			interrupts = <0x0 0x3d 0x4>;
    			#address-cells = <0x1>;
    			#size-cells = <0x0>;
    			ti,hwmods = "mcspi2";
    			ti,spi-num-cs = <0x2>;
    			dmas = <0xaf 0x2b 0xaf 0x2c 0xaf 0x2d 0xaf 0x2e>;
    			dma-names = "tx0", "rx0", "tx1", "rx1";
    			status = "disabled";
    			phandle = <0x1bd>;
    		};
    
    		spi@480b8000 {
    			compatible = "ti,omap4-mcspi";
    			reg = <0x480b8000 0x200>;
    			interrupts = <0x0 0x56 0x4>;
    			#address-cells = <0x1>;
    			#size-cells = <0x0>;
    			ti,hwmods = "mcspi3";
    			ti,spi-num-cs = <0x2>;
    			dmas = <0xaf 0xf 0xaf 0x10>;
    			dma-names = "tx0", "rx0";
    			status = "disabled";
    			phandle = <0x1be>;
    		};
    
    		spi@480ba000 {
    			compatible = "ti,omap4-mcspi";
    			reg = <0x480ba000 0x200>;
    			interrupts = <0x0 0x2b 0x4>;
    			#address-cells = <0x1>;
    			#size-cells = <0x0>;
    			ti,hwmods = "mcspi4";
    			ti,spi-num-cs = <0x1>;
    			dmas = <0xaf 0x46 0xaf 0x47>;
    			dma-names = "tx0", "rx0";
    			status = "disabled";
    			phandle = <0x1bf>;
    		};
    
    		qspi@4b300000 {
    			compatible = "ti,dra7xxx-qspi";
    			reg = <0x4b300000 0x100 0x5c000000 0x4000000>;
    			reg-names = "qspi_base", "qspi_mmap";
    			syscon-chipselects = <0x8 0x558>;
    			#address-cells = <0x1>;
    			#size-cells = <0x0>;
    			ti,hwmods = "qspi";
    			clocks = <0xba>;
    			clock-names = "fck";
    			num-cs = <0x4>;
    			interrupts = <0x0 0x157 0x4>;
    			status = "disabled";
    			u-boot,dm-spl;
    			phandle = <0x1c0>;
    
    			m25p80@0 {
    				compatible = "spi-flash";
    				u-boot,dm-spl;
    			};
    		};
    
    		ocp2scp@4a090000 {
    			compatible = "ti,omap-ocp2scp", "simple-bus";
    			#address-cells = <0x1>;
    			#size-cells = <0x1>;
    			ranges;
    			reg = <0x4a090000 0x20>;
    			ti,hwmods = "ocp2scp3";
    
    			phy@4A096000 {
    				compatible = "ti,phy-pipe3-sata";
    				reg = <0x4a096000 0x80 0x4a096400 0x64 0x4a096800 0x40>;
    				reg-names = "phy_rx", "phy_tx", "pll_ctrl";
    				syscon-phy-power = <0x8 0x374>;
    				clocks = <0x10 0xbb>;
    				clock-names = "sysclk", "refclk";
    				syscon-pllreset = <0x8 0x3fc>;
    				#phy-cells = <0x0>;
    				phandle = <0xc3>;
    			};
    
    			pciephy@4a094000 {
    				compatible = "ti,phy-pipe3-pcie";
    				reg = <0x4a094000 0x80 0x4a094400 0x64>;
    				reg-names = "phy_rx", "phy_tx";
    				syscon-phy-power = <0xbc 0x1c>;
    				syscon-pcs = <0xbc 0x10>;
    				clocks = <0x58 0x59 0xbd 0xbe 0xbf 0x5d 0x10>;
    				clock-names = "dpll_ref", "dpll_ref_m2", "wkupclk", "refclk", "div-clk", "phy-div", "sysclk";
    				#phy-cells = <0x0>;
    				phandle = <0xa8>;
    			};
    
    			pciephy@4a095000 {
    				compatible = "ti,phy-pipe3-pcie";
    				reg = <0x4a095000 0x80 0x4a095400 0x64>;
    				reg-names = "phy_rx", "phy_tx";
    				syscon-phy-power = <0xbc 0x20>;
    				syscon-pcs = <0xbc 0x10>;
    				clocks = <0x58 0x59 0xc0 0xc1 0xc2 0x5d 0x10>;
    				clock-names = "dpll_ref", "dpll_ref_m2", "wkupclk", "refclk", "div-clk", "phy-div", "sysclk";
    				#phy-cells = <0x0>;
    				status = "disabled";
    				phandle = <0xab>;
    			};
    		};
    
    		sata@4a141100 {
    			compatible = "snps,dwc-ahci";
    			reg = <0x4a140000 0x1100 0x4a141100 0x7>;
    			interrupts = <0x0 0x31 0x4>;
    			phys = <0xc3>;
    			phy-names = "sata-phy";
    			clocks = <0xbb>;
    			ti,hwmods = "sata";
    			ports-implemented = <0x1>;
    			status = "disabled";
    			phandle = <0x1c1>;
    		};
    
    		rtc@48838000 {
    			compatible = "ti,am3352-rtc";
    			reg = <0x48838000 0x100>;
    			interrupts = <0x0 0xd9 0x4 0x0 0xd9 0x4>;
    			ti,hwmods = "rtcss";
    			clocks = <0x50>;
    			phandle = <0x1c2>;
    		};
    
    		ocp2scp@4a080000 {
    			compatible = "ti,omap-ocp2scp", "simple-bus";
    			#address-cells = <0x1>;
    			#size-cells = <0x1>;
    			ranges;
    			reg = <0x4a080000 0x20>;
    			ti,hwmods = "ocp2scp1";
    			u-boot,dm-spl;
    
    			phy@4a084000 {
    				compatible = "ti,dra7x-usb2", "ti,omap-usb2";
    				reg = <0x4a084000 0x400>;
    				syscon-phy-power = <0x8 0x300>;
    				clocks = <0xc4 0xc5>;
    				clock-names = "wkupclk", "refclk";
    				#phy-cells = <0x0>;
    				phy-supply = <0xc6>;
    				u-boot,dm-spl;
    				phandle = <0xca>;
    			};
    
    			phy@4a085000 {
    				compatible = "ti,dra7x-usb2-phy2", "ti,omap-usb2";
    				reg = <0x4a085000 0x400>;
    				syscon-phy-power = <0x8 0xe74>;
    				clocks = <0xc7 0xc8>;
    				clock-names = "wkupclk", "refclk";
    				#phy-cells = <0x0>;
    				phy-supply = <0xc6>;
    				phandle = <0xcc>;
    			};
    
    			phy@4a084400 {
    				compatible = "ti,omap-usb3";
    				reg = <0x4a084400 0x80 0x4a084800 0x64 0x4a084c00 0x40>;
    				reg-names = "phy_rx", "phy_tx", "pll_ctrl";
    				syscon-phy-power = <0x8 0x370>;
    				clocks = <0xc9 0x10 0xc5>;
    				clock-names = "wkupclk", "sysclk", "refclk";
    				#phy-cells = <0x0>;
    				u-boot,dm-spl;
    				phandle = <0xcb>;
    			};
    		};
    
    		omap_dwc3_1@48880000 {
    			compatible = "ti,dwc3";
    			ti,hwmods = "usb_otg_ss1";
    			reg = <0x48880000 0x10000>;
    			interrupts = <0x0 0x48 0x4>;
    			#address-cells = <0x1>;
    			#size-cells = <0x1>;
    			utmi-mode = <0x2>;
    			ranges;
    			u-boot,dm-spl;
    			phandle = <0x1c3>;
    
    			usb@48890000 {
    				compatible = "snps,dwc3";
    				reg = <0x48890000 0x17000>;
    				interrupts = <0x0 0x47 0x4 0x0 0x47 0x4 0x0 0x48 0x4>;
    				interrupt-names = "peripheral", "host", "otg";
    				phys = <0xca 0xcb>;
    				phy-names = "usb2-phy", "usb3-phy";
    				maximum-speed = "super-speed";
    				dr_mode = "host";
    				snps,dis_u3_susphy_quirk;
    				snps,dis_u2_susphy_quirk;
    				u-boot,dm-spl;
    				phandle = <0x1c4>;
    			};
    		};
    
    		omap_dwc3_2@488c0000 {
    			compatible = "ti,dwc3";
    			ti,hwmods = "usb_otg_ss2";
    			reg = <0x488c0000 0x10000>;
    			interrupts = <0x0 0x57 0x4>;
    			#address-cells = <0x1>;
    			#size-cells = <0x1>;
    			utmi-mode = <0x2>;
    			ranges;
    			phandle = <0x1c5>;
    
    			usb@488d0000 {
    				compatible = "snps,dwc3";
    				reg = <0x488d0000 0x17000>;
    				interrupts = <0x0 0x49 0x4 0x0 0x49 0x4 0x0 0x57 0x4>;
    				interrupt-names = "peripheral", "host", "otg";
    				phys = <0xcc>;
    				phy-names = "usb2-phy";
    				maximum-speed = "high-speed";
    				dr_mode = "host";
    				snps,dis_u3_susphy_quirk;
    				snps,dis_u2_susphy_quirk;
    				phandle = <0x1c6>;
    			};
    		};
    
    		omap_dwc3_3@48900000 {
    			compatible = "ti,dwc3";
    			ti,hwmods = "usb_otg_ss3";
    			reg = <0x48900000 0x10000>;
    			interrupts = <0x0 0x158 0x4>;
    			#address-cells = <0x1>;
    			#size-cells = <0x1>;
    			utmi-mode = <0x2>;
    			ranges;
    			status = "disabled";
    			phandle = <0x1c7>;
    
    			usb@48910000 {
    				compatible = "snps,dwc3";
    				reg = <0x48910000 0x17000>;
    				interrupts = <0x0 0x58 0x4 0x0 0x58 0x4 0x0 0x158 0x4>;
    				interrupt-names = "peripheral", "host", "otg";
    				maximum-speed = "high-speed";
    				dr_mode = "otg";
    				snps,dis_u3_susphy_quirk;
    				snps,dis_u2_susphy_quirk;
    				phandle = <0x1c8>;
    			};
    		};
    
    		elm@48078000 {
    			compatible = "ti,am3352-elm";
    			reg = <0x48078000 0xfc0>;
    			interrupts = <0x0 0x1 0x4>;
    			ti,hwmods = "elm";
    			status = "disabled";
    			phandle = <0x1c9>;
    		};
    
    		gpmc@50000000 {
    			compatible = "ti,am3352-gpmc";
    			ti,hwmods = "gpmc";
    			reg = <0x50000000 0x37c>;
    			interrupts = <0x0 0xf 0x4>;
    			dmas = <0xcd 0x4 0x0>;
    			dma-names = "rxtx";
    			gpmc,num-cs = <0x8>;
    			gpmc,num-waitpins = <0x2>;
    			#address-cells = <0x2>;
    			#size-cells = <0x1>;
    			interrupt-controller;
    			#interrupt-cells = <0x2>;
    			gpio-controller;
    			#gpio-cells = <0x2>;
    			status = "disabled";
    			phandle = <0x1ca>;
    		};
    
    		atl@4843c000 {
    			compatible = "ti,dra7-atl";
    			reg = <0x4843c000 0x3ff>;
    			ti,hwmods = "atl";
    			ti,provided-clocks = <0x43 0x42 0x41 0x40>;
    			clocks = <0xf>;
    			clock-names = "fck";
    			status = "disabled";
    			phandle = <0x1cb>;
    		};
    
    		mcasp@48460000 {
    			compatible = "ti,dra7-mcasp-audio";
    			ti,hwmods = "mcasp1";
    			reg = <0x48460000 0x2000 0x45800000 0x1000>;
    			reg-names = "mpu", "dat";
    			interrupts = <0x0 0x68 0x4 0x0 0x67 0x4>;
    			interrupt-names = "tx", "rx";
    			dmas = <0xcd 0x81 0x1 0xcd 0x80 0x1>;
    			dma-names = "tx", "rx";
    			clocks = <0xce 0xcf 0xd0>;
    			clock-names = "fck", "ahclkx", "ahclkr";
    			status = "disabled";
    			phandle = <0x1cc>;
    		};
    
    		mcasp@48464000 {
    			compatible = "ti,dra7-mcasp-audio";
    			ti,hwmods = "mcasp2";
    			reg = <0x48464000 0x2000 0x45c00000 0x1000>;
    			reg-names = "mpu", "dat";
    			interrupts = <0x0 0x95 0x4 0x0 0x94 0x4>;
    			interrupt-names = "tx", "rx";
    			dmas = <0xcd 0x83 0x1 0xcd 0x82 0x1>;
    			dma-names = "tx", "rx";
    			clocks = <0xd1 0xd2 0xd3>;
    			clock-names = "fck", "ahclkx", "ahclkr";
    			status = "disabled";
    			phandle = <0x1cd>;
    		};
    
    		mcasp@48468000 {
    			compatible = "ti,dra7-mcasp-audio";
    			ti,hwmods = "mcasp3";
    			reg = <0x48468000 0x2000 0x46000000 0x1000>;
    			reg-names = "mpu", "dat";
    			interrupts = <0x0 0x97 0x4 0x0 0x96 0x4>;
    			interrupt-names = "tx", "rx";
    			dmas = <0xcd 0x85 0x1 0xcd 0x84 0x1>;
    			dma-names = "tx", "rx";
    			clocks = <0xd4 0xd5>;
    			clock-names = "fck", "ahclkx";
    			status = "disabled";
    			phandle = <0x1ce>;
    		};
    
    		mcasp@4846c000 {
    			compatible = "ti,dra7-mcasp-audio";
    			ti,hwmods = "mcasp4";
    			reg = <0x4846c000 0x2000 0x48436000 0x1000>;
    			reg-names = "mpu", "dat";
    			interrupts = <0x0 0x99 0x4 0x0 0x98 0x4>;
    			interrupt-names = "tx", "rx";
    			dmas = <0xcd 0x87 0x1 0xcd 0x86 0x1>;
    			dma-names = "tx", "rx";
    			clocks = <0xd6 0xd7>;
    			clock-names = "fck", "ahclkx";
    			status = "disabled";
    			phandle = <0x1cf>;
    		};
    
    		mcasp@48470000 {
    			compatible = "ti,dra7-mcasp-audio";
    			ti,hwmods = "mcasp5";
    			reg = <0x48470000 0x2000 0x4843a000 0x1000>;
    			reg-names = "mpu", "dat";
    			interrupts = <0x0 0x9b 0x4 0x0 0x9a 0x4>;
    			interrupt-names = "tx", "rx";
    			dmas = <0xcd 0x89 0x1 0xcd 0x88 0x1>;
    			dma-names = "tx", "rx";
    			clocks = <0xd8 0xd9>;
    			clock-names = "fck", "ahclkx";
    			status = "disabled";
    			phandle = <0x1d0>;
    		};
    
    		mcasp@48474000 {
    			compatible = "ti,dra7-mcasp-audio";
    			ti,hwmods = "mcasp6";
    			reg = <0x48474000 0x2000 0x4844c000 0x1000>;
    			reg-names = "mpu", "dat";
    			interrupts = <0x0 0x9d 0x4 0x0 0x9c 0x4>;
    			interrupt-names = "tx", "rx";
    			dmas = <0xcd 0x8b 0x1 0xcd 0x8a 0x1>;
    			dma-names = "tx", "rx";
    			clocks = <0xda 0xdb>;
    			clock-names = "fck", "ahclkx";
    			status = "disabled";
    			phandle = <0x1d1>;
    		};
    
    		mcasp@48478000 {
    			compatible = "ti,dra7-mcasp-audio";
    			ti,hwmods = "mcasp7";
    			reg = <0x48478000 0x2000 0x48450000 0x1000>;
    			reg-names = "mpu", "dat";
    			interrupts = <0x0 0x9f 0x4 0x0 0x9e 0x4>;
    			interrupt-names = "tx", "rx";
    			dmas = <0xcd 0x8d 0x1 0xcd 0x8c 0x1>;
    			dma-names = "tx", "rx";
    			clocks = <0xdc 0xdd>;
    			clock-names = "fck", "ahclkx";
    			status = "disabled";
    			phandle = <0x1d2>;
    		};
    
    		mcasp@4847c000 {
    			compatible = "ti,dra7-mcasp-audio";
    			ti,hwmods = "mcasp8";
    			reg = <0x4847c000 0x2000 0x48454000 0x1000>;
    			reg-names = "mpu", "dat";
    			interrupts = <0x0 0xa1 0x4 0x0 0xa0 0x4>;
    			interrupt-names = "tx", "rx";
    			dmas = <0xcd 0x8f 0x1 0xcd 0x8e 0x1>;
    			dma-names = "tx", "rx";
    			clocks = <0xde 0xdf>;
    			clock-names = "fck", "ahclkx";
    			status = "disabled";
    			phandle = <0x1d3>;
    		};
    
    		crossbar@4a002a48 {
    			compatible = "ti,irq-crossbar";
    			reg = <0x4a002a48 0x130>;
    			interrupt-controller;
    			interrupt-parent = <0x7>;
    			#interrupt-cells = <0x3>;
    			ti,max-irqs = <0xa0>;
    			ti,max-crossbar-sources = <0x190>;
    			ti,reg-size = <0x2>;
    			ti,irqs-reserved = <0x0 0x1 0x2 0x3 0x5 0x6 0x83 0x84>;
    			ti,irqs-skip = <0xa 0x85 0x8b 0x8c>;
    			ti,irqs-safe-map = <0x0>;
    			phandle = <0x1>;
    		};
    
    		ethernet@48484000 {
    			compatible = "ti,dra7-cpsw", "ti,cpsw";
    			ti,hwmods = "gmac";
    			clocks = <0xe0 0xe1>;
    			clock-names = "fck", "cpts";
    			cpdma_channels = <0x8>;
    			ale_entries = <0x400>;
    			bd_ram_size = <0x2000>;
    			mac_control = <0x20>;
    			slaves = <0x2>;
    			active_slave = <0x0>;
    			cpts_clock_mult = <0x784cfe14>;
    			cpts_clock_shift = <0x1d>;
    			reg = <0x48484000 0x1000 0x48485200 0x2e00>;
    			#address-cells = <0x1>;
    			#size-cells = <0x1>;
    			ti,no-idle;
    			interrupts = <0x0 0x14e 0x4 0x0 0x14f 0x4 0x0 0x150 0x4 0x0 0x151 0x4>;
    			ranges;
    			syscon = <0x8>;
    			status = "disabled";
    			phandle = <0x1d4>;
    
    			mdio@48485000 {
    				compatible = "ti,cpsw-mdio", "ti,davinci_mdio";
    				#address-cells = <0x1>;
    				#size-cells = <0x0>;
    				ti,hwmods = "davinci_mdio";
    				bus_freq = <0xf4240>;
    				reg = <0x48485000 0x100>;
    				phandle = <0x1d5>;
    			};
    
    			slave@48480200 {
    				mac-address = [00 00 00 00 00 00];
    				phandle = <0x1d6>;
    			};
    
    			slave@48480300 {
    				mac-address = [00 00 00 00 00 00];
    				phandle = <0x1d7>;
    			};
    
    			cpsw-phy-sel@4a002554 {
    				compatible = "ti,dra7xx-cpsw-phy-sel";
    				reg = <0x4a002554 0x4>;
    				reg-names = "gmii-sel";
    				phandle = <0x1d8>;
    			};
    		};
    
    		can@481cc000 {
    			compatible = "ti,dra7-d_can";
    			ti,hwmods = "dcan1";
    			reg = <0x4ae3c000 0x2000>;
    			syscon-raminit = <0x8 0x558 0x0>;
    			interrupts = <0x0 0xde 0x4>;
    			clocks = <0xe2>;
    			status = "disabled";
    			phandle = <0x1d9>;
    		};
    
    		can@481d0000 {
    			compatible = "ti,dra7-d_can";
    			ti,hwmods = "dcan2";
    			reg = <0x48480000 0x2000>;
    			syscon-raminit = <0x8 0x558 0x1>;
    			interrupts = <0x0 0xe1 0x4>;
    			clocks = <0x10>;
    			status = "disabled";
    			phandle = <0x1da>;
    		};
    
    		dss@58000000 {
    			compatible = "ti,dra7-dss";
    			status = "disabled";
    			ti,hwmods = "dss_core";
    			syscon-pll-ctrl = <0x8 0x538>;
    			#address-cells = <0x1>;
    			#size-cells = <0x1>;
    			ranges;
    			reg = <0x58000000 0x80 0x58004054 0x4 0x58004300 0x20 0x58009054 0x4 0x58009300 0x20>;
    			reg-names = "dss", "pll1_clkctrl", "pll1", "pll2_clkctrl", "pll2";
    			clocks = <0xe3 0xe4 0xe5>;
    			clock-names = "fck", "video1_clk", "video2_clk";
    			phandle = <0x1db>;
    
    			dispc@58001000 {
    				compatible = "ti,dra7-dispc";
    				reg = <0x58001000 0x1000>;
    				interrupts = <0x0 0x14 0x4>;
    				ti,hwmods = "dss_dispc";
    				clocks = <0xe3>;
    				clock-names = "fck";
    				syscon-pol = <0x8 0x534>;
    			};
    
    			encoder@58060000 {
    				compatible = "ti,dra7-hdmi";
    				reg = <0x58040000 0x200 0x58040200 0x80 0x58040300 0x80 0x58060000 0x19000>;
    				reg-names = "wp", "pll", "phy", "core";
    				interrupts = <0x0 0x60 0x4>;
    				status = "disabled";
    				ti,hwmods = "dss_hdmi";
    				clocks = <0xe6 0xe7>;
    				clock-names = "fck", "sys_clk";
    				phandle = <0x1dc>;
    			};
    		};
    
    		epwmss@4843e000 {
    			compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
    			reg = <0x4843e000 0x30>;
    			ti,hwmods = "epwmss0";
    			#address-cells = <0x1>;
    			#size-cells = <0x1>;
    			status = "disabled";
    			ranges;
    			phandle = <0x1dd>;
    
    			pwm@4843e200 {
    				compatible = "ti,dra746-ehrpwm", "ti,am3352-ehrpwm";
    				#pwm-cells = <0x3>;
    				reg = <0x4843e200 0x80>;
    				clocks = <0xe8 0xa>;
    				clock-names = "tbclk", "fck";
    				status = "disabled";
    				phandle = <0x1de>;
    			};
    
    			ecap@4843e100 {
    				compatible = "ti,dra746-ecap", "ti,am3352-ecap";
    				#pwm-cells = <0x3>;
    				reg = <0x4843e100 0x80>;
    				clocks = <0xa>;
    				clock-names = "fck";
    				status = "disabled";
    				phandle = <0x1df>;
    			};
    		};
    
    		epwmss@48440000 {
    			compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
    			reg = <0x48440000 0x30>;
    			ti,hwmods = "epwmss1";
    			#address-cells = <0x1>;
    			#size-cells = <0x1>;
    			status = "disabled";
    			ranges;
    			phandle = <0x1e0>;
    
    			pwm@48440200 {
    				compatible = "ti,dra746-ehrpwm", "ti,am3352-ehrpwm";
    				#pwm-cells = <0x3>;
    				reg = <0x48440200 0x80>;
    				clocks = <0xe9 0xa>;
    				clock-names = "tbclk", "fck";
    				status = "disabled";
    				phandle = <0x1e1>;
    			};
    
    			ecap@48440100 {
    				compatible = "ti,dra746-ecap", "ti,am3352-ecap";
    				#pwm-cells = <0x3>;
    				reg = <0x48440100 0x80>;
    				clocks = <0xa>;
    				clock-names = "fck";
    				status = "disabled";
    				phandle = <0x1e2>;
    			};
    		};
    
    		epwmss@48442000 {
    			compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
    			reg = <0x48442000 0x30>;
    			ti,hwmods = "epwmss2";
    			#address-cells = <0x1>;
    			#size-cells = <0x1>;
    			status = "disabled";
    			ranges;
    			phandle = <0x1e3>;
    
    			pwm@48442200 {
    				compatible = "ti,dra746-ehrpwm", "ti,am3352-ehrpwm";
    				#pwm-cells = <0x3>;
    				reg = <0x48442200 0x80>;
    				clocks = <0xea 0xa>;
    				clock-names = "tbclk", "fck";
    				status = "disabled";
    				phandle = <0x1e4>;
    			};
    
    			ecap@48442100 {
    				compatible = "ti,dra746-ecap", "ti,am3352-ecap";
    				#pwm-cells = <0x3>;
    				reg = <0x48442100 0x80>;
    				clocks = <0xa>;
    				clock-names = "fck";
    				status = "disabled";
    				phandle = <0x1e5>;
    			};
    		};
    
    		aes@4b500000 {
    			compatible = "ti,omap4-aes";
    			ti,hwmods = "aes1";
    			reg = <0x4b500000 0xa0>;
    			interrupts = <0x0 0x50 0x4>;
    			dmas = <0xcd 0x6f 0x0 0xcd 0x6e 0x0>;
    			dma-names = "tx", "rx";
    			clocks = <0x9>;
    			clock-names = "fck";
    			phandle = <0x1e6>;
    		};
    
    		aes@4b700000 {
    			compatible = "ti,omap4-aes";
    			ti,hwmods = "aes2";
    			reg = <0x4b700000 0xa0>;
    			interrupts = <0x0 0x3b 0x4>;
    			dmas = <0xcd 0x72 0x0 0xcd 0x71 0x0>;
    			dma-names = "tx", "rx";
    			clocks = <0x9>;
    			clock-names = "fck";
    			phandle = <0x1e7>;
    		};
    
    		des@480a5000 {
    			compatible = "ti,omap4-des";
    			ti,hwmods = "des";
    			reg = <0x480a5000 0xa0>;
    			interrupts = <0x0 0x4d 0x4>;
    			dmas = <0xaf 0x75 0xaf 0x74>;
    			dma-names = "tx", "rx";
    			clocks = <0x9>;
    			clock-names = "fck";
    			phandle = <0x1e8>;
    		};
    
    		sham@53100000 {
    			compatible = "ti,omap5-sham";
    			ti,hwmods = "sham";
    			reg = <0x4b101000 0x300>;
    			interrupts = <0x0 0x2e 0x4>;
    			dmas = <0xcd 0x77 0x0>;
    			dma-names = "rx";
    			clocks = <0x9>;
    			clock-names = "fck";
    			phandle = <0x1e9>;
    		};
    
    		rng@48090000 {
    			compatible = "ti,omap4-rng";
    			ti,hwmods = "rng";
    			reg = <0x48090000 0x2000>;
    			interrupts = <0x0 0x2f 0x4>;
    			clocks = <0x9>;
    			clock-names = "fck";
    			phandle = <0x1ea>;
    		};
    
    		dsp_system@41500000 {
    			compatible = "syscon";
    			reg = <0x41500000 0x100>;
    			phandle = <0xeb>;
    		};
    
    		omap_dwc3_4@48940000 {
    			compatible = "ti,dwc3";
    			ti,hwmods = "usb_otg_ss4";
    			reg = <0x48940000 0x10000>;
    			interrupts = <0x0 0x15a 0x4>;
    			#address-cells = <0x1>;
    			#size-cells = <0x1>;
    			utmi-mode = <0x2>;
    			ranges;
    			status = "disabled";
    			phandle = <0x1eb>;
    
    			usb@48950000 {
    				compatible = "snps,dwc3";
    				reg = <0x48950000 0x17000>;
    				interrupts = <0x0 0x159 0x4 0x0 0x159 0x4 0x0 0x15a 0x4>;
    				interrupt-names = "peripheral", "host", "otg";
    				maximum-speed = "high-speed";
    				dr_mode = "otg";
    				phandle = <0x1ec>;
    			};
    		};
    
    		mmu@41501000 {
    			compatible = "ti,dra7-dsp-iommu";
    			reg = <0x41501000 0x100>;
    			interrupts = <0x0 0x92 0x4>;
    			ti,hwmods = "mmu0_dsp2";
    			#iommu-cells = <0x0>;
    			ti,syscon-mmuconfig = <0xeb 0x0>;
    			status = "disabled";
    			phandle = <0x1ed>;
    		};
    
    		mmu@41502000 {
    			compatible = "ti,dra7-dsp-iommu";
    			reg = <0x41502000 0x100>;
    			interrupts = <0x0 0x93 0x4>;
    			ti,hwmods = "mmu1_dsp2";
    			#iommu-cells = <0x0>;
    			ti,syscon-mmuconfig = <0xeb 0x1>;
    			status = "disabled";
    			phandle = <0x1ee>;
    		};
    	};
    
    	thermal-zones {
    		phandle = <0x1ef>;
    
    		cpu_thermal {
    			polling-delay-passive = <0xfa>;
    			polling-delay = <0x1f4>;
    			thermal-sensors = <0xec 0x0>;
    			coefficients = <0x0 0x7d0>;
    			phandle = <0x1f0>;
    
    			trips {
    				phandle = <0x1f1>;
    
    				cpu_alert {
    					temperature = <0x13880>;
    					hysteresis = <0x7d0>;
    					type = "passive";
    					phandle = <0xed>;
    				};
    
    				cpu_crit {
    					temperature = <0x15f90>;
    					hysteresis = <0x7d0>;
    					type = "critical";
    					phandle = <0x1f2>;
    				};
    
    				cpu_alert1 {
    					temperature = <0xc350>;
    					hysteresis = <0x7d0>;
    					type = "active";
    					phandle = <0x1f3>;
    				};
    			};
    
    			cooling-maps {
    				phandle = <0x1f4>;
    
    				map0 {
    					trip = <0xed>;
    					cooling-device = <0xee 0xffffffff 0xffffffff>;
    				};
    			};
    		};
    
    		gpu_thermal {
    			polling-delay-passive = <0xfa>;
    			polling-delay = <0x1f4>;
    			thermal-sensors = <0xec 0x1>;
    			coefficients = <0x0 0x7d0>;
    			phandle = <0x1f5>;
    
    			trips {
    
    				gpu_crit {
    					temperature = <0x15f90>;
    					hysteresis = <0x7d0>;
    					type = "critical";
    					phandle = <0x1f6>;
    				};
    			};
    		};
    
    		core_thermal {
    			polling-delay-passive = <0xfa>;
    			polling-delay = <0x1f4>;
    			thermal-sensors = <0xec 0x2>;
    			coefficients = <0x0 0x7d0>;
    			phandle = <0x1f7>;
    
    			trips {
    
    				core_crit {
    					temperature = <0x15f90>;
    					hysteresis = <0x7d0>;
    					type = "critical";
    					phandle = <0x1f8>;
    				};
    			};
    		};
    
    		dspeve_thermal {
    			polling-delay-passive = <0xfa>;
    			polling-delay = <0x1f4>;
    			thermal-sensors = <0xec 0x3>;
    			coefficients = <0x0 0x7d0>;
    			phandle = <0x1f9>;
    
    			trips {
    
    				dspeve_crit {
    					temperature = <0x15f90>;
    					hysteresis = <0x7d0>;
    					type = "critical";
    					phandle = <0x1fa>;
    				};
    			};
    		};
    
    		iva_thermal {
    			polling-delay-passive = <0xfa>;
    			polling-delay = <0x1f4>;
    			thermal-sensors = <0xec 0x4>;
    			coefficients = <0x0 0x7d0>;
    			phandle = <0x1fb>;
    
    			trips {
    
    				iva_crit {
    					temperature = <0x15f90>;
    					hysteresis = <0x7d0>;
    					type = "critical";
    					phandle = <0x1fc>;
    				};
    			};
    		};
    	};
    
    	pmu {
    		compatible = "arm,cortex-a15-pmu";
    		interrupt-parent = <0x7>;
    		interrupts = <0x0 0x83 0x4 0x0 0x84 0x4>;
    	};
    
    	memory@0 {
    		device_type = "memory";
    		reg = <0x0 0x80000000 0x0 0x80000000>;
    	};
    
    	fixedregulator-vdd_3v3 {
    		compatible = "regulator-fixed";
    		regulator-name = "vdd_3v3";
    		vin-supply = <0xef>;
    		regulator-min-microvolt = <0x325aa0>;
    		regulator-max-microvolt = <0x325aa0>;
    		phandle = <0xb3>;
    	};
    
    	fixedregulator-aic_dvdd {
    		compatible = "regulator-fixed";
    		regulator-name = "aic_dvdd_fixed";
    		vin-supply = <0xb3>;
    		regulator-min-microvolt = <0x1b7740>;
    		regulator-max-microvolt = <0x1b7740>;
    		phandle = <0x1fd>;
    	};
    
    	fixedregulator-vtt {
    		compatible = "regulator-fixed";
    		regulator-name = "vtt_fixed";
    		vin-supply = <0xf0>;
    		regulator-min-microvolt = <0x325aa0>;
    		regulator-max-microvolt = <0x325aa0>;
    		regulator-always-on;
    		regulator-boot-on;
    		enable-active-high;
    		phandle = <0x1fe>;
    	};
    
    	__symbols__ {
    		gic = "/interrupt-controller@48211000";
    		wakeupgen = "/interrupt-controller@48281000";
    		cpu0 = "/cpus/cpu@0";
    		cpu0_opp_table = "/opp-table";
    		l4_cfg = "/ocp/l4@4a000000";
    		scm = "/ocp/l4@4a000000/scm@2000";
    		scm_conf = "/ocp/l4@4a000000/scm@2000/scm_conf@0";
    		pbias_regulator = "/ocp/l4@4a000000/scm@2000/scm_conf@0/pbias_regulator@e00";
    		pbias_mmc_reg = "/ocp/l4@4a000000/scm@2000/scm_conf@0/pbias_regulator@e00/pbias_mmc_omap5";
    		scm_conf_clocks = "/ocp/l4@4a000000/scm@2000/scm_conf@0/clocks";
    		dss_deshdcp_clk = "/ocp/l4@4a000000/scm@2000/scm_conf@0/clocks/dss_deshdcp_clk@558";
    		ehrpwm0_tbclk = "/ocp/l4@4a000000/scm@2000/scm_conf@0/clocks/ehrpwm0_tbclk@558";
    		ehrpwm1_tbclk = "/ocp/l4@4a000000/scm@2000/scm_conf@0/clocks/ehrpwm1_tbclk@558";
    		ehrpwm2_tbclk = "/ocp/l4@4a000000/scm@2000/scm_conf@0/clocks/ehrpwm2_tbclk@558";
    		sys_32k_ck = "/ocp/l4@4a000000/scm@2000/scm_conf@0/clocks/sys_32k_ck";
    		dra7_pmx_core = "/ocp/l4@4a000000/scm@2000/pinmux@1400";
    		mmc1_pins_default = "/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc1_pins_default";
    		mmc1_pins_sdr12 = "/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc1_pins_sdr12";
    		mmc1_pins_hs = "/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc1_pins_hs";
    		mmc1_pins_sdr25 = "/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc1_pins_sdr25";
    		mmc1_pins_sdr50 = "/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc1_pins_sdr50";
    		mmc1_pins_ddr50 = "/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc1_pins_ddr50";
    		mmc1_pins_sdr104 = "/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc1_pins_sdr104";
    		mmc2_pins_default = "/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc2_pins_default";
    		mmc2_pins_hs = "/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc2_pins_hs";
    		mmc2_pins_ddr_3_3v_rev11 = "/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc2_pins_ddr_3_3v_rev11";
    		mmc2_pins_ddr_1_8v_rev11 = "/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc2_pins_ddr_1_8v_rev11";
    		mmc2_pins_ddr_rev20 = "/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc2_pins_ddr_rev20";
    		mmc2_pins_hs200 = "/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc2_pins_hs200";
    		mmc4_pins_default = "/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc4_pins_default";
    		mmc4_pins_hs = "/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc4_pins_hs";
    		mmc3_pins_default = "/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc3_pins_default";
    		mmc3_pins_hs = "/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc3_pins_hs";
    		mmc3_pins_sdr12 = "/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc3_pins_sdr12";
    		mmc3_pins_sdr25 = "/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc3_pins_sdr25";
    		mmc3_pins_sdr50 = "/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc3_pins_sdr50";
    		mmc4_pins_sdr12 = "/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc4_pins_sdr12";
    		mmc4_pins_sdr25 = "/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc4_pins_sdr25";
    		scm_conf1 = "/ocp/l4@4a000000/scm@2000/scm_conf@1c04";
    		scm_conf_pcie = "/ocp/l4@4a000000/scm@2000/scm_conf@1c24";
    		sdma_xbar = "/ocp/l4@4a000000/scm@2000/dma-router@b78";
    		edma_xbar = "/ocp/l4@4a000000/scm@2000/dma-router@c78";
    		cm_core_aon = "/ocp/l4@4a000000/cm_core_aon@5000";
    		cm_core_aon_clocks = "/ocp/l4@4a000000/cm_core_aon@5000/clocks";
    		atl_clkin0_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/atl_clkin0_ck";
    		atl_clkin1_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/atl_clkin1_ck";
    		atl_clkin2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/atl_clkin2_ck";
    		atl_clkin3_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/atl_clkin3_ck";
    		hdmi_clkin_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/hdmi_clkin_ck";
    		mlb_clkin_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/mlb_clkin_ck";
    		mlbp_clkin_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/mlbp_clkin_ck";
    		pciesref_acs_clk_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/pciesref_acs_clk_ck";
    		ref_clkin0_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/ref_clkin0_ck";
    		ref_clkin1_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/ref_clkin1_ck";
    		ref_clkin2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/ref_clkin2_ck";
    		ref_clkin3_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/ref_clkin3_ck";
    		rmii_clk_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/rmii_clk_ck";
    		sdvenc_clkin_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/sdvenc_clkin_ck";
    		secure_32k_clk_src_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/secure_32k_clk_src_ck";
    		sys_clk32_crystal_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/sys_clk32_crystal_ck";
    		sys_clk32_pseudo_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/sys_clk32_pseudo_ck";
    		virt_12000000_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/virt_12000000_ck";
    		virt_13000000_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/virt_13000000_ck";
    		virt_16800000_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/virt_16800000_ck";
    		virt_19200000_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/virt_19200000_ck";
    		virt_20000000_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/virt_20000000_ck";
    		virt_26000000_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/virt_26000000_ck";
    		virt_27000000_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/virt_27000000_ck";
    		virt_38400000_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/virt_38400000_ck";
    		sys_clkin2 = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/sys_clkin2";
    		usb_otg_clkin_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/usb_otg_clkin_ck";
    		video1_clkin_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/video1_clkin_ck";
    		video1_m2_clkin_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/video1_m2_clkin_ck";
    		video2_clkin_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/video2_clkin_ck";
    		video2_m2_clkin_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/video2_m2_clkin_ck";
    		dpll_abe_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_abe_ck@1e0";
    		dpll_abe_x2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_abe_x2_ck";
    		dpll_abe_m2x2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_abe_m2x2_ck@1f0";
    		abe_clk = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/abe_clk@108";
    		dpll_abe_m2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_abe_m2_ck@1f0";
    		dpll_abe_m3x2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_abe_m3x2_ck@1f4";
    		dpll_core_byp_mux = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_core_byp_mux@12c";
    		dpll_core_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_core_ck@120";
    		dpll_core_x2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_core_x2_ck";
    		dpll_core_h12x2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_core_h12x2_ck@13c";
    		mpu_dpll_hs_clk_div = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/mpu_dpll_hs_clk_div";
    		dpll_mpu_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_mpu_ck@160";
    		dpll_mpu_m2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_mpu_m2_ck@170";
    		mpu_dclk_div = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/mpu_dclk_div";
    		dsp_dpll_hs_clk_div = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dsp_dpll_hs_clk_div";
    		dpll_dsp_byp_mux = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_dsp_byp_mux@240";
    		dpll_dsp_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_dsp_ck@234";
    		dpll_dsp_m2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_dsp_m2_ck@244";
    		iva_dpll_hs_clk_div = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/iva_dpll_hs_clk_div";
    		dpll_iva_byp_mux = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_iva_byp_mux@1ac";
    		dpll_iva_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_iva_ck@1a0";
    		dpll_iva_m2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_iva_m2_ck@1b0";
    		iva_dclk = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/iva_dclk";
    		dpll_gpu_byp_mux = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_gpu_byp_mux@2e4";
    		dpll_gpu_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_gpu_ck@2d8";
    		dpll_gpu_m2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_gpu_m2_ck@2e8";
    		dpll_core_m2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_core_m2_ck@130";
    		core_dpll_out_dclk_div = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/core_dpll_out_dclk_div";
    		dpll_ddr_byp_mux = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_ddr_byp_mux@21c";
    		dpll_ddr_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_ddr_ck@210";
    		dpll_ddr_m2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_ddr_m2_ck@220";
    		dpll_gmac_byp_mux = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_gmac_byp_mux@2b4";
    		dpll_gmac_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_gmac_ck@2a8";
    		dpll_gmac_m2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_gmac_m2_ck@2b8";
    		video2_dclk_div = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/video2_dclk_div";
    		video1_dclk_div = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/video1_dclk_div";
    		hdmi_dclk_div = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/hdmi_dclk_div";
    		per_dpll_hs_clk_div = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/per_dpll_hs_clk_div";
    		usb_dpll_hs_clk_div = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/usb_dpll_hs_clk_div";
    		eve_dpll_hs_clk_div = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/eve_dpll_hs_clk_div";
    		dpll_eve_byp_mux = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_eve_byp_mux@290";
    		dpll_eve_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_eve_ck@284";
    		dpll_eve_m2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_eve_m2_ck@294";
    		eve_dclk_div = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/eve_dclk_div";
    		dpll_core_h13x2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_core_h13x2_ck@140";
    		dpll_core_h14x2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_core_h14x2_ck@144";
    		dpll_core_h22x2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_core_h22x2_ck@154";
    		dpll_core_h23x2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_core_h23x2_ck@158";
    		dpll_core_h24x2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_core_h24x2_ck@15c";
    		dpll_ddr_x2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_ddr_x2_ck";
    		dpll_ddr_h11x2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_ddr_h11x2_ck@228";
    		dpll_dsp_x2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_dsp_x2_ck";
    		dpll_dsp_m3x2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_dsp_m3x2_ck@248";
    		dpll_gmac_x2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_gmac_x2_ck";
    		dpll_gmac_h11x2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_gmac_h11x2_ck@2c0";
    		dpll_gmac_h12x2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_gmac_h12x2_ck@2c4";
    		dpll_gmac_h13x2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_gmac_h13x2_ck@2c8";
    		dpll_gmac_m3x2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_gmac_m3x2_ck@2bc";
    		gmii_m_clk_div = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/gmii_m_clk_div";
    		hdmi_clk2_div = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/hdmi_clk2_div";
    		hdmi_div_clk = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/hdmi_div_clk";
    		l3_iclk_div = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/l3_iclk_div@100";
    		l4_root_clk_div = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/l4_root_clk_div";
    		video1_clk2_div = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/video1_clk2_div";
    		video1_div_clk = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/video1_div_clk";
    		video2_clk2_div = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/video2_clk2_div";
    		video2_div_clk = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/video2_div_clk";
    		ipu1_gfclk_mux = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/ipu1_gfclk_mux@520";
    		mcasp1_ahclkr_mux = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/mcasp1_ahclkr_mux@550";
    		mcasp1_ahclkx_mux = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/mcasp1_ahclkx_mux@550";
    		mcasp1_aux_gfclk_mux = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/mcasp1_aux_gfclk_mux@550";
    		timer5_gfclk_mux = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/timer5_gfclk_mux@558";
    		timer6_gfclk_mux = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/timer6_gfclk_mux@560";
    		timer7_gfclk_mux = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/timer7_gfclk_mux@568";
    		timer8_gfclk_mux = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/timer8_gfclk_mux@570";
    		uart6_gfclk_mux = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/uart6_gfclk_mux@580";
    		dummy_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dummy_ck";
    		cm_core_aon_clockdomains = "/ocp/l4@4a000000/cm_core_aon@5000/clockdomains";
    		cm_core = "/ocp/l4@4a000000/cm_core@8000";
    		cm_core_clocks = "/ocp/l4@4a000000/cm_core@8000/clocks";
    		dpll_pcie_ref_ck = "/ocp/l4@4a000000/cm_core@8000/clocks/dpll_pcie_ref_ck@200";
    		dpll_pcie_ref_m2ldo_ck = "/ocp/l4@4a000000/cm_core@8000/clocks/dpll_pcie_ref_m2ldo_ck@210";
    		apll_pcie_in_clk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/apll_pcie_in_clk_mux@4ae06118";
    		apll_pcie_ck = "/ocp/l4@4a000000/cm_core@8000/clocks/apll_pcie_ck@21c";
    		optfclk_pciephy1_32khz = "/ocp/l4@4a000000/cm_core@8000/clocks/optfclk_pciephy1_32khz@4a0093b0";
    		optfclk_pciephy2_32khz = "/ocp/l4@4a000000/cm_core@8000/clocks/optfclk_pciephy2_32khz@4a0093b8";
    		optfclk_pciephy_div = "/ocp/l4@4a000000/cm_core@8000/clocks/optfclk_pciephy_div@4a00821c";
    		optfclk_pciephy1_clk = "/ocp/l4@4a000000/cm_core@8000/clocks/optfclk_pciephy1_clk@4a0093b0";
    		optfclk_pciephy2_clk = "/ocp/l4@4a000000/cm_core@8000/clocks/optfclk_pciephy2_clk@4a0093b8";
    		optfclk_pciephy1_div_clk = "/ocp/l4@4a000000/cm_core@8000/clocks/optfclk_pciephy1_div_clk@4a0093b0";
    		optfclk_pciephy2_div_clk = "/ocp/l4@4a000000/cm_core@8000/clocks/optfclk_pciephy2_div_clk@4a0093b8";
    		apll_pcie_clkvcoldo = "/ocp/l4@4a000000/cm_core@8000/clocks/apll_pcie_clkvcoldo";
    		apll_pcie_clkvcoldo_div = "/ocp/l4@4a000000/cm_core@8000/clocks/apll_pcie_clkvcoldo_div";
    		apll_pcie_m2_ck = "/ocp/l4@4a000000/cm_core@8000/clocks/apll_pcie_m2_ck";
    		dpll_per_byp_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/dpll_per_byp_mux@14c";
    		dpll_per_ck = "/ocp/l4@4a000000/cm_core@8000/clocks/dpll_per_ck@140";
    		dpll_per_m2_ck = "/ocp/l4@4a000000/cm_core@8000/clocks/dpll_per_m2_ck@150";
    		func_96m_aon_dclk_div = "/ocp/l4@4a000000/cm_core@8000/clocks/func_96m_aon_dclk_div";
    		dpll_usb_byp_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/dpll_usb_byp_mux@18c";
    		dpll_usb_ck = "/ocp/l4@4a000000/cm_core@8000/clocks/dpll_usb_ck@180";
    		dpll_usb_m2_ck = "/ocp/l4@4a000000/cm_core@8000/clocks/dpll_usb_m2_ck@190";
    		dpll_pcie_ref_m2_ck = "/ocp/l4@4a000000/cm_core@8000/clocks/dpll_pcie_ref_m2_ck@210";
    		dpll_per_x2_ck = "/ocp/l4@4a000000/cm_core@8000/clocks/dpll_per_x2_ck";
    		dpll_per_h11x2_ck = "/ocp/l4@4a000000/cm_core@8000/clocks/dpll_per_h11x2_ck@158";
    		dpll_per_h12x2_ck = "/ocp/l4@4a000000/cm_core@8000/clocks/dpll_per_h12x2_ck@15c";
    		dpll_per_h13x2_ck = "/ocp/l4@4a000000/cm_core@8000/clocks/dpll_per_h13x2_ck@160";
    		dpll_per_h14x2_ck = "/ocp/l4@4a000000/cm_core@8000/clocks/dpll_per_h14x2_ck@164";
    		dpll_per_m2x2_ck = "/ocp/l4@4a000000/cm_core@8000/clocks/dpll_per_m2x2_ck@150";
    		dpll_usb_clkdcoldo = "/ocp/l4@4a000000/cm_core@8000/clocks/dpll_usb_clkdcoldo";
    		func_128m_clk = "/ocp/l4@4a000000/cm_core@8000/clocks/func_128m_clk";
    		func_12m_fclk = "/ocp/l4@4a000000/cm_core@8000/clocks/func_12m_fclk";
    		func_24m_clk = "/ocp/l4@4a000000/cm_core@8000/clocks/func_24m_clk";
    		func_48m_fclk = "/ocp/l4@4a000000/cm_core@8000/clocks/func_48m_fclk";
    		func_96m_fclk = "/ocp/l4@4a000000/cm_core@8000/clocks/func_96m_fclk";
    		l3init_60m_fclk = "/ocp/l4@4a000000/cm_core@8000/clocks/l3init_60m_fclk@104";
    		clkout2_clk = "/ocp/l4@4a000000/cm_core@8000/clocks/clkout2_clk@6b0";
    		l3init_960m_gfclk = "/ocp/l4@4a000000/cm_core@8000/clocks/l3init_960m_gfclk@6c0";
    		dss_32khz_clk = "/ocp/l4@4a000000/cm_core@8000/clocks/dss_32khz_clk@1120";
    		dss_48mhz_clk = "/ocp/l4@4a000000/cm_core@8000/clocks/dss_48mhz_clk@1120";
    		dss_dss_clk = "/ocp/l4@4a000000/cm_core@8000/clocks/dss_dss_clk@1120";
    		dss_hdmi_clk = "/ocp/l4@4a000000/cm_core@8000/clocks/dss_hdmi_clk@1120";
    		dss_video1_clk = "/ocp/l4@4a000000/cm_core@8000/clocks/dss_video1_clk@1120";
    		dss_video2_clk = "/ocp/l4@4a000000/cm_core@8000/clocks/dss_video2_clk@1120";
    		gpio2_dbclk = "/ocp/l4@4a000000/cm_core@8000/clocks/gpio2_dbclk@1760";
    		gpio3_dbclk = "/ocp/l4@4a000000/cm_core@8000/clocks/gpio3_dbclk@1768";
    		gpio4_dbclk = "/ocp/l4@4a000000/cm_core@8000/clocks/gpio4_dbclk@1770";
    		gpio5_dbclk = "/ocp/l4@4a000000/cm_core@8000/clocks/gpio5_dbclk@1778";
    		gpio6_dbclk = "/ocp/l4@4a000000/cm_core@8000/clocks/gpio6_dbclk@1780";
    		gpio7_dbclk = "/ocp/l4@4a000000/cm_core@8000/clocks/gpio7_dbclk@1810";
    		gpio8_dbclk = "/ocp/l4@4a000000/cm_core@8000/clocks/gpio8_dbclk@1818";
    		mmc1_clk32k = "/ocp/l4@4a000000/cm_core@8000/clocks/mmc1_clk32k@1328";
    		mmc2_clk32k = "/ocp/l4@4a000000/cm_core@8000/clocks/mmc2_clk32k@1330";
    		mmc3_clk32k = "/ocp/l4@4a000000/cm_core@8000/clocks/mmc3_clk32k@1820";
    		mmc4_clk32k = "/ocp/l4@4a000000/cm_core@8000/clocks/mmc4_clk32k@1828";
    		sata_ref_clk = "/ocp/l4@4a000000/cm_core@8000/clocks/sata_ref_clk@1388";
    		usb_otg_ss1_refclk960m = "/ocp/l4@4a000000/cm_core@8000/clocks/usb_otg_ss1_refclk960m@13f0";
    		usb_otg_ss2_refclk960m = "/ocp/l4@4a000000/cm_core@8000/clocks/usb_otg_ss2_refclk960m@1340";
    		usb_phy1_always_on_clk32k = "/ocp/l4@4a000000/cm_core@8000/clocks/usb_phy1_always_on_clk32k@640";
    		usb_phy2_always_on_clk32k = "/ocp/l4@4a000000/cm_core@8000/clocks/usb_phy2_always_on_clk32k@688";
    		usb_phy3_always_on_clk32k = "/ocp/l4@4a000000/cm_core@8000/clocks/usb_phy3_always_on_clk32k@698";
    		atl_dpll_clk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/atl_dpll_clk_mux@c00";
    		atl_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/atl_gfclk_mux@c00";
    		rmii_50mhz_clk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/rmii_50mhz_clk_mux@13d0";
    		gmac_rft_clk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/gmac_rft_clk_mux@13d0";
    		gpu_core_gclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/gpu_core_gclk_mux@1220";
    		gpu_hyd_gclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/gpu_hyd_gclk_mux@1220";
    		l3instr_ts_gclk_div = "/ocp/l4@4a000000/cm_core@8000/clocks/l3instr_ts_gclk_div@e50";
    		mcasp2_ahclkr_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/mcasp2_ahclkr_mux@1860";
    		mcasp2_ahclkx_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/mcasp2_ahclkx_mux@1860";
    		mcasp2_aux_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/mcasp2_aux_gfclk_mux@1860";
    		mcasp3_ahclkx_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/mcasp3_ahclkx_mux@1868";
    		mcasp3_aux_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/mcasp3_aux_gfclk_mux@1868";
    		mcasp4_ahclkx_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/mcasp4_ahclkx_mux@1898";
    		mcasp4_aux_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/mcasp4_aux_gfclk_mux@1898";
    		mcasp5_ahclkx_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/mcasp5_ahclkx_mux@1878";
    		mcasp5_aux_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/mcasp5_aux_gfclk_mux@1878";
    		mcasp6_ahclkx_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/mcasp6_ahclkx_mux@1904";
    		mcasp6_aux_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/mcasp6_aux_gfclk_mux@1904";
    		mcasp7_ahclkx_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/mcasp7_ahclkx_mux@1908";
    		mcasp7_aux_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/mcasp7_aux_gfclk_mux@1908";
    		mcasp8_ahclkx_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/mcasp8_ahclkx_mux@1890";
    		mcasp8_aux_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/mcasp8_aux_gfclk_mux@1890";
    		mmc1_fclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/mmc1_fclk_mux@1328";
    		mmc1_fclk_div = "/ocp/l4@4a000000/cm_core@8000/clocks/mmc1_fclk_div@1328";
    		mmc2_fclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/mmc2_fclk_mux@1330";
    		mmc2_fclk_div = "/ocp/l4@4a000000/cm_core@8000/clocks/mmc2_fclk_div@1330";
    		mmc3_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/mmc3_gfclk_mux@1820";
    		mmc3_gfclk_div = "/ocp/l4@4a000000/cm_core@8000/clocks/mmc3_gfclk_div@1820";
    		mmc4_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/mmc4_gfclk_mux@1828";
    		mmc4_gfclk_div = "/ocp/l4@4a000000/cm_core@8000/clocks/mmc4_gfclk_div@1828";
    		qspi_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/qspi_gfclk_mux@1838";
    		qspi_gfclk_div = "/ocp/l4@4a000000/cm_core@8000/clocks/qspi_gfclk_div@1838";
    		timer10_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/timer10_gfclk_mux@1728";
    		timer11_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/timer11_gfclk_mux@1730";
    		timer13_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/timer13_gfclk_mux@17c8";
    		timer14_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/timer14_gfclk_mux@17d0";
    		timer15_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/timer15_gfclk_mux@17d8";
    		timer16_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/timer16_gfclk_mux@1830";
    		timer2_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/timer2_gfclk_mux@1738";
    		timer3_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/timer3_gfclk_mux@1740";
    		timer4_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/timer4_gfclk_mux@1748";
    		timer9_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/timer9_gfclk_mux@1750";
    		uart1_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/uart1_gfclk_mux@1840";
    		uart2_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/uart2_gfclk_mux@1848";
    		uart3_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/uart3_gfclk_mux@1850";
    		uart4_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/uart4_gfclk_mux@1858";
    		uart5_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/uart5_gfclk_mux@1870";
    		uart7_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/uart7_gfclk_mux@18d0";
    		uart8_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/uart8_gfclk_mux@18e0";
    		uart9_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/uart9_gfclk_mux@18e8";
    		vip1_gclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/vip1_gclk_mux@1020";
    		vip2_gclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/vip2_gclk_mux@1028";
    		vip3_gclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/vip3_gclk_mux@1030";
    		cm_core_clockdomains = "/ocp/l4@4a000000/cm_core@8000/clockdomains";
    		coreaon_clkdm = "/ocp/l4@4a000000/cm_core@8000/clockdomains/coreaon_clkdm";
    		l4_wkup = "/ocp/l4@4ae00000";
    		counter32k = "/ocp/l4@4ae00000/counter@4000";
    		prm = "/ocp/l4@4ae00000/prm@6000";
    		prm_clocks = "/ocp/l4@4ae00000/prm@6000/clocks";
    		sys_clkin1 = "/ocp/l4@4ae00000/prm@6000/clocks/sys_clkin1@110";
    		abe_dpll_sys_clk_mux = "/ocp/l4@4ae00000/prm@6000/clocks/abe_dpll_sys_clk_mux@118";
    		abe_dpll_bypass_clk_mux = "/ocp/l4@4ae00000/prm@6000/clocks/abe_dpll_bypass_clk_mux@114";
    		abe_dpll_clk_mux = "/ocp/l4@4ae00000/prm@6000/clocks/abe_dpll_clk_mux@10c";
    		abe_24m_fclk = "/ocp/l4@4ae00000/prm@6000/clocks/abe_24m_fclk@11c";
    		aess_fclk = "/ocp/l4@4ae00000/prm@6000/clocks/aess_fclk@178";
    		abe_giclk_div = "/ocp/l4@4ae00000/prm@6000/clocks/abe_giclk_div@174";
    		abe_lp_clk_div = "/ocp/l4@4ae00000/prm@6000/clocks/abe_lp_clk_div@1d8";
    		abe_sys_clk_div = "/ocp/l4@4ae00000/prm@6000/clocks/abe_sys_clk_div@120";
    		adc_gfclk_mux = "/ocp/l4@4ae00000/prm@6000/clocks/adc_gfclk_mux@1dc";
    		sys_clk1_dclk_div = "/ocp/l4@4ae00000/prm@6000/clocks/sys_clk1_dclk_div@1c8";
    		sys_clk2_dclk_div = "/ocp/l4@4ae00000/prm@6000/clocks/sys_clk2_dclk_div@1cc";
    		per_abe_x1_dclk_div = "/ocp/l4@4ae00000/prm@6000/clocks/per_abe_x1_dclk_div@1bc";
    		dsp_gclk_div = "/ocp/l4@4ae00000/prm@6000/clocks/dsp_gclk_div@18c";
    		gpu_dclk = "/ocp/l4@4ae00000/prm@6000/clocks/gpu_dclk@1a0";
    		emif_phy_dclk_div = "/ocp/l4@4ae00000/prm@6000/clocks/emif_phy_dclk_div@190";
    		gmac_250m_dclk_div = "/ocp/l4@4ae00000/prm@6000/clocks/gmac_250m_dclk_div@19c";
    		gmac_main_clk = "/ocp/l4@4ae00000/prm@6000/clocks/gmac_main_clk";
    		l3init_480m_dclk_div = "/ocp/l4@4ae00000/prm@6000/clocks/l3init_480m_dclk_div@1ac";
    		usb_otg_dclk_div = "/ocp/l4@4ae00000/prm@6000/clocks/usb_otg_dclk_div@184";
    		sata_dclk_div = "/ocp/l4@4ae00000/prm@6000/clocks/sata_dclk_div@1c0";
    		pcie2_dclk_div = "/ocp/l4@4ae00000/prm@6000/clocks/pcie2_dclk_div@1b8";
    		pcie_dclk_div = "/ocp/l4@4ae00000/prm@6000/clocks/pcie_dclk_div@1b4";
    		emu_dclk_div = "/ocp/l4@4ae00000/prm@6000/clocks/emu_dclk_div@194";
    		secure_32k_dclk_div = "/ocp/l4@4ae00000/prm@6000/clocks/secure_32k_dclk_div@1c4";
    		clkoutmux0_clk_mux = "/ocp/l4@4ae00000/prm@6000/clocks/clkoutmux0_clk_mux@158";
    		clkoutmux1_clk_mux = "/ocp/l4@4ae00000/prm@6000/clocks/clkoutmux1_clk_mux@15c";
    		clkoutmux2_clk_mux = "/ocp/l4@4ae00000/prm@6000/clocks/clkoutmux2_clk_mux@160";
    		custefuse_sys_gfclk_div = "/ocp/l4@4ae00000/prm@6000/clocks/custefuse_sys_gfclk_div";
    		eve_clk = "/ocp/l4@4ae00000/prm@6000/clocks/eve_clk@180";
    		hdmi_dpll_clk_mux = "/ocp/l4@4ae00000/prm@6000/clocks/hdmi_dpll_clk_mux@164";
    		mlb_clk = "/ocp/l4@4ae00000/prm@6000/clocks/mlb_clk@134";
    		mlbp_clk = "/ocp/l4@4ae00000/prm@6000/clocks/mlbp_clk@130";
    		per_abe_x1_gfclk2_div = "/ocp/l4@4ae00000/prm@6000/clocks/per_abe_x1_gfclk2_div@138";
    		timer_sys_clk_div = "/ocp/l4@4ae00000/prm@6000/clocks/timer_sys_clk_div@144";
    		video1_dpll_clk_mux = "/ocp/l4@4ae00000/prm@6000/clocks/video1_dpll_clk_mux@168";
    		video2_dpll_clk_mux = "/ocp/l4@4ae00000/prm@6000/clocks/video2_dpll_clk_mux@16c";
    		wkupaon_iclk_mux = "/ocp/l4@4ae00000/prm@6000/clocks/wkupaon_iclk_mux@108";
    		gpio1_dbclk = "/ocp/l4@4ae00000/prm@6000/clocks/gpio1_dbclk@1838";
    		dcan1_sys_clk_mux = "/ocp/l4@4ae00000/prm@6000/clocks/dcan1_sys_clk_mux@1888";
    		timer1_gfclk_mux = "/ocp/l4@4ae00000/prm@6000/clocks/timer1_gfclk_mux@1840";
    		uart10_gfclk_mux = "/ocp/l4@4ae00000/prm@6000/clocks/uart10_gfclk_mux@1880";
    		prm_clockdomains = "/ocp/l4@4ae00000/prm@6000/clockdomains";
    		scm_wkup = "/ocp/l4@4ae00000/scm_conf@c000";
    		pcie1_rc = "/ocp/axi@0/pcie@51000000";
    		pcie1_intc = "/ocp/axi@0/pcie@51000000/interrupt-controller";
    		pcie1_ep = "/ocp/axi@0/pcie_ep@51000000";
    		pcie2_intc = "/ocp/axi@1/pcie@51800000/interrupt-controller";
    		ocmcram1 = "/ocp/ocmcram@40300000";
    		ocmcram2 = "/ocp/ocmcram@40400000";
    		ocmcram3 = "/ocp/ocmcram@40500000";
    		bandgap = "/ocp/bandgap@4a0021e0";
    		dsp1_system = "/ocp/dsp_system@40d00000";
    		dra7_iodelay_core = "/ocp/padconf@4844a000";
    		mmc1_iodelay_ddr_rev11_conf = "/ocp/padconf@4844a000/mmc1_iodelay_ddr_rev11_conf";
    		mmc1_iodelay_ddr_rev20_conf = "/ocp/padconf@4844a000/mmc1_iodelay_ddr50_rev20_conf";
    		mmc1_iodelay_sdr104_rev11_conf = "/ocp/padconf@4844a000/mmc1_iodelay_sdr104_rev11_conf";
    		mmc1_iodelay_sdr104_rev20_conf = "/ocp/padconf@4844a000/mmc1_iodelay_sdr104_rev20_conf";
    		mmc2_iodelay_hs200_rev11_conf = "/ocp/padconf@4844a000/mmc2_iodelay_hs200_rev11_conf";
    		mmc2_iodelay_hs200_rev20_conf = "/ocp/padconf@4844a000/mmc2_iodelay_hs200_rev20_conf";
    		mmc2_iodelay_ddr_3_3v_rev11_conf = "/ocp/padconf@4844a000/mmc2_iodelay_ddr_3_3v_rev11_conf";
    		mmc2_iodelay_ddr_1_8v_rev11_conf = "/ocp/padconf@4844a000/mmc2_iodelay_ddr_1_8v_rev11_conf";
    		mmc3_iodelay_manual1_rev11_conf = "/ocp/padconf@4844a000/mmc3_iodelay_manual1_conf";
    		mmc3_iodelay_manual1_rev20_conf = "/ocp/padconf@4844a000/mmc3_iodelay_manual1_conf";
    		mmc4_iodelay_ds_rev11_conf = "/ocp/padconf@4844a000/mmc4_iodelay_ds_rev11_conf";
    		mmc4_iodelay_ds_rev20_conf = "/ocp/padconf@4844a000/mmc4_iodelay_ds_rev20_conf";
    		mmc4_iodelay_sdr12_hs_sdr25_rev11_conf = "/ocp/padconf@4844a000/mmc4_iodelay_sdr12_hs_sdr25_rev11_conf";
    		mmc4_iodelay_sdr12_hs_sdr25_rev20_conf = "/ocp/padconf@4844a000/mmc4_iodelay_sdr12_hs_sdr25_rev20_conf";
    		sdma = "/ocp/dma-controller@4a056000";
    		edma = "/ocp/edma@43300000";
    		edma_tptc0 = "/ocp/tptc@43400000";
    		edma_tptc1 = "/ocp/tptc@43500000";
    		gpio1 = "/ocp/gpio@4ae10000";
    		gpio2 = "/ocp/gpio@48055000";
    		gpio3 = "/ocp/gpio@48057000";
    		gpio4 = "/ocp/gpio@48059000";
    		gpio5 = "/ocp/gpio@4805b000";
    		gpio6 = "/ocp/gpio@4805d000";
    		gpio7 = "/ocp/gpio@48051000";
    		gpio8 = "/ocp/gpio@48053000";
    		uart1 = "/ocp/serial@4806a000";
    		uart2 = "/ocp/serial@4806c000";
    		uart3 = "/ocp/serial@48020000";
    		uart4 = "/ocp/serial@4806e000";
    		uart5 = "/ocp/serial@48066000";
    		uart6 = "/ocp/serial@48068000";
    		uart7 = "/ocp/serial@48420000";
    		uart8 = "/ocp/serial@48422000";
    		uart9 = "/ocp/serial@48424000";
    		uart10 = "/ocp/serial@4ae2b000";
    		mailbox1 = "/ocp/mailbox@4a0f4000";
    		mailbox2 = "/ocp/mailbox@4883a000";
    		mailbox3 = "/ocp/mailbox@4883c000";
    		mailbox4 = "/ocp/mailbox@4883e000";
    		mailbox5 = "/ocp/mailbox@48840000";
    		mbox_ipu1_ipc3x = "/ocp/mailbox@48840000/mbox_ipu1_ipc3x";
    		mbox_dsp1_ipc3x = "/ocp/mailbox@48840000/mbox_dsp1_ipc3x";
    		mailbox6 = "/ocp/mailbox@48842000";
    		mbox_ipu2_ipc3x = "/ocp/mailbox@48842000/mbox_ipu2_ipc3x";
    		mbox_dsp2_ipc3x = "/ocp/mailbox@48842000/mbox_dsp2_ipc3x";
    		mailbox7 = "/ocp/mailbox@48844000";
    		mailbox8 = "/ocp/mailbox@48846000";
    		mailbox9 = "/ocp/mailbox@4885e000";
    		mailbox10 = "/ocp/mailbox@48860000";
    		mailbox11 = "/ocp/mailbox@48862000";
    		mailbox12 = "/ocp/mailbox@48864000";
    		mailbox13 = "/ocp/mailbox@48802000";
    		timer1 = "/ocp/timer@4ae18000";
    		timer2 = "/ocp/timer@48032000";
    		timer3 = "/ocp/timer@48034000";
    		timer4 = "/ocp/timer@48036000";
    		timer5 = "/ocp/timer@48820000";
    		timer6 = "/ocp/timer@48822000";
    		timer7 = "/ocp/timer@48824000";
    		timer8 = "/ocp/timer@48826000";
    		timer9 = "/ocp/timer@4803e000";
    		timer10 = "/ocp/timer@48086000";
    		timer11 = "/ocp/timer@48088000";
    		timer12 = "/ocp/timer@4ae20000";
    		timer13 = "/ocp/timer@48828000";
    		timer14 = "/ocp/timer@4882a000";
    		timer15 = "/ocp/timer@4882c000";
    		timer16 = "/ocp/timer@4882e000";
    		wdt2 = "/ocp/wdt@4ae14000";
    		hwspinlock = "/ocp/spinlock@4a0f6000";
    		i2c1 = "/ocp/i2c@48070000";
    		tps659038 = "/ocp/i2c@48070000/tps659038@58";
    		smps12_reg = "/ocp/i2c@48070000/tps659038@58/tps659038_pmic/regulators/smps12";
    		smps3_reg = "/ocp/i2c@48070000/tps659038@58/tps659038_pmic/regulators/smps3";
    		smps45_reg = "/ocp/i2c@48070000/tps659038@58/tps659038_pmic/regulators/smps45";
    		smps6_reg = "/ocp/i2c@48070000/tps659038@58/tps659038_pmic/regulators/smps6";
    		smps8_reg = "/ocp/i2c@48070000/tps659038@58/tps659038_pmic/regulators/smps8";
    		ldo1_reg = "/ocp/i2c@48070000/tps659038@58/tps659038_pmic/regulators/ldo1";
    		ldo2_reg = "/ocp/i2c@48070000/tps659038@58/tps659038_pmic/regulators/ldo2";
    		ldo3_reg = "/ocp/i2c@48070000/tps659038@58/tps659038_pmic/regulators/ldo3";
    		ldo4_reg = "/ocp/i2c@48070000/tps659038@58/tps659038_pmic/regulators/ldo4";
    		ldo9_reg = "/ocp/i2c@48070000/tps659038@58/tps659038_pmic/regulators/ldo9";
    		ldoln_reg = "/ocp/i2c@48070000/tps659038@58/tps659038_pmic/regulators/ldoln";
    		ldousb_reg = "/ocp/i2c@48070000/tps659038@58/tps659038_pmic/regulators/ldousb";
    		regen1 = "/ocp/i2c@48070000/tps659038@58/tps659038_pmic/regulators/regen1";
    		tps659038_rtc = "/ocp/i2c@48070000/tps659038@58/tps659038_rtc";
    		tps659038_pwr_button = "/ocp/i2c@48070000/tps659038@58/tps659038_pwr_button";
    		tps659038_gpio = "/ocp/i2c@48070000/tps659038@58/tps659038_gpio";
    		i2c2 = "/ocp/i2c@48072000";
    		i2c3 = "/ocp/i2c@48060000";
    		mcp_rtc = "/ocp/i2c@48060000/rtc@6f";
    		i2c4 = "/ocp/i2c@4807a000";
    		i2c5 = "/ocp/i2c@4807c000";
    		mmc1 = "/ocp/mmc@4809c000";
    		mmc2 = "/ocp/mmc@480b4000";
    		mmc3 = "/ocp/mmc@480ad000";
    		mmc4 = "/ocp/mmc@480d1000";
    		mmu0_dsp1 = "/ocp/mmu@40d01000";
    		mmu1_dsp1 = "/ocp/mmu@40d02000";
    		mmu_ipu1 = "/ocp/mmu@58882000";
    		mmu_ipu2 = "/ocp/mmu@55082000";
    		abb_mpu = "/ocp/regulator-abb-mpu";
    		abb_ivahd = "/ocp/regulator-abb-ivahd";
    		abb_dspeve = "/ocp/regulator-abb-dspeve";
    		abb_gpu = "/ocp/regulator-abb-gpu";
    		mcspi1 = "/ocp/spi@48098000";
    		mcspi2 = "/ocp/spi@4809a000";
    		mcspi3 = "/ocp/spi@480b8000";
    		mcspi4 = "/ocp/spi@480ba000";
    		qspi = "/ocp/qspi@4b300000";
    		sata_phy = "/ocp/ocp2scp@4a090000/phy@4A096000";
    		pcie1_phy = "/ocp/ocp2scp@4a090000/pciephy@4a094000";
    		pcie2_phy = "/ocp/ocp2scp@4a090000/pciephy@4a095000";
    		sata = "/ocp/sata@4a141100";
    		rtc = "/ocp/rtc@48838000";
    		usb2_phy1 = "/ocp/ocp2scp@4a080000/phy@4a084000";
    		usb2_phy2 = "/ocp/ocp2scp@4a080000/phy@4a085000";
    		usb3_phy1 = "/ocp/ocp2scp@4a080000/phy@4a084400";
    		omap_dwc3_1 = "/ocp/omap_dwc3_1@48880000";
    		usb1 = "/ocp/omap_dwc3_1@48880000/usb@48890000";
    		omap_dwc3_2 = "/ocp/omap_dwc3_2@488c0000";
    		usb2 = "/ocp/omap_dwc3_2@488c0000/usb@488d0000";
    		omap_dwc3_3 = "/ocp/omap_dwc3_3@48900000";
    		usb3 = "/ocp/omap_dwc3_3@48900000/usb@48910000";
    		elm = "/ocp/elm@48078000";
    		gpmc = "/ocp/gpmc@50000000";
    		atl = "/ocp/atl@4843c000";
    		mcasp1 = "/ocp/mcasp@48460000";
    		mcasp2 = "/ocp/mcasp@48464000";
    		mcasp3 = "/ocp/mcasp@48468000";
    		mcasp4 = "/ocp/mcasp@4846c000";
    		mcasp5 = "/ocp/mcasp@48470000";
    		mcasp6 = "/ocp/mcasp@48474000";
    		mcasp7 = "/ocp/mcasp@48478000";
    		mcasp8 = "/ocp/mcasp@4847c000";
    		crossbar_mpu = "/ocp/crossbar@4a002a48";
    		mac = "/ocp/ethernet@48484000";
    		davinci_mdio = "/ocp/ethernet@48484000/mdio@48485000";
    		cpsw_emac0 = "/ocp/ethernet@48484000/slave@48480200";
    		cpsw_emac1 = "/ocp/ethernet@48484000/slave@48480300";
    		phy_sel = "/ocp/ethernet@48484000/cpsw-phy-sel@4a002554";
    		dcan1 = "/ocp/can@481cc000";
    		dcan2 = "/ocp/can@481d0000";
    		dss = "/ocp/dss@58000000";
    		hdmi = "/ocp/dss@58000000/encoder@58060000";
    		epwmss0 = "/ocp/epwmss@4843e000";
    		ehrpwm0 = "/ocp/epwmss@4843e000/pwm@4843e200";
    		ecap0 = "/ocp/epwmss@4843e000/ecap@4843e100";
    		epwmss1 = "/ocp/epwmss@48440000";
    		ehrpwm1 = "/ocp/epwmss@48440000/pwm@48440200";
    		ecap1 = "/ocp/epwmss@48440000/ecap@48440100";
    		epwmss2 = "/ocp/epwmss@48442000";
    		ehrpwm2 = "/ocp/epwmss@48442000/pwm@48442200";
    		ecap2 = "/ocp/epwmss@48442000/ecap@48442100";
    		aes1 = "/ocp/aes@4b500000";
    		aes2 = "/ocp/aes@4b700000";
    		des = "/ocp/des@480a5000";
    		sham = "/ocp/sham@53100000";
    		rng = "/ocp/rng@48090000";
    		dsp2_system = "/ocp/dsp_system@41500000";
    		omap_dwc3_4 = "/ocp/omap_dwc3_4@48940000";
    		usb4 = "/ocp/omap_dwc3_4@48940000/usb@48950000";
    		mmu0_dsp2 = "/ocp/mmu@41501000";
    		mmu1_dsp2 = "/ocp/mmu@41502000";
    		thermal_zones = "/thermal-zones";
    		cpu_thermal = "/thermal-zones/cpu_thermal";
    		cpu_trips = "/thermal-zones/cpu_thermal/trips";
    		cpu_alert0 = "/thermal-zones/cpu_thermal/trips/cpu_alert";
    		cpu_crit = "/thermal-zones/cpu_thermal/trips/cpu_crit";
    		cpu_alert1 = "/thermal-zones/cpu_thermal/trips/cpu_alert1";
    		cpu_cooling_maps = "/thermal-zones/cpu_thermal/cooling-maps";
    		gpu_thermal = "/thermal-zones/gpu_thermal";
    		gpu_crit = "/thermal-zones/gpu_thermal/trips/gpu_crit";
    		core_thermal = "/thermal-zones/core_thermal";
    		core_crit = "/thermal-zones/core_thermal/trips/core_crit";
    		dspeve_thermal = "/thermal-zones/dspeve_thermal";
    		dspeve_crit = "/thermal-zones/dspeve_thermal/trips/dspeve_crit";
    		iva_thermal = "/thermal-zones/iva_thermal";
    		iva_crit = "/thermal-zones/iva_thermal/trips/iva_crit";
    		vdd_3v3 = "/fixedregulator-vdd_3v3";
    		aic_dvdd = "/fixedregulator-aic_dvdd";
    		vtt_fixed = "/fixedregulator-vtt";
    	};
    };

    This is the modified mux_data.h

    /* SPDX-License-Identifier: GPL-2.0+ */
    /*
     * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
     *
     * Author: Felipe Balbi <balbi@ti.com>
     *
     * Based on board/ti/dra7xx/evm.c
     */
    #ifndef _MUX_DATA_BEAGLE_X15_H_
    #define _MUX_DATA_BEAGLE_X15_H_
    
    #include <asm/arch/mux_dra7xx.h>
    
    const struct pad_conf_entry core_padconf_array_essential_sec4[] = {
    	{GPMC_AD0, (M0 | PIN_INPUT)},	/* gpmc_ad0.GPMC_AD0 */
    	{GPMC_AD1, (M0 | PIN_INPUT)},	/* gpmc_ad1.GPMC_AD1 */
    	{GPMC_AD2, (M0 | PIN_INPUT)},	/* gpmc_ad2.GPMC_AD2 */
    	{GPMC_AD3, (M0 | PIN_INPUT)},	/* gpmc_ad3.GPMC_AD3 */
    	{GPMC_AD4, (M0 | PIN_INPUT)},	/* gpmc_ad4.GPMC_AD4 */
    	{GPMC_AD5, (M0 | PIN_INPUT)},	/* gpmc_ad5.GPMC_AD5 */
    	{GPMC_AD6, (M0 | PIN_INPUT)},	/* gpmc_ad6.GPMC_AD6 */
    	{GPMC_AD7, (M0 | PIN_INPUT)},	/* gpmc_ad7.GPMC_AD7 */
    	{GPMC_AD8, (M0 | PIN_INPUT)},	/* gpmc_ad8.GPMC_AD8 */
    	{GPMC_AD9, (M0 | PIN_INPUT)},	/* gpmc_ad9.GPMC_AD9 */
    	{GPMC_AD10, (M0 | PIN_INPUT)},	/* gpmc_ad10.GPMC_AD10 */
    	{GPMC_AD11, (M0 | PIN_INPUT)},	/* gpmc_ad11.GPMC_AD11 */
    	{GPMC_AD12, (M0 | PIN_INPUT)},	/* gpmc_ad12.GPMC_AD12 */
    	{GPMC_AD13, (M0 | PIN_INPUT)},	/* gpmc_ad13.GPMC_AD13 */
    	{GPMC_AD14, (M0 | PIN_INPUT)},	/* gpmc_ad14.GPMC_AD14 */
    	{GPMC_AD15, (M0 | PIN_INPUT)},	/* gpmc_ad15.GPMC_AD15 */
    	{GPMC_A0, (M15 | PIN_INPUT_PULLDOWN)},	/* gpmc_a0.driver_off */
    	{GPMC_A1, (M0 | PIN_OUTPUT_PULLDOWN)},	/* gpmc_a1.gpmc_a1 */
    	{GPMC_A2, (M0 | PIN_OUTPUT_PULLDOWN)},	/* gpmc_a2.gpmc_a2 */
    	{GPMC_A3, (M0 | PIN_OUTPUT_PULLDOWN)},	/* gpmc_a3.gpmc_a3 */
    	{GPMC_A4, (M0 | PIN_OUTPUT_PULLDOWN)},	/* gpmc_a4.gpmc_a4 */
    	{GPMC_A5, (M0 | PIN_OUTPUT_PULLDOWN)},	/* gpmc_a5.gpmc_a5 */
    	{GPMC_A6, (M0 | PIN_OUTPUT_PULLDOWN)},	/* gpmc_a6.gpmc_a6 */
    	{GPMC_A7, (M0 | PIN_OUTPUT_PULLDOWN)},	/* gpmc_a7.gpmc_a7 */
    	{GPMC_A8, (M0 | PIN_OUTPUT_PULLDOWN)},	/* gpmc_a8.gpmc_a8 */
    	{GPMC_A9, (M0 | PIN_OUTPUT_PULLDOWN)},	/* gpmc_a9.gpmc_a9 */
    	{GPMC_A10, (M0 | PIN_OUTPUT_PULLDOWN)},	/* gpmc_a10.gpmc_a10 */
    	{GPMC_A11, (M0 | PIN_OUTPUT_PULLDOWN)},	/* gpmc_a11.gpmc_a11 */
    	{GPMC_A12, (M0 | PIN_OUTPUT_PULLDOWN)},	/* gpmc_a12.gpmc_a12 */
    	{GPMC_A13, (M0 | PIN_OUTPUT_PULLDOWN)},	/* gpmc_a13.gpmc_a13 */
    	{GPMC_A14, (M0 | PIN_OUTPUT_PULLDOWN)},	/* gpmc_a14.gpmc_a14 */
    	{GPMC_A15, (M0 | PIN_OUTPUT_PULLDOWN)},	/* gpmc_a15.gpmc_a15 */
    	{GPMC_A16, (M0 | PIN_OUTPUT_PULLDOWN)},	/* gpmc_a16.gpmc_a16 */
    	{GPMC_A17, (M0 | PIN_OUTPUT_PULLDOWN)},	/* gpmc_a17.gpmc_a17 */
    	{GPMC_A18, (M0 | PIN_OUTPUT_PULLDOWN)},	/* gpmc_a18.gpmc_a18 */
    	{GPMC_A19, (M0 | PIN_OUTPUT_PULLDOWN)},	/* gpmc_a19.gpmc_a19 */
    	{GPMC_A20, (M0 | PIN_OUTPUT_PULLDOWN)},	/* gpmc_a20.gpmc_a20 */
    	{GPMC_A21, (M0 | PIN_OUTPUT_PULLDOWN)},	/* gpmc_a21.gpmc_a21 */
    	{GPMC_A22, (M0 | PIN_OUTPUT_PULLDOWN)},	/* gpmc_a22.gpmc_a22 */
    	{GPMC_A23, (M0 | PIN_OUTPUT_PULLDOWN)},	/* gpmc_a23.gpmc_a23 */
    	{GPMC_A24, (M0 | PIN_OUTPUT_PULLDOWN)},	/* gpmc_a24.gpmc_a24 */
    	{GPMC_A25, (M0 | PIN_OUTPUT_PULLDOWN)},	/* gpmc_a25.gpmc_a25 */
    	{GPMC_A26, (M0 | PIN_OUTPUT_PULLDOWN)},	/* gpmc_a26.gpmc_a26 */
    	{GPMC_A27, (M0 | PIN_OUTPUT_PULLDOWN)},	/* gpmc_a27.gpmc_a27 */
    	{GPMC_CS0, (M0 | PIN_OUTPUT_PULLDOWN)},	/* gpmc_cs0.gpmc_cs0 */
    	{GPMC_CS1, (M0 | PIN_OUTPUT_PULLDOWN)},	/* gpmc_cs1.gpmc_cs1 */
    	{GPMC_CS2, (M0 | PIN_OUTPUT_PULLDOWN)},	/* gpmc_cs2.gpmc_cs2 */
    	{GPMC_CS3, (M0 | PIN_OUTPUT_PULLDOWN)},	/* gpmc_cs3.gpmc_cs3 */
    	{GPMC_CLK, (M3 | PIN_INPUT_PULLUP)},	/* gpmc_clk.gpmc_wait1 */
    	{GPMC_ADVN_ALE, (M0 | PIN_OUTPUT_PULLDOWN)},	/* gpmc_advn_ale.gpmc_advn_ale */
    	{GPMC_OEN_REN, (M0 | PIN_OUTPUT_PULLDOWN)},	/* gpmc_oen_ren.gpmc_oen_ren */
    	{GPMC_WEN, (M0 | PIN_OUTPUT_PULLDOWN)},	/* gpmc_wen.gpmc_wen */
    	{GPMC_BEN0, (M0 | PIN_OUTPUT_PULLDOWN)},	/* gpmc_ben0.gpmc_ben0 */
    	{GPMC_BEN1, (M0 | PIN_OUTPUT_PULLDOWN)},	/* gpmc_ben1.gpmc_ben1 */
    	{GPMC_WAIT0, (M0 | PIN_INPUT_PULLUP)},	/* gpmc_wait0.GPMC_WAIT0 */
    
    	{VIN1A_D0, (M14 | PIN_OUTPUT_PULLDOWN)},		/* relais_test_in_sig	vin1a_d0.gpio3_4 */
    	{VIN1A_D1, (M14 | PIN_INPUT_PULLUP)},		/* ~irq_uart01_exp		vin1a_d1.gpio3_5 */
    	{VIN1A_D2, (M14 | PIN_INPUT)},				/* hwv_b5--hrtb 		vin1a_d2.gpio3_6 */
    	{VIN1A_D3, (M14 | PIN_INPUT)},				/* hwv_b4 				vin1a_d3.gpio3_7 */
    	{VIN1A_D4, (M14 | PIN_INPUT)},				/* hwv_b1 				vin1a_d4.gpio3_8 */
    	{VIN1A_D5, (M14 | PIN_INPUT)},				/* hwv_b3 				vin1a_d5.gpio3_9 */
    	{VIN1A_D6, (M14 | PIN_INPUT_PULLUP)},		/* ~irq_uart23_exp	vin1a_d6.gpio3_10 */
    	{VIN1A_D7, (M14 | PIN_INPUT)},				/* hwv_b2 				vin1a_d7.gpio3_11 */
    	{VIN1A_D8, (M14 | PIN_OUTPUT_PULLDOWN)},	/* ertec_rst_in		vin1a_d8.gpio3_12 */
    	{VIN1A_D9, (M14 | PIN_INPUT)},				/* hwv_b0 				vin1a_d8.gpio3_13 */
    	{VIN1A_D10, (M14 | PIN_INPUT)},				/* ertec_pmic_pgood	vin1a_d10.gpio3_14 */
    	{VIN1A_D11, (M14 | PIN_OUTPUT_PULLDOWN)},	/* usr_led				vin1a_d11.gpio3_15 */
    	{VIN1A_D12, (M14 | PIN_INPUT_PULLDOWN)},	/* pwr_ref1				vin1a_d12.gpio3_16 */
    	{VIN1A_D13, (M14 | PIN_INPUT)},				/* relais_test_out_sig	vin1a_d13.gpio3_17 */
    	{VIN1A_D14, (M14 | PIN_INPUT)},				/* ertec_pmic_pgood	pwr_ref2	vin1a_d14.gpio3_18 */
    	{VIN1A_D15, (M14 | PIN_INPUT)},				/* __gpmc_irq		pwr_ref2	vin1a_d14.gpio3_19 */
    	{GPIO6_16, (M0 | PIN_INPUT_PULLUP)},		/* SYS_NIRQ1		 gpio6_16.gpio6_16 */
    
    	{VIN1A_D16, (M15 | PIN_INPUT_PULLDOWN)},	/* NC vin1a_d16.Driver_off */
    	{VIN1A_D19, (M15 | PIN_INPUT_PULLDOWN)},	/* NC vin1a_d19.Driver_off */
    	{VIN1A_D20, (M15 | PIN_INPUT_PULLDOWN)},	/* NC vin1a_d20.Driver_off */
    	{VIN1A_D22, (M15 | PIN_INPUT_PULLDOWN)},	/* NC vin1a_d22.Driver_off */
    	{VIN2A_CLK0, (M15 | PIN_INPUT_PULLDOWN)},	/* NC vin2a_clk0.Driver_off */
    	{VIN2A_DE0, (M15 | PIN_INPUT_PULLDOWN)},	/* NC vin2a_de0.Driver_off */
    	{VIN2A_FLD0, (M15 | PIN_INPUT_PULLDOWN)},	/* NC vin2a_fld0.Driver_off */
    	{VIN2A_HSYNC0, (M15 | PIN_INPUT_PULLDOWN)},/* NC vin2a_hsync0.Driver_off */
    	{VIN2A_VSYNC0, (M15 | PIN_INPUT_PULLDOWN)},/* NC vin2a_vsync0.Driver_off */
    	{VIN2A_D0, (M15 | PIN_INPUT_PULLDOWN)},	/* NC vin2a_d0.Driver_off */
    	{VIN2A_D1, (M15 | PIN_INPUT_PULLDOWN)},	/* NC vin2a_d1.Driver_off */
    	{VIN2A_D2, (M15 | PIN_INPUT_PULLDOWN)},	/* NC vin2a_d2.Driver_off */
    	{VIN2A_D3, (M15 | PIN_INPUT_PULLDOWN)},	/* NC vin2a_d3.Driver_off */
    	{VIN2A_D4, (M15 | PIN_INPUT_PULLDOWN)},	/* NC vin2a_d4.Driver_off */
    	{VIN2A_D5, (M15 | PIN_INPUT_PULLDOWN)},	/* NC vin2a_d5.Driver_off */
    	{VOUT1_FLD, (M15 | PIN_INPUT_PULLDOWN)},	/* NC vout1_fld.Driver_off */
    	{GPIO6_14, (M15 | PIN_INPUT_PULLDOWN)},	/* NC gpio6_14.Driver_off */
    	{GPIO6_15, (M15 | PIN_INPUT_PULLDOWN)},	/* NC gpio6_15.Driver_off */
    	{XREF_CLK0, (M15 | PIN_INPUT_PULLDOWN)},	/* NC xref_clk0.Driver_off */
    	{XREF_CLK1, (M15 | PIN_INPUT_PULLDOWN)},	/* NC xref_clk1.Driver_off */
    	{XREF_CLK2, (M15 | PIN_INPUT_PULLDOWN)},	/* NC xref_clk2.Driver_off */
    	{XREF_CLK3, (M15 | PIN_INPUT_PULLDOWN)},	/* NC xref_clk3.Driver_off */
    	{MCASP1_ACLKR, (M15 | PIN_INPUT_PULLDOWN)},/* NC MCASP1_aclkr.Driver_off */
    	{MCASP1_FSR, (M15 | PIN_INPUT_PULLDOWN)},	/* NC MCASP1_fsr.Driver_off */
    	{MCASP1_AXR2, (M15 | PIN_INPUT_PULLDOWN)},	/* NC MCASP1_AXR2.Driver_off */
    	{MCASP1_AXR3, (M15 | PIN_INPUT_PULLDOWN)},	/* NC MCASP1_AXR3.Driver_off */
    	{MCASP1_AXR4, (M15 | PIN_INPUT_PULLDOWN)},	/* NC MCASP1_AXR4.Driver_off */
    	{MCASP1_AXR5, (M15 | PIN_INPUT_PULLDOWN)},	/* NC MCASP1_AXR5.Driver_off */
    	{MCASP1_AXR6, (M15 | PIN_INPUT_PULLDOWN)},	/* NC MCASP1_AXR6.Driver_off */
    	{MCASP1_AXR7, (M15 | PIN_INPUT_PULLDOWN)},	/* NC MCASP1_AXR7.Driver_off */
    	{MCASP3_AXR0, (M15 | PIN_INPUT_PULLDOWN)},	/* NC MCASP3_AXR0.Driver_off */
    	{MCASP3_AXR1, (M15 | PIN_INPUT_PULLDOWN)},	/* NC MCASP3_AXR1.Driver_off */
    	{MMC3_CLK, (M15 | PIN_INPUT_PULLUP)},			/* NC mmc3_clk.Driver_off */
    	{MMC3_CMD, (M15 | PIN_INPUT_PULLUP)},			/* NC mmc3_cmd.Driver_off */
    	{MMC3_DAT0, (M15 | PIN_INPUT_PULLUP)},			/* NC mmc3_dat0.Driver_off */
    	{MMC3_DAT1, (M15 | PIN_INPUT_PULLUP)},			/* NC mmc3_dat1.Driver_off */
    	{MMC3_DAT2, (M15 | PIN_INPUT_PULLUP)},			/* NC mmc3_dat2.Driver_off */
    	{MMC3_DAT3, (M15 | PIN_INPUT_PULLUP)},			/* NC mmc3_dat3.Driver_off */
    	{MMC3_DAT4, (M15 | PIN_INPUT_PULLUP)},			/* NC mmc3_dat4.Driver_off */
    	{MMC3_DAT5, (M15 | PIN_INPUT_PULLUP)},			/* NC mmc3_dat5.Driver_off */
    	{MMC3_DAT6, (M15 | PIN_INPUT_PULLUP)},			/* NC mmc3_dat6.Driver_off */
    	{MMC3_DAT7, (M15 | PIN_INPUT_PULLUP)},			/* NC mmc3_dat7.Driver_off */
    	{MCASP5_ACLKX, (M15 | PIN_INPUT_PULLDOWN)},	/* NC MCASP5_aclkx.Driver_off */
    	{MCASP5_FSX, (M15 | PIN_INPUT_PULLDOWN)},		/* NC MCASP5_fsx.Driver_off */
    	{MCASP5_AXR0, (M15 | PIN_INPUT_PULLDOWN)},	/* NC MCASP5_AXR0.Driver_off */
    	{MCASP5_AXR1, (M15 | PIN_INPUT_PULLDOWN)},	/* NC MCASP5_AXR1.Driver_off */
    	{DCAN1_TX, (M15 | PIN_INPUT_PULLUP)},		/* NC dcan1_tx.Driver_off */
    	{DCAN1_RX, (M15 | PIN_INPUT_PULLDOWN)},	/* SATA1 dcan1_rx.DRIVER_OFF */
    	{VIN1B_CLK1, (M15 | PIN_INPUT_PULLDOWN)},	/* NC	vin1b_clk1.Driver_off  */  
    	{VOUT1_CLK, (M15 | PIN_INPUT_PULLDOWN)},	/* vout1_clk.driver_off */
    	{VOUT1_DE, (M15 | PIN_INPUT_PULLDOWN)},	/* vout1_de.driver_off */
    	{VOUT1_HSYNC, (M15 | PIN_INPUT_PULLDOWN)},	/* vout1_hsync.driver_off */
    	{VOUT1_VSYNC, (M15 | PIN_INPUT_PULLDOWN)},	/* vout1_vsync.driver_off */
    	{VOUT1_D0, (M15 | PIN_INPUT_PULLDOWN)},	/* vout1_d0.driver_off */
    	{VOUT1_D1, (M15 | PIN_INPUT_PULLDOWN)},	/* vout1_d1.driver_off */
    	{VOUT1_D2, (M15 | PIN_INPUT_PULLDOWN)},	/* vout1_d2.driver_off */
    	{VOUT1_D3, (M15 | PIN_INPUT_PULLDOWN)},	/* vout1_d3.driver_off */
    	{VOUT1_D4, (M15 | PIN_INPUT_PULLDOWN)},	/* vout1_d4.driver_off */
    	{VOUT1_D5, (M15 | PIN_INPUT_PULLDOWN)},	/* vout1_d5.driver_off */
    	{VOUT1_D6, (M15 | PIN_INPUT_PULLDOWN)},	/* vout1_d6.driver_off */
    	{VOUT1_D7, (M15 | PIN_INPUT_PULLDOWN)},	/* vout1_d7.driver_off */
    	{VOUT1_D8, (M15 | PIN_INPUT_PULLDOWN)},	/* vout1_d8.driver_off */
    	{VOUT1_D9, (M15 | PIN_INPUT_PULLDOWN)},	/* vout1_d9.driver_off */
    	{VOUT1_D10, (M15 | PIN_INPUT_PULLDOWN)},	/* vout1_d10.driver_off */
    	{VOUT1_D11, (M15 | PIN_INPUT_PULLDOWN)},	/* vout1_d11.driver_off */
    	{VOUT1_D12, (M15 | PIN_INPUT_PULLDOWN)},	/* vout1_d12.driver_off */
    	{VOUT1_D13, (M15 | PIN_INPUT_PULLDOWN)},	/* vout1_d13.driver_off */
    	{VOUT1_D14, (M15 | PIN_INPUT_PULLDOWN)},	/* vout1_d14.driver_off */
    	{VOUT1_D15, (M15 | PIN_INPUT_PULLDOWN)},	/* vout1_d15.driver_off */
    	{VOUT1_D16, (M15 | PIN_INPUT_PULLDOWN)},	/* vout1_d16.driver_off */
    	{VOUT1_D17, (M15 | PIN_INPUT_PULLDOWN)},	/* vout1_d17.driver_off */
    	{VOUT1_D18, (M15 | PIN_INPUT_PULLDOWN)},	/* vout1_d18.driver_off */
    	{VOUT1_D19, (M15 | PIN_INPUT_PULLDOWN)},	/* vout1_d19.driver_off */
    	{VOUT1_D20, (M15 | PIN_INPUT_PULLDOWN)},	/* vout1_d20.driver_off */
    	{VOUT1_D21, (M15 | PIN_INPUT_PULLDOWN)},	/* vout1_d21.driver_off */
    	{VOUT1_D22, (M15 | PIN_INPUT_PULLDOWN)},	/* vout1_d22.driver_off */
    	{VOUT1_D23, (M15 | PIN_INPUT_PULLDOWN)},	/* vout1_d23.driver_off */
    	{WAKEUP0, (M15 | PIN_INPUT_PULLDOWN)},	/* NC Wakeup0.Driver off */
    	{WAKEUP1, (M15 | PIN_INPUT_PULLDOWN)},	/* NC Wakeup1.Driver off */
    	{WAKEUP2, (M15 | PIN_INPUT_PULLDOWN)},	/* NC Wakeup2.Driver off */
    	{WAKEUP3, (M15 | PIN_INPUT_PULLDOWN)},	/* NC Wakeup3.Driver off */	
    	{UART1_RXD, (M15 | PIN_INPUT_PULLDOWN)},/* NC uart1_rxd.disabled */
    	{UART1_TXD, (M15 | PIN_INPUT_PULLDOWN)},	/* NC uart1_txd.disabled */
    	{UART1_CTSN, (M15 | PIN_INPUT_PULLDOWN)},	/* NC uart1_ctsn.disabled */
    	{UART1_RTSN, (M15 | PIN_INPUT_PULLDOWN)},	/* NC uart1_rtsn.disabled */
    	{UART2_RXD, (M15 | PIN_INPUT_PULLDOWN)},	/* NC uart2_rxd.disabled */
    	{UART2_TXD, (M15 | PIN_INPUT_PULLDOWN)},	/* NC uart2_txd.disabled */
    
    
    
    	
    	{MDIO_MCLK, (M0 | PIN_OUTPUT | SLEWCONTROL)},/* EPHY_0_1 mdio_mclk.mdio_mclk */
    	{MDIO_D, (M0 | PIN_INPUT | SLEWCONTROL)},		/* EPHY_0_1 mdio_d.mdio_d */
    	{RMII_MHZ_50_CLK, (M0 | PIN_INPUT_PULLDOWN)},/* EPHY_0_1 RMII_MHZ_50_CLK.RMII_MHZ_50_CLK */
    
    	{RGMII0_TXD3, (M1 | PIN_INPUT_PULLDOWN)},		/* EPHY0 rgmii0_txd3.rmii0_crs */
    	{RGMII0_TXD2, (M1 | PIN_INPUT_PULLDOWN )},	/* EPHY0 rgmii0_txd2.rmii0_rxer  */
    	{RGMII0_TXD1, (M1 | PIN_INPUT_PULLDOWN )},	/* EPHY0 rgmii0_txd1.rmii0_rxd1 */
    	{RGMII0_TXD0, (M1 | PIN_INPUT_PULLDOWN )},	/* EPHY0 rgmii0_txd0.rmii0_rxd0 */
    	{RGMII0_RXD2, (M1 | PIN_OUTPUT_PULLDOWN )},	/* EPHY0 rgmii0_rxd2.rmii0_txen */
    	{RGMII0_RXD1, (M1 | PIN_OUTPUT_PULLDOWN )},	/* EPHY0 rgmii0_rxd1.rmii0_txd1 */
    	{RGMII0_RXD0, (M1 | PIN_OUTPUT_PULLDOWN )},	/* EPHY0 rgmii0_rxd0.rmii0_txd0 */
    
    	{UART3_RXD, (M2 | PIN_INPUT_PULLDOWN)},		/* EPHY1 uart3_rxd.rmii1_crs  */
    	{UART3_TXD, (M2 | PIN_INPUT_PULLDOWN)},		/* EPHY1 uart3_txd.rmii1_rxer */
    	{RGMII0_TXC, (M2 | PIN_INPUT_PULLDOWN)},		/* EPHY1 rgmii0_txc.rmii1_rxd1 */
    	{RGMII0_TXCTL, (M2 | PIN_INPUT_PULLDOWN)},	/* EPHY1 rgmii0_txctl.rmii1_rxd0 */
    	{RGMII0_RXC, (M2 | PIN_OUTPUT_PULLDOWN )},	/* EPHY1 rgmii0_rxc.rmii1_txd1 */
    	{RGMII0_RXCTL, (M2 | PIN_OUTPUT_PULLDOWN )},	/* EPHY1 rgmii0_rxctl.rmii1_txd1 */
    	{RGMII0_RXD3, (M2 | PIN_OUTPUT_PULLDOWN )},	/* EPHY1 rgmii0_rxd3.rmii1_txd0 */
    
    	{USB1_DRVVBUS, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* usb1_drvvbus.usb1_drvvbus */
    	{USB2_DRVVBUS, (M0 | PIN_OUTPUT_PULLDOWN | SLEWCONTROL)},	/* usb2_drvvbus.usb2_drvvbus */
    
    
    
    	{VIN2A_D6, (M11 | PIN_INPUT_PULLDOWN)},	/* EPHY2 vin2a_d6.pr1_mii_mt1_clk */
    	{VIN2A_D7, (M11 | PIN_OUTPUT_PULLDOWN)},	/* EPHY2 vin2a_d7.pr1_mii1_txen */
    	{VIN2A_D13, (M11 | PIN_OUTPUT_PULLDOWN)},	/* EPHY2 vin2a_d13.pr1_mii1_txd0 */
    	{VIN2A_D12, (M11 | PIN_OUTPUT_PULLDOWN)},	/* EPHY2 vin2a_d12.pr1_mii1_txd1 */
    	{VIN2A_D9, (M11 | PIN_OUTPUT_PULLDOWN)},	/* EPHY2 vin2a_d9.pr1_mii1_txd2 */
    	{VIN2A_D8, (M8 | PIN_INPUT_PULLDOWN)},		/* EPHY2 vin2a_d8.mii1_rxd3 */
    	{VIN2A_D14, (M11 | PIN_INPUT_PULLDOWN)},	/* EPHY2 vin2a_d14.pr1_mii_mr1_clk  */
    	{VIN2A_D15, (M11 | PIN_INPUT_PULLDOWN)},	/* EPHY2 vin2a_d15.pr1_mii1_rxdv  */
    	{VIN2A_D20, (M8 | PIN_INPUT_PULLDOWN)},	/* EPHY2 vin2a_d20.mii1_rxer  */
    	{VIN2A_D19, (M11 | PIN_INPUT_PULLDOWN)},	/* EPHY2 vin2a_d19.pr1_mii1_rxd0 */
    	{VIN2A_D18, (M11 | PIN_INPUT_PULLDOWN)},	/* EPHY2 vin2a_d18.pr1_mii1_rxd1 */
    	{VIN2A_D17, (M11 | PIN_INPUT_PULLDOWN)},	/* EPHY2 vin2a_d17.pr1_mii1_rxd2  */
    	{VIN2A_D16, (M11 | PIN_INPUT_PULLDOWN)},	/* EPHY2 vin2a_d16.pr1_mii1_rxd3  */
    	{VIN2A_D22, (M11 | PIN_INPUT_PULLDOWN)},	/* EPHY2 vin2a_d22.pr1_mii1_col  */
    	{VIN2A_D23, (M11 | PIN_INPUT_PULLDOWN)},	/* EPHY2 vin2a_d23.pr1_mii1_crs */
    	{VIN2A_D10, (M11 | PIN_OUTPUT_PULLDOWN)},	/* EPHY2 vin2a_d10.pr1_mdio_mdclk */
    	{VIN2A_D11, (M3 | PIN_INPUT_PULLDOWN)},	/* EPHY2 vin2a_d11.mdio_d  */
    	{VIN2A_D21, (M11 | PIN_INPUT_PULLDOWN)},	/* EPHY2 vin2a_d21.pr1_mii1_rxlink  */
    
    
    
    	{MCASP1_AXR1, (M11 | PIN_INPUT_PULLDOWN)},	/* EPHY3 MCASP1_AXR1.pr2_mii_mt0_clk */
    	{MCASP1_AXR8, (M11 | PIN_OUTPUT_PULLDOWN)},	/* EPHY3 MCASP1_AXR8.pr2_mii0_txen */
    	{MCASP1_AXR12, (M11 | PIN_OUTPUT_PULLDOWN)},	/* EPHY3 MCASP1_AXR12.pr2_mii0_txd0 */
    	{MCASP1_AXR11, (M11 | PIN_OUTPUT_PULLDOWN)},	/* EPHY3 MCASP1_AXR11.pr2_mii0_txd1  */
    	{MCASP1_AXR10, (M11 | PIN_OUTPUT_PULLDOWN)},	/* EPHY3 MCASP1_AXR10.pr2_mii0_txd2 */
    	{MCASP1_AXR9, (M11 | PIN_OUTPUT_PULLDOWN)},	/* EPHY3 MCASP1_AXR9.pr2_mii0_txd3  */
    	{MCASP1_AXR13, (M11 | PIN_INPUT_PULLDOWN)},	/* EPHY3 MCASP1_AXR13.pr2_mii_mr0_clk */
    	{MCASP1_AXR14, (M11 | PIN_INPUT_PULLDOWN)},	/* EPHY3 MCASP1_AXR14.pr2_mii0_rxdv  */
    	{MCASP1_AXR0, (M11 | PIN_INPUT_PULLDOWN)},	/* EPHY3 MCASP1_AXR14.pr2_mii0_rxer  */
    	{MCASP2_AXR2, (M11 | PIN_INPUT_PULLDOWN)},	/* EPHY3 MCASP2_AXR2.pr2_mii0_rxd0 */
    	{MCASP2_FSX, (M11 | PIN_INPUT_PULLDOWN)},		/* EPHY3 MCASP2_fsx.pr2_mii0_rxd1 */
    	{MCASP2_ACLKX, (M11 | PIN_INPUT_PULLDOWN)},	/* EPHY3 MCASP2_aclkx.pr2_mii0_rxd2 */
    	{MCASP1_AXR15, (M11 | PIN_INPUT_PULLDOWN)},	/* EPHY3 MCASP1_AXR15.pr2_mii0_rxd3 */
    	{MCASP3_FSX, (M11 | PIN_INPUT_PULLDOWN)},		/* EPHY3 MCASP3_fsx.pr2_mii0_col */
    	{MCASP3_ACLKX, (M11 | PIN_INPUT_PULLDOWN)},	/* EPHY3 MCASP3_aclkx.pr2_mii0_crs */
    	{MCASP1_ACLKX, (M11 | PIN_INPUT_PULLUP)},		/* EPHY3 MCASP1_aclkx.pr2_mdio_mdclk */
    	{MCASP1_FSX, (M11 | PIN_INPUT_PULLUP)},		/* EPHY3 MCASP1_fsx.pr2_mdio_data */
    	{MCASP1_FSX, (M11 | PIN_INPUT_PULLUP)},		/* EPHY3 MCASP1_fsx.pr2_mdio_data */
    	{MCASP2_AXR3, (M11 | PIN_INPUT_PULLUP)}, 		/* EPHY3 mcasp2_axr3.pr2_mii0_rxlink */
    
    
    	{MMC1_CLK, (M0 | PIN_INPUT_PULLUP)},	/* MMC1 mmc1_clk.mmc1_clk */
    	{MMC1_CMD, (M0 | PIN_INPUT_PULLUP)},	/* MMC1 mmc1_cmd.mmc1_cmd */
    	{MMC1_DAT0, (M0 | PIN_INPUT_PULLUP)},	/* MMC1 mmc1_dat0.mmc1_dat0 */
    	{MMC1_DAT1, (M0 | PIN_INPUT_PULLUP)},	/* MMC1 mmc1_dat1.mmc1_dat1 */
    	{MMC1_DAT2, (M0 | PIN_INPUT_PULLUP)},	/* MMC1 mmc1_dat2.mmc1_dat2 */
    	{MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)},	/* MMC1 mmc1_dat3.mmc1_dat3 */
    	{MMC1_SDCD, (M0 | PIN_INPUT_PULLUP)},	/* MMC1 mmc1_sdcd.mmc1_sdcd */
    	{MMC1_SDWP, (M0 | PIN_INPUT_PULLUP)},	/* MMC1 mmc1_sdwp.mmc1_sdwp */
    
    
    	{UART2_CTSN, (M2 | PIN_INPUT_PULLUP)},	/* UART3 uart2_ctsn.uart3_rxd */
    	{UART2_RTSN, (M1 | PIN_OUTPUT)},			/* UART3 uart2_rtsn.uart3_txd */
    
    	{MCASP4_ACLKX, (M3 | PIN_INPUT_PULLUP)},	/* UART8 MCASP4_aclkx.uart8_rxd */
    	{MCASP4_FSX, (M3 | PIN_OUTPUT)},				/* UART8 MCASP4_fsx.uart8_txd */
    	{MCASP4_AXR0, (M3 | PIN_INPUT_PULLUP)},	/* UART8 MCASP4_AXR0.uart8_ctsn */
    	{MCASP4_AXR1, (M3 | PIN_OUTPUT_PULLUP)},	/* UART8 MCASP4_AXR1.uart8_rtsn */
    
    
    	{I2C1_SDA, (M0 | PIN_INPUT_PULLUP)},	/* I2C1 i2c1_sda.i2c1_sda */
    	{I2C1_SCL, (M0 | PIN_INPUT_PULLUP)},	/* I2C1 i2c1_scl.i2c1_scl */
    	{I2C2_SDA, (M0 | PIN_INPUT_PULLUP)},	/* I2C2 i2c2_sda.i2c2_sda */
    	{I2C2_SCL, (M0 | PIN_INPUT_PULLUP)},	/* I2C2 i2c2_scl.i2c2_scl */
    	{GPIO6_10, (M2 | PIN_INPUT_PULLDOWN)},	/* I2C3 gpio6_10.i2c3_sda  */
    	{GPIO6_11, (M2 | PIN_INPUT_PULLUP)},	/* I2C3 gpio6_11.i2c3_scl */
    
    
    	{SPI1_SCLK, (M0 | PIN_INPUT_PULLDOWN)},/* SPI1 spi1_sclk.spi1_sclk */
    	{SPI1_D1, (M0 | PIN_INPUT_PULLDOWN)},	/* SPI1 spi1_d1.spi1_d1 */
    	{SPI1_D0, (M0 | PIN_INPUT_PULLDOWN)},	/* SPI1 spi1_d0.spi1_d0 */
    	{SPI1_CS0, (M0 | PIN_INPUT_PULLUP)},	/* SPI1 spi1_cs0.spi1_cs0 */
    	{SPI1_CS1, (M0 | PIN_INPUT_PULLUP)},	/* SPI1 spi1_cs1.spi1_cs1 */
    	{SPI1_CS2, (M0 | PIN_INPUT_PULLUP)},	/* SPI1 spi1_cs2.spi1_cs2 */
    	{SPI1_CS3, (M0 | PIN_INPUT_PULLUP)},	/* SPI1 spi1_cs3.spi1_cs3 */
    
    	{SPI2_SCLK, (M0 | PIN_INPUT_PULLDOWN)},/* SPI2 spi2_sclk.spi2_sclk */
    	{SPI2_D1, (M0 | PIN_INPUT_PULLDOWN)},	/* SPI2 spi2_d1.spi2_d1 */
    	{SPI2_D0, (M0 | PIN_INPUT_PULLDOWN)},	/* SPI2 spi2_d0.spi2_d0 */
    	{SPI2_CS0, (M0 | PIN_INPUT_PULLUP )},	/* SPI2 spi2_cs0.spi2_cs0 */
    
    	{ON_OFF, (M0 | PIN_OUTPUT_PULLDOWN)},	/* on_off.on_off */
    	{RTC_PORZ, (M0 | PIN_INPUT_PULLUP)},	/* rtc_porz.rtc_porz */
    	{RTC_ISO, (M0 | PIN_INPUT_PULLUP)},	/* rtc_porz.rtc_porz */
    	
    	{TMS, (M0 | PIN_INPUT_PULLUP)},	/* tms.tms */
    	{TDI, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* tdi.tdi */
    	{TDO, (M0 | PIN_OUTPUT)},	/* tdo.tdo */
    	{TCLK, (M0 | PIN_INPUT_PULLDOWN)},	/* tclk.tclk */
    	{TRSTN, (M0 | PIN_INPUT)},	/* trstn.trstn */
    	{RTCK, (M0 | PIN_OUTPUT)},	/* rtck.rtck */
    	{EMU0, (M0 | PIN_INPUT)},	/* emu0.emu0 */
    	{EMU1, (M0 | PIN_INPUT)},	/* emu1.emu1 */
    	{NMIN_DSP, (M0 | PIN_INPUT_PULLUP)},	/* nmin_dsp.nmin_dsp */
    	{RSTOUTN, (M0 | PIN_OUTPUT)},	/* rstoutn.rstoutn */
    };
    
    const struct pad_conf_entry core_padconf_array_delta_sec4_sr[] = {
    	//{MMC1_SDWP, (M14 | PIN_INPUT | SLEWCONTROL)},	/* mmc1_sdwp.gpio6_28 */
    
    };
    
    
    const struct pad_conf_entry early_padconf[] = {
    	{UART2_CTSN, (M2 | PIN_INPUT_PULLUP)},	/* uart2_ctsn.uart3_rxd */
    	{UART2_RTSN, (M1 | PIN_OUTPUT)},	/* uart2_rtsn.uart3_txd */
    	{I2C1_SDA, (PIN_INPUT_PULLUP | M0)},	/* C21.I2C1_SDA */
    	{I2C1_SCL, (PIN_INPUT_PULLUP | M0)},	/* C20.I2C1_SCL */
    };
    
    #endif /* _MUX_DATA_BEAGLE_X15_H_ */

  • See the "no dt node" messages. Since the kernel booted now you can start to put back the nodes you removed. Please, also see this thread.

  • Hello Thank you for your support, Kemal.

    >> See the "no dt node" messages. Since the kernel booted now you can start to put back the nodes you removed. Please, also see this thread.

    The first "no dt node" message I have shot it.Trough adding the following lines in my DTS main structure "/ { ... } " :

    	ocp {
    		sdma: dma-controller@4a056000 {
    			ti,hwmods = "dma_system";
    		};
    	};

    But I get problems with the node GPU because the AM5726 don't has a GPU. And on other dts Files for boards they have a AM5728 processor I cannot see there is a GPU node exists.

    As next, a little Overview of Error and "dt-node" messages:

    [    0.731631] omap_hwmod: l3_main_2 using broken dt data from ocp
    [    0.756415] omap_hwmod: dma_system: no dt node
    [    0.994216] omap_hwmod: gpu: no dt node
    [    1.217944] omap_hwmod: hdq1w: no dt node
    [    1.470919] omap_hwmod: smartreflex_core: no dt node
    [    1.697090] omap_hwmod: smartreflex_mpu: no dt node
    [    1.944218] omap_hwmod: vpe: no dt node
    [    2.168163] omap_hwmod: vip1: no dt node
    [    2.398932] omap_hwmod: vip2: no dt node
    [    2.622949] omap_hwmod: vip3: no dt node
    [    2.937297]  r5:c09b4c88 r4:00000000
    [    2.937303] Code: e3130080 1a000067 e5943004 e1a00004 (e5942044) 
    [    3.302253] ---[ end trace 000000000000000a ]---
    [    3.302320] Kernel panic - not syncing: Attempted to kill init! exitcode=0x0000000b

    Here you can see the current MLO and Kernel messages:

    U-Boot SPL 2019.01 (Oct 21 2019 - 13:31:27 +0200)
    DRA752-GP ES2.0
    Trying to boot from MMC1
    no pinctrl state for default mode
    no pinctrl state for default mode
    Loading Environment from FAT... *** Warning - bad CRC, using default environment
    
    Loading Environment from MMC... Card did not respond to voltage select!
    *** Warning - No block device, using default environment
    
    
    
    U-Boot 2019.01 (Oct 21 2019 - 13:31:27 +0200)
    
    CPU  : DRA752-GP ES2.0
    Model: TI AM5726 sec4
    Board: SEC4 
    DRAM:  1 GiB
    Size of DRAM is 1024 MB
    
    beagle_x
    MMC:   OMAP SD/MMC: 0
    Loading Environment from FAT... *** Warning - bad CRC, using default environment
    
    Loading Environment from MMC... MMC Device 1 not found
    *** Warning - No MMC card found, using default environment
    
     *** -> This Board is unknown
    
    late init
    
    late init 2a
    
    invalid mmc device
    late init 2b
    
    end of late init
    
    Net:   No ethernet found.
    Hit any key to stop autoboot:  0 
    => 
    => 
    => 
    => setenv bootargs console=ttyS2,115200 earlyprintk loglevel=3 mem=0x40000000 loglevel=7
    => load mmc 0:1 0x88000000 sec4.dtb
    128132 bytes read in 8 ms (15.3 MiB/s)
    => load mmc 0:1 0x82000000 zImage
    4203008 bytes read in 188 ms (21.3 MiB/s)
    => bootz 0x82000000 - 0x88000000
    ## Flattened Device Tree blob at 88000000
       Booting using the fdt blob at 0x88000000
       Loading Device Tree to 8ffdd000, end 8ffff483 ... OK
    
    Starting kernel ...
    
    [    0.000000] Booting Linux on physical CPU 0x0
    [    0.000000] Linux version 4.19.38-rt19 (rene@ubuntu) (gcc version 8.3.0 (GNU Toolchain for the A-profile Architecture 8.3-2019.03 (arm-rel-8.36))9
    [    0.000000] CPU: ARMv7 Processor [412fc0f2] revision 2 (ARMv7), cr=30c5387d
    [    0.000000] CPU: div instructions available: patching division code
    [    0.000000] CPU: PIPT / VIPT nonaliasing data cache, PIPT instruction cache
    [    0.000000] OF: fdt: Machine model: TI AM5726 sec4
    [    0.000000] bootconsole [earlycon0] enabled
    [    0.000000] Memory policy: Data cache writealloc
    [    0.000000] efi: Getting EFI parameters from FDT:
    [    0.000000] efi: UEFI not found.
    [    0.000000] cma: Reserved 24 MiB at 0x00000000be400000
    [    0.000000] OMAP4: Map 0x00000000bfd00000 to (ptrval) for dram barrier
    [    0.000000] DRA752 ES2.0
    [    0.000000] random: get_random_bytes called from start_kernel+0xb0/0x480 with crng_init=0
    [    0.000000] percpu: Embedded 15 pages/cpu s32288 r8192 d20960 u61440
    [    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 259648
    [    0.000000] Kernel command line: console=ttyS2,115200 earlyprintk loglevel=3 mem=0x40000000 loglevel=7
    [    0.000000] Dentry cache hash table entries: 131072 (order: 8, 1048576 bytes)
    [    0.000000] Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
    [    0.000000] Memory: 994888K/1045504K available (8192K kernel code, 329K rwdata, 2644K rodata, 2048K init, 275K bss, 26040K reserved, 24576K cma-r)
    [    0.000000] Virtual kernel memory layout:
    [    0.000000]     vector  : 0xffff0000 - 0xffff1000   (   4 kB)
    [    0.000000]     fixmap  : 0xffc00000 - 0xfff00000   (3072 kB)
    [    0.000000]     vmalloc : 0xf0800000 - 0xff800000   ( 240 MB)
    [    0.000000]     lowmem  : 0xc0000000 - 0xf0000000   ( 768 MB)
    [    0.000000]     pkmap   : 0xbfe00000 - 0xc0000000   (   2 MB)
    [    0.000000]     modules : 0xbf000000 - 0xbfe00000   (  14 MB)
    [    0.000000]       .text : 0x(ptrval) - 0x(ptrval)   (10208 kB)
    [    0.000000]       .init : 0x(ptrval) - 0x(ptrval)   (2048 kB)
    [    0.000000]       .data : 0x(ptrval) - 0x(ptrval)   ( 330 kB)
    [    0.000000]        .bss : 0x(ptrval) - 0x(ptrval)   ( 276 kB)
    [    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1
    [    0.000000] rcu: Preemptible hierarchical RCU implementation.
    [    0.000000] rcu:     RCU priority boosting: priority 1 delay 500 ms.
    [    0.000000]  No expedited grace period (rcu_normal_after_boot).
    [    0.000000]  Tasks RCU enabled.
    [    0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
    [    0.000000] GIC: Using split EOI/Deactivate mode
    [    0.000000] ti_dt_clocks_register: missing clkctrl nodes, please update your dts.
    [    0.000000] OMAP clockevent source: timer1 at 32786 Hz
    [    0.000000] arch_timer: cp15 timer(s) running at 6.14MHz (phys).
    [    0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x16af5adb9, max_idle_ns: 440795202250 ns
    [    0.000004] sched_clock: 56 bits at 6MHz, resolution 162ns, wraps every 4398046511023ns
    [    0.000011] Switching to timer-based delay loop, resolution 162ns
    [    0.000326] clocksource: 32k_counter: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 58327039986419 ns
    [    0.000329] OMAP clocksource: 32k_counter at 32768 Hz
    [    0.000727] Console: colour dummy device 80x30
    [    0.259619] Calibrating delay loop (skipped), value calculated using timer frequency.. 12.29 BogoMIPS (lpj=61475)
    [    0.259628] pid_max: default: 32768 minimum: 301
    [    0.259762] Mount-cache hash table entries: 2048 (order: 1, 8192 bytes)
    [    0.259771] Mountpoint-cache hash table entries: 2048 (order: 1, 8192 bytes)
    [    0.260511] CPU: Testing write buffer coherency: ok
    [    0.260540] CPU0: Spectre v2: using ICIALLU workaround
    [    0.260781] /cpus/cpu@0 missing clock-frequency property
    [    0.305725] /cpus/cpu@1 missing clock-frequency property
    [    0.311175] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
    [    0.370182] Setting up static identity map for 0x80200000 - 0x80200060
    [    0.390159] rcu: Hierarchical SRCU implementation.
    [    0.450674] EFI services will not be available.
    [    0.470296] smp: Bringing up secondary CPUs ...
    [    0.590710] CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
    [    0.590714] CPU1: Spectre v2: using ICIALLU workaround
    [    0.590844] smp: Brought up 1 node, 2 CPUs
    [    0.606125] SMP: Total of 2 processors activated (24.59 BogoMIPS).
    [    0.612472] CPU: All CPU(s) started in HYP mode.
    [    0.617206] CPU: Virtualization extensions available.
    [    0.623043] devtmpfs: initialized
    [    0.658118] VFP support v0.3: implementor 41 architecture 4 part 30 variant f rev 0
    [    0.666309] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
    [    0.676424] futex hash table entries: 512 (order: 3, 32768 bytes)
    [    0.683233] pinctrl core: initialized pinctrl subsystem
    [    0.689410] DMI not present or invalid.
    [    0.693801] NET: Registered protocol family 16
    [    0.701107] DMA: preallocated 256 KiB pool for atomic coherent allocations
    [    0.709054] omap_hwmod: l3_main_2 using broken dt data from ocp
    [    0.748598] omap_hwmod: gpu: no dt node
    [    0.752535] ------------[ cut here ]------------
    [    0.757285] WARNING: CPU: 0 PID: 1 at arch/arm/mach-omap2/omap_hwmod.c:2409 _init.constprop.22+0x1b0/0x4dc
    [    0.767183] omap_hwmod: gpu: doesn't have mpu register target base
    [    0.773522] Modules linked in:
    [    0.776663] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.19.38-rt19 #1
    [    0.776666] Hardware name: Generic DRA74X (Flattened Device Tree)
    [    0.776669] Backtrace: 
    [    0.776683] [<c020c748>] (dump_backtrace) from [<c020ca80>] (show_stack+0x18/0x1c)
    [    0.776689]  r7:c0bb657c r6:60000013 r5:00000000 r4:c10505a4
    [    0.776700] [<c020ca68>] (show_stack) from [<c09a0684>] (dump_stack+0x90/0xa4)
    [    0.776707] [<c09a05f4>] (dump_stack) from [<c022d1a0>] (__warn+0xdc/0xf8)
    [    0.776713]  r7:c0bb657c r6:00000009 r5:00000000 r4:ef09dddc
    [    0.776719] [<c022d0c4>] (__warn) from [<c022cdbc>] (warn_slowpath_fmt+0x50/0x6c)
    [    0.776724]  r9:c0e48824 r8:00000000 r7:c101427c r6:00000000 r5:c0bb6b64 r4:c1007488
    [    0.776732] [<c022cd70>] (warn_slowpath_fmt) from [<c0e0cad0>] (_init.constprop.22+0x1b0/0x4dc)
    [    0.776736]  r3:c0bb8c00 r2:c0bb6b64
    [    0.776739]  r5:00000000 r4:c1014244
    [    0.776749] [<c0e0c920>] (_init.constprop.22) from [<c0e0cf2c>] (__omap_hwmod_setup_all+0x48/0x134)
    [    0.776754]  r10:c0e58320 r9:c0e48824 r8:00000000 r7:c0e0cee4 r6:ffffe000 r5:c100c728
    [    0.776757]  r4:c1014244
    [    0.776766] [<c0e0cee4>] (__omap_hwmod_setup_all) from [<c02023fc>] (do_one_initcall+0x84/0x1b0)
    [    0.776769]  r5:c1007488 r4:c10525c0
    [    0.776776] [<c0202378>] (do_one_initcall) from [<c0e01048>] (kernel_init_freeable+0x214/0x2a8)
    [    0.776781]  r8:c0e48844 r7:c0e004f0 r6:c10525c0 r5:c10525c0 r4:00000003
    [    0.776790] [<c0e00e34>] (kernel_init_freeable) from [<c09b4c98>] (kernel_init+0x10/0x118)
    [    0.776795]  r10:00000000 r9:00000000 r8:00000000 r7:00000000 r6:00000000 r5:c09b4c88
    [    0.776797]  r4:00000000
    [    0.776805] [<c09b4c88>] (kernel_init) from [<c02010e0>] (ret_from_fork+0x14/0x34)
    [    0.776808] Exception stack(0xef09dfb0 to 0xef09dff8)
    [    0.776813] dfa0:                                     00000000 00000000 00000000 00000000
    [    0.776818] dfc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
    [    0.776822] dfe0: 00000000 00000000 00000000 00000000 00000013 00000000
    [    0.776826]  r5:c09b4c88 r4:00000000
    [    0.776828] ---[ end trace 0000000000000001 ]---
    [    0.971056] omap_hwmod: hdq1w: no dt node
    [    0.975166] ------------[ cut here ]------------
    [    0.979905] WARNING: CPU: 0 PID: 1 at arch/arm/mach-omap2/omap_hwmod.c:2409 _init.constprop.22+0x1b0/0x4dc
    [    0.989802] omap_hwmod: hdq1w: doesn't have mpu register target base
    [    0.996315] Modules linked in:
    [    0.999461] CPU: 0 PID: 1 Comm: swapper/0 Tainted: G        W         4.19.38-rt19 #1
    [    0.999464] Hardware name: Generic DRA74X (Flattened Device Tree)
    [    0.999466] Backtrace: 
    [    0.999476] [<c020c748>] (dump_backtrace) from [<c020ca80>] (show_stack+0x18/0x1c)
    [    0.999481]  r7:c0bb657c r6:60000013 r5:00000000 r4:c10505a4
    [    0.999489] [<c020ca68>] (show_stack) from [<c09a0684>] (dump_stack+0x90/0xa4)
    [    0.999495] [<c09a05f4>] (dump_stack) from [<c022d1a0>] (__warn+0xdc/0xf8)
    [    0.999500]  r7:c0bb657c r6:00000009 r5:00000000 r4:ef09dddc
    [    0.999505] [<c022d0c4>] (__warn) from [<c022cdbc>] (warn_slowpath_fmt+0x50/0x6c)
    [    0.999511]  r9:c0e48824 r8:00000000 r7:c10141c0 r6:00000000 r5:c0bb6b64 r4:c1007488
    [    0.999519] [<c022cd70>] (warn_slowpath_fmt) from [<c0e0cad0>] (_init.constprop.22+0x1b0/0x4dc)
    [    0.999522]  r3:c0bb8be8 r2:c0bb6b64
    [    0.999525]  r5:00000000 r4:c1014188
    [    0.999534] [<c0e0c920>] (_init.constprop.22) from [<c0e0cf2c>] (__omap_hwmod_setup_all+0x48/0x134)
    [    0.999539]  r10:c0e58320 r9:c0e48824 r8:00000000 r7:c0e0cee4 r6:ffffe000 r5:c100c728
    [    0.999541]  r4:c1014188
    [    0.999550] [<c0e0cee4>] (__omap_hwmod_setup_all) from [<c02023fc>] (do_one_initcall+0x84/0x1b0)
    [    0.999553]  r5:c1007488 r4:c10525c0
    [    0.999559] [<c0202378>] (do_one_initcall) from [<c0e01048>] (kernel_init_freeable+0x214/0x2a8)
    [    0.999564]  r8:c0e48844 r7:c0e004f0 r6:c10525c0 r5:c10525c0 r4:00000003
    [    0.999572] [<c0e00e34>] (kernel_init_freeable) from [<c09b4c98>] (kernel_init+0x10/0x118)
    [    0.999577]  r10:00000000 r9:00000000 r8:00000000 r7:00000000 r6:00000000 r5:c09b4c88
    [    0.999579]  r4:00000000
    [    0.999586] [<c09b4c88>] (kernel_init) from [<c02010e0>] (ret_from_fork+0x14/0x34)
    [    0.999590] Exception stack(0xef09dfb0 to 0xef09dff8)
    [    0.999594] dfa0:                                     00000000 00000000 00000000 00000000
    [    0.999598] dfc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
    [    0.999602] dfe0: 00000000 00000000 00000000 00000000 00000013 00000000
    [    0.999606]  r5:c09b4c88 r4:00000000
    [    0.999609] ---[ end trace 0000000000000002 ]---
    [    1.223820] omap_hwmod: smartreflex_core: no dt node
    [    1.228910] ------------[ cut here ]------------
    [    1.233655] WARNING: CPU: 0 PID: 1 at arch/arm/mach-omap2/omap_hwmod.c:2409 _init.constprop.22+0x1b0/0x4dc
    [    1.243557] omap_hwmod: smartreflex_core: doesn't have mpu register target base
    [    1.251048] Modules linked in:
    [    1.254192] CPU: 0 PID: 1 Comm: swapper/0 Tainted: G        W         4.19.38-rt19 #1
    [    1.254195] Hardware name: Generic DRA74X (Flattened Device Tree)
    [    1.254197] Backtrace: 
    [    1.254207] [<c020c748>] (dump_backtrace) from [<c020ca80>] (show_stack+0x18/0x1c)
    [    1.254213]  r7:c0bb657c r6:60000013 r5:00000000 r4:c10505a4
    [    1.254221] [<c020ca68>] (show_stack) from [<c09a0684>] (dump_stack+0x90/0xa4)
    [    1.254228] [<c09a05f4>] (dump_stack) from [<c022d1a0>] (__warn+0xdc/0xf8)
    [    1.254233]  r7:c0bb657c r6:00000009 r5:00000000 r4:ef09dddc
    [    1.254238] [<c022d0c4>] (__warn) from [<c022cdbc>] (warn_slowpath_fmt+0x50/0x6c)
    [    1.254244]  r9:c0e48824 r8:00000000 r7:c10122a4 r6:00000000 r5:c0bb6b64 r4:c1007488
    [    1.254252] [<c022cd70>] (warn_slowpath_fmt) from [<c0e0cad0>] (_init.constprop.22+0x1b0/0x4dc)
    [    1.254255]  r3:c0bb8734 r2:c0bb6b64
    [    1.254258]  r5:00000000 r4:c101226c
    [    1.254267] [<c0e0c920>] (_init.constprop.22) from [<c0e0cf2c>] (__omap_hwmod_setup_all+0x48/0x134)
    [    1.254273]  r10:c0e58320 r9:c0e48824 r8:00000000 r7:c0e0cee4 r6:ffffe000 r5:c100c728
    [    1.254275]  r4:c101226c
    [    1.254283] [<c0e0cee4>] (__omap_hwmod_setup_all) from [<c02023fc>] (do_one_initcall+0x84/0x1b0)
    [    1.254287]  r5:c1007488 r4:c10525c0
    [    1.254293] [<c0202378>] (do_one_initcall) from [<c0e01048>] (kernel_init_freeable+0x214/0x2a8)
    [    1.254298]  r8:c0e48844 r7:c0e004f0 r6:c10525c0 r5:c10525c0 r4:00000003
    [    1.254305] [<c0e00e34>] (kernel_init_freeable) from [<c09b4c98>] (kernel_init+0x10/0x118)
    [    1.254310]  r10:00000000 r9:00000000 r8:00000000 r7:00000000 r6:00000000 r5:c09b4c88
    [    1.254313]  r4:00000000
    [    1.254320] [<c09b4c88>] (kernel_init) from [<c02010e0>] (ret_from_fork+0x14/0x34)
    [    1.254323] Exception stack(0xef09dfb0 to 0xef09dff8)
    [    1.254327] dfa0:                                     00000000 00000000 00000000 00000000
    [    1.254332] dfc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
    [    1.254336] dfe0: 00000000 00000000 00000000 00000000 00000013 00000000
    [    1.254339]  r5:c09b4c88 r4:00000000
    [    1.254342] ---[ end trace 0000000000000003 ]---
    [    1.449960] omap_hwmod: smartreflex_mpu: no dt node
    [    1.454971] ------------[ cut here ]------------
    [    1.459710] WARNING: CPU: 0 PID: 1 at arch/arm/mach-omap2/omap_hwmod.c:2409 _init.constprop.22+0x1b0/0x4dc
    [    1.469611] omap_hwmod: smartreflex_mpu: doesn't have mpu register target base
    [    1.477036] Modules linked in:
    [    1.480174] CPU: 0 PID: 1 Comm: swapper/0 Tainted: G        W         4.19.38-rt19 #1
    [    1.480177] Hardware name: Generic DRA74X (Flattened Device Tree)
    [    1.480179] Backtrace: 
    [    1.480189] [<c020c748>] (dump_backtrace) from [<c020ca80>] (show_stack+0x18/0x1c)
    [    1.480194]  r7:c0bb657c r6:60000013 r5:00000000 r4:c10505a4
    [    1.480202] [<c020ca68>] (show_stack) from [<c09a0684>] (dump_stack+0x90/0xa4)
    [    1.480208] [<c09a05f4>] (dump_stack) from [<c022d1a0>] (__warn+0xdc/0xf8)
    [    1.480213]  r7:c0bb657c r6:00000009 r5:00000000 r4:ef09dddc
    [    1.480218] [<c022d0c4>] (__warn) from [<c022cdbc>] (warn_slowpath_fmt+0x50/0x6c)
    [    1.480223]  r9:c0e48824 r8:00000000 r7:c101221c r6:00000000 r5:c0bb6b64 r4:c1007488
    [    1.480231] [<c022cd70>] (warn_slowpath_fmt) from [<c0e0cad0>] (_init.constprop.22+0x1b0/0x4dc)
    [    1.480234]  r3:c0bb8724 r2:c0bb6b64
    [    1.480237]  r5:00000000 r4:c10121e4
    [    1.480246] [<c0e0c920>] (_init.constprop.22) from [<c0e0cf2c>] (__omap_hwmod_setup_all+0x48/0x134)
    [    1.480252]  r10:c0e58320 r9:c0e48824 r8:00000000 r7:c0e0cee4 r6:ffffe000 r5:c100c728
    [    1.480254]  r4:c10121e4
    [    1.480262] [<c0e0cee4>] (__omap_hwmod_setup_all) from [<c02023fc>] (do_one_initcall+0x84/0x1b0)
    [    1.480265]  r5:c1007488 r4:c10525c0
    [    1.480271] [<c0202378>] (do_one_initcall) from [<c0e01048>] (kernel_init_freeable+0x214/0x2a8)
    [    1.480276]  r8:c0e48844 r7:c0e004f0 r6:c10525c0 r5:c10525c0 r4:00000003
    [    1.480283] [<c0e00e34>] (kernel_init_freeable) from [<c09b4c98>] (kernel_init+0x10/0x118)
    [    1.480288]  r10:00000000 r9:00000000 r8:00000000 r7:00000000 r6:00000000 r5:c09b4c88
    [    1.480291]  r4:00000000
    [    1.480297] [<c09b4c88>] (kernel_init) from [<c02010e0>] (ret_from_fork+0x14/0x34)
    [    1.480301] Exception stack(0xef09dfb0 to 0xef09dff8)
    [    1.480305] dfa0:                                     00000000 00000000 00000000 00000000
    [    1.480310] dfc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
    [    1.480314] dfe0: 00000000 00000000 00000000 00000000 00000013 00000000
    [    1.480318]  r5:c09b4c88 r4:00000000
    [    1.480320] ---[ end trace 0000000000000004 ]---
    [    1.697146] omap_hwmod: vpe: no dt node
    [    1.701079] ------------[ cut here ]------------
    [    1.705846] WARNING: CPU: 0 PID: 1 at arch/arm/mach-omap2/omap_hwmod.c:2409 _init.constprop.22+0x1b0/0x4dc
    [    1.715752] omap_hwmod: vpe: doesn't have mpu register target base
    [    1.722109] Modules linked in:
    [    1.725249] CPU: 0 PID: 1 Comm: swapper/0 Tainted: G        W         4.19.38-rt19 #1
    [    1.725253] Hardware name: Generic DRA74X (Flattened Device Tree)
    [    1.725255] Backtrace: 
    [    1.725265] [<c020c748>] (dump_backtrace) from [<c020ca80>] (show_stack+0x18/0x1c)
    [    1.725270]  r7:c0bb657c r6:60000013 r5:00000000 r4:c10505a4
    [    1.725278] [<c020ca68>] (show_stack) from [<c09a0684>] (dump_stack+0x90/0xa4)
    [    1.725284] [<c09a05f4>] (dump_stack) from [<c022d1a0>] (__warn+0xdc/0xf8)
    [    1.725290]  r7:c0bb657c r6:00000009 r5:00000000 r4:ef09dddc
    [    1.725295] [<c022d0c4>] (__warn) from [<c022cdbc>] (warn_slowpath_fmt+0x50/0x6c)
    [    1.725301]  r9:c0e48824 r8:00000000 r7:c1015a6c r6:00000000 r5:c0bb6b64 r4:c1007488
    [    1.725309] [<c022cd70>] (warn_slowpath_fmt) from [<c0e0cad0>] (_init.constprop.22+0x1b0/0x4dc)
    [    1.725312]  r3:c0bb8e90 r2:c0bb6b64
    [    1.725315]  r5:00000000 r4:c1015a34
    [    1.725324] [<c0e0c920>] (_init.constprop.22) from [<c0e0cf2c>] (__omap_hwmod_setup_all+0x48/0x134)
    [    1.725330]  r10:c0e58320 r9:c0e48824 r8:00000000 r7:c0e0cee4 r6:ffffe000 r5:c100c728
    [    1.725332]  r4:c1015a34
    [    1.725340] [<c0e0cee4>] (__omap_hwmod_setup_all) from [<c02023fc>] (do_one_initcall+0x84/0x1b0)
    [    1.725343]  r5:c1007488 r4:c10525c0
    [    1.725349] [<c0202378>] (do_one_initcall) from [<c0e01048>] (kernel_init_freeable+0x214/0x2a8)
    [    1.725354]  r8:c0e48844 r7:c0e004f0 r6:c10525c0 r5:c10525c0 r4:00000003
    [    1.725362] [<c0e00e34>] (kernel_init_freeable) from [<c09b4c98>] (kernel_init+0x10/0x118)
    [    1.725367]  r10:00000000 r9:00000000 r8:00000000 r7:00000000 r6:00000000 r5:c09b4c88
    [    1.725369]  r4:00000000
    [    1.725376] [<c09b4c88>] (kernel_init) from [<c02010e0>] (ret_from_fork+0x14/0x34)
    [    1.725379] Exception stack(0xef09dfb0 to 0xef09dff8)
    [    1.725384] dfa0:                                     00000000 00000000 00000000 00000000
    [    1.725388] dfc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
    [    1.725392] dfe0: 00000000 00000000 00000000 00000000 00000013 00000000
    [    1.725396]  r5:c09b4c88 r4:00000000
    [    1.725398] ---[ end trace 0000000000000005 ]---
    [    1.921003] omap_hwmod: vip1: no dt node
    [    1.925026] ------------[ cut here ]------------
    [    1.929766] WARNING: CPU: 0 PID: 1 at arch/arm/mach-omap2/omap_hwmod.c:2409 _init.constprop.22+0x1b0/0x4dc
    [    1.939665] omap_hwmod: vip1: doesn't have mpu register target base
    [    1.946088] Modules linked in:
    [    1.949229] CPU: 0 PID: 1 Comm: swapper/0 Tainted: G        W         4.19.38-rt19 #1
    [    1.949232] Hardware name: Generic DRA74X (Flattened Device Tree)
    [    1.949233] Backtrace: 
    [    1.949245] [<c020c748>] (dump_backtrace) from [<c020ca80>] (show_stack+0x18/0x1c)
    [    1.949250]  r7:c0bb657c r6:60000013 r5:00000000 r4:c10505a4
    [    1.949257] [<c020ca68>] (show_stack) from [<c09a0684>] (dump_stack+0x90/0xa4)
    [    1.949264] [<c09a05f4>] (dump_stack) from [<c022d1a0>] (__warn+0xdc/0xf8)
    [    1.949268]  r7:c0bb657c r6:00000009 r5:00000000 r4:ef09dddc
    [    1.949274] [<c022d0c4>] (__warn) from [<c022cdbc>] (warn_slowpath_fmt+0x50/0x6c)
    [    1.949279]  r9:c0e48824 r8:00000000 r7:c10159b0 r6:00000000 r5:c0bb6b64 r4:c1007488
    [    1.949287] [<c022cd70>] (warn_slowpath_fmt) from [<c0e0cad0>] (_init.constprop.22+0x1b0/0x4dc)
    [    1.949290]  r3:c0bb8e74 r2:c0bb6b64
    [    1.949293]  r5:00000000 r4:c1015978
    [    1.949302] [<c0e0c920>] (_init.constprop.22) from [<c0e0cf2c>] (__omap_hwmod_setup_all+0x48/0x134)
    [    1.949307]  r10:c0e58320 r9:c0e48824 r8:00000000 r7:c0e0cee4 r6:ffffe000 r5:c100c728
    [    1.949309]  r4:c1015978
    [    1.949317] [<c0e0cee4>] (__omap_hwmod_setup_all) from [<c02023fc>] (do_one_initcall+0x84/0x1b0)
    [    1.949321]  r5:c1007488 r4:c10525c0
    [    1.949327] [<c0202378>] (do_one_initcall) from [<c0e01048>] (kernel_init_freeable+0x214/0x2a8)
    [    1.949332]  r8:c0e48844 r7:c0e004f0 r6:c10525c0 r5:c10525c0 r4:00000003
    [    1.949340] [<c0e00e34>] (kernel_init_freeable) from [<c09b4c98>] (kernel_init+0x10/0x118)
    [    1.949345]  r10:00000000 r9:00000000 r8:00000000 r7:00000000 r6:00000000 r5:c09b4c88
    [    1.949347]  r4:00000000
    [    1.949354] [<c09b4c88>] (kernel_init) from [<c02010e0>] (ret_from_fork+0x14/0x34)
    [    1.949357] Exception stack(0xef09dfb0 to 0xef09dff8)
    [    1.949362] dfa0:                                     00000000 00000000 00000000 00000000
    [    1.949366] dfc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
    [    1.949370] dfe0: 00000000 00000000 00000000 00000000 00000013 00000000
    [    1.949374]  r5:c09b4c88 r4:00000000
    [    1.949376] ---[ end trace 0000000000000006 ]---
    [    2.152027] omap_hwmod: vip2: no dt node
    [    2.156080] ------------[ cut here ]------------
    [    2.160820] WARNING: CPU: 0 PID: 1 at arch/arm/mach-omap2/omap_hwmod.c:2409 _init.constprop.22+0x1b0/0x4dc
    [    2.170720] omap_hwmod: vip2: doesn't have mpu register target base
    [    2.177161] Modules linked in:
    [    2.180302] CPU: 0 PID: 1 Comm: swapper/0 Tainted: G        W         4.19.38-rt19 #1
    [    2.180307] Hardware name: Generic DRA74X (Flattened Device Tree)
    [    2.180309] Backtrace: 
    [    2.180319] [<c020c748>] (dump_backtrace) from [<c020ca80>] (show_stack+0x18/0x1c)
    [    2.180324]  r7:c0bb657c r6:60000013 r5:00000000 r4:c10505a4
    [    2.180331] [<c020ca68>] (show_stack) from [<c09a0684>] (dump_stack+0x90/0xa4)
    [    2.180338] [<c09a05f4>] (dump_stack) from [<c022d1a0>] (__warn+0xdc/0xf8)
    [    2.180343]  r7:c0bb657c r6:00000009 r5:00000000 r4:ef09dddc
    [    2.180348] [<c022d0c4>] (__warn) from [<c022cdbc>] (warn_slowpath_fmt+0x50/0x6c)
    [    2.180354]  r9:c0e48824 r8:00000000 r7:c101592c r6:00000000 r5:c0bb6b64 r4:c1007488
    [    2.180362] [<c022cd70>] (warn_slowpath_fmt) from [<c0e0cad0>] (_init.constprop.22+0x1b0/0x4dc)
    [    2.180365]  r3:c0bb8e6c r2:c0bb6b64
    [    2.180368]  r5:00000000 r4:c10158f4
    [    2.180377] [<c0e0c920>] (_init.constprop.22) from [<c0e0cf2c>] (__omap_hwmod_setup_all+0x48/0x134)
    [    2.180382]  r10:c0e58320 r9:c0e48824 r8:00000000 r7:c0e0cee4 r6:ffffe000 r5:c100c728
    [    2.180385]  r4:c10158f4
    [    2.180393] [<c0e0cee4>] (__omap_hwmod_setup_all) from [<c02023fc>] (do_one_initcall+0x84/0x1b0)
    [    2.180396]  r5:c1007488 r4:c10525c0
    [    2.180402] [<c0202378>] (do_one_initcall) from [<c0e01048>] (kernel_init_freeable+0x214/0x2a8)
    [    2.180407]  r8:c0e48844 r7:c0e004f0 r6:c10525c0 r5:c10525c0 r4:00000003
    [    2.180415] [<c0e00e34>] (kernel_init_freeable) from [<c09b4c98>] (kernel_init+0x10/0x118)
    [    2.180420]  r10:00000000 r9:00000000 r8:00000000 r7:00000000 r6:00000000 r5:c09b4c88
    [    2.180422]  r4:00000000
    [    2.180429] [<c09b4c88>] (kernel_init) from [<c02010e0>] (ret_from_fork+0x14/0x34)
    [    2.180432] Exception stack(0xef09dfb0 to 0xef09dff8)
    [    2.180437] dfa0:                                     00000000 00000000 00000000 00000000
    [    2.180442] dfc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
    [    2.180446] dfe0: 00000000 00000000 00000000 00000000 00000013 00000000
    [    2.180449]  r5:c09b4c88 r4:00000000
    [    2.180452] ---[ end trace 0000000000000007 ]---
    [    2.375963] omap_hwmod: vip3: no dt node
    [    2.379984] ------------[ cut here ]------------
    [    2.384724] WARNING: CPU: 0 PID: 1 at arch/arm/mach-omap2/omap_hwmod.c:2409 _init.constprop.22+0x1b0/0x4dc
    [    2.394623] omap_hwmod: vip3: doesn't have mpu register target base
    [    2.401046] Modules linked in:
    [    2.404187] CPU: 0 PID: 1 Comm: swapper/0 Tainted: G        W         4.19.38-rt19 #1
    [    2.404192] Hardware name: Generic DRA74X (Flattened Device Tree)
    [    2.404194] Backtrace: 
    [    2.404203] [<c020c748>] (dump_backtrace) from [<c020ca80>] (show_stack+0x18/0x1c)
    [    2.404209]  r7:c0bb657c r6:60000013 r5:00000000 r4:c10505a4
    [    2.404216] [<c020ca68>] (show_stack) from [<c09a0684>] (dump_stack+0x90/0xa4)
    [    2.404222] [<c09a05f4>] (dump_stack) from [<c022d1a0>] (__warn+0xdc/0xf8)
    [    2.404227]  r7:c0bb657c r6:00000009 r5:00000000 r4:ef09dddc
    [    2.404233] [<c022d0c4>] (__warn) from [<c022cdbc>] (warn_slowpath_fmt+0x50/0x6c)
    [    2.404238]  r9:c0e48824 r8:00000000 r7:c10158a8 r6:00000000 r5:c0bb6b64 r4:c1007488
    [    2.404246] [<c022cd70>] (warn_slowpath_fmt) from [<c0e0cad0>] (_init.constprop.22+0x1b0/0x4dc)
    [    2.404249]  r3:c0bb8e64 r2:c0bb6b64
    [    2.404252]  r5:00000000 r4:c1015870
    [    2.404261] [<c0e0c920>] (_init.constprop.22) from [<c0e0cf2c>] (__omap_hwmod_setup_all+0x48/0x134)
    [    2.404267]  r10:c0e58320 r9:c0e48824 r8:00000000 r7:c0e0cee4 r6:ffffe000 r5:c100c728
    [    2.404269]  r4:c1015870
    [    2.404277] [<c0e0cee4>] (__omap_hwmod_setup_all) from [<c02023fc>] (do_one_initcall+0x84/0x1b0)
    [    2.404280]  r5:c1007488 r4:c10525c0
    [    2.404287] [<c0202378>] (do_one_initcall) from [<c0e01048>] (kernel_init_freeable+0x214/0x2a8)
    [    2.404292]  r8:c0e48844 r7:c0e004f0 r6:c10525c0 r5:c10525c0 r4:00000003
    [    2.404300] [<c0e00e34>] (kernel_init_freeable) from [<c09b4c98>] (kernel_init+0x10/0x118)
    [    2.404305]  r10:00000000 r9:00000000 r8:00000000 r7:00000000 r6:00000000 r5:c09b4c88
    [    2.404307]  r4:00000000
    [    2.404314] [<c09b4c88>] (kernel_init) from [<c02010e0>] (ret_from_fork+0x14/0x34)
    [    2.404317] Exception stack(0xef09dfb0 to 0xef09dff8)
    [    2.404321] dfa0:                                     00000000 00000000 00000000 00000000
    [    2.404326] dfc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
    [    2.404331] dfe0: 00000000 00000000 00000000 00000000 00000013 00000000
    [    2.404335]  r5:c09b4c88 r4:00000000
    [    2.404338] ---[ end trace 0000000000000008 ]---
    [    2.690326] Unhandled fault: asynchronous external abort (0x1211) at 0x00000000
    [    2.690329] pgd = (ptrval)
    [    2.690333] [00000000] *pgd=80000080004003, *pmd=00000000
    [    2.690344] Internal error: : 1211 [#1] PREEMPT SMP ARM
    [    2.690347] Modules linked in:
    [    2.690354] CPU: 0 PID: 1 Comm: swapper/0 Tainted: G        W         4.19.38-rt19 #1
    [    2.690356] Hardware name: Generic DRA74X (Flattened Device Tree)
    [    2.690364] PC is at _enable_sysc+0x5c/0x25c
    [    2.690369] LR is at _enable_sysc+0x48/0x25c
    [    2.690373] pc : [<c021d908>]    lr : [<c021d8f4>]    psr: 40000013
    [    2.690376] sp : ef09de38  ip : ef09de38  fp : ef09de64
    [    2.690379] r10: c0e58320  r9 : c0e48824  r8 : 00000000
    [    2.690382] r7 : c1012900  r6 : 00000000  r5 : c1007488  r4 : c10123e8
    [    2.690386] r3 : c101246c  r2 : c101248c  r1 : 00000078  r0 : c10123e8
    [    2.690390] Flags: nZcv  IRQs on  FIQs on  Mode SVC_32  ISA ARM  Segment user
    [    2.690395] Control: 30c5387d  Table: 80003000  DAC: fffffffd
    [    2.690398] Process swapper/0 (pid: 1, stack limit = 0x(ptrval))
    [    2.690401] Stack: (0xef09de38 to 0xef09e000)
    [    2.690405] de20:                                                       c0224e90 c09b9e08
    [    2.690411] de40: ef09de64 b3a39597 c10123e8 c1052c10 00000000 c1012900 ef09de8c ef09de68
    [    2.690416] de60: c021dc60 c021d8b8 c10123e8 c100ff70 c10123e8 c101240c c1007488 c1012420
    [    2.690421] de80: ef09debc ef09de90 c021e184 c021db14 ef09debc ef09dea0 00000008 b3a39597
    [    2.690426] dea0: c10123e8 c100c728 ffffe000 c0e0cee4 ef09ded4 ef09dec0 c0e0d004 c021dfd0
    [    2.690431] dec0: c10525c0 c1007488 ef09df4c ef09ded8 c02023fc c0e0cef0 00000000 c0bbb460
    [    2.690436] dee0: c0bbb440 c0bbb400 c0bc6a5c c1007488 00000000 c0bbb418 00000002 00000002
    [    2.690441] df00: 00000000 c0bb11e8 c0e004f0 c0c933f0 c1018960 efffcabb efffcac4 b3a39597
    [    2.690446] df20: c027ff88 b3a39597 c10525c0 00000003 c10525c0 c10525c0 c0e004f0 c0e48844
    [    2.690451] df40: ef09df94 ef09df50 c0e01048 c0202384 00000002 00000002 00000000 c0e004f0
    [    2.690456] df60: c0c933f0 000000d1 c09b9e5c 00000000 c09b4c88 00000000 00000000 00000000
    [    2.690460] df80: 00000000 00000000 ef09dfac ef09df98 c09b4c98 c0e00e40 00000000 c09b4c88
    [    2.690465] dfa0: 00000000 ef09dfb0 c02010e0 c09b4c94 00000000 00000000 00000000 00000000
    [    2.690470] dfc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
    [    2.690474] dfe0: 00000000 00000000 00000000 00000000 00000013 00000000 00000000 00000000
    [    2.690476] Backtrace: 
    [    2.690484] [<c021d8ac>] (_enable_sysc) from [<c021dc60>] (_enable+0x158/0x284)
    [    2.690490]  r7:c1012900 r6:00000000 r5:c1052c10 r4:c10123e8
    [    2.690497] [<c021db08>] (_enable) from [<c021e184>] (_setup.part.16+0x1c0/0x4e0)
    [    2.690501]  r7:c1012420 r6:c1007488 r5:c101240c r4:c10123e8
    [    2.690510] [<c021dfc4>] (_setup.part.16) from [<c0e0d004>] (__omap_hwmod_setup_all+0x120/0x134)
    [    2.690514]  r7:c0e0cee4 r6:ffffe000 r5:c100c728 r4:c10123e8
    [    2.690522] [<c0e0cee4>] (__omap_hwmod_setup_all) from [<c02023fc>] (do_one_initcall+0x84/0x1b0)
    [    2.690526]  r5:c1007488 r4:c10525c0
    [    2.690532] [<c0202378>] (do_one_initcall) from [<c0e01048>] (kernel_init_freeable+0x214/0x2a8)
    [    2.690537]  r8:c0e48844 r7:c0e004f0 r6:c10525c0 r5:c10525c0 r4:00000003
    [    2.690545] [<c0e00e34>] (kernel_init_freeable) from [<c09b4c98>] (kernel_init+0x10/0x118)
    [    2.690551]  r10:00000000 r9:00000000 r8:00000000 r7:00000000 r6:00000000 r5:c09b4c88
    [    2.690553]  r4:00000000
    [    2.690560] [<c09b4c88>] (kernel_init) from [<c02010e0>] (ret_from_fork+0x14/0x34)
    [    2.690563] Exception stack(0xef09dfb0 to 0xef09dff8)
    [    2.690567] dfa0:                                     00000000 00000000 00000000 00000000
    [    2.690572] dfc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
    [    2.690576] dfe0: 00000000 00000000 00000000 00000000 00000013 00000000
    [    2.690580]  r5:c09b4c88 r4:00000000
    [    2.690586] Code: e3130080 1a000067 e5943004 e1a00004 (e5942044) 
    [    3.055548] ---[ end trace 0000000000000009 ]---
    [    3.055615] Kernel panic - not syncing: Attempted to kill init! exitcode=0x0000000b
    [    3.055615] 
    [    3.055625] CPU1: stopping
    [    3.055631] CPU: 1 PID: 0 Comm: swapper/1 Tainted: G      D W         4.19.38-rt19 #1
    [    3.055633] Hardware name: Generic DRA74X (Flattened Device Tree)
    [    3.055635] Backtrace: 
    [    3.055647] [<c020c748>] (dump_backtrace) from [<c020ca80>] (show_stack+0x18/0x1c)
    [    3.055653]  r7:fa212000 r6:60000193 r5:00000000 r4:c10505a4
    [    3.055661] [<c020ca68>] (show_stack) from [<c09a0684>] (dump_stack+0x90/0xa4)
    [    3.055669] [<c09a05f4>] (dump_stack) from [<c020f1b8>] (handle_IPI+0x1bc/0x22c)
    [    3.055675]  r7:fa212000 r6:00000001 r5:00000000 r4:c1052840
    [    3.055685] [<c020effc>] (handle_IPI) from [<c05522a0>] (gic_handle_irq+0x94/0x98)
    [    3.055689]  r6:fa21200c r5:c102707c r4:c100796c
    [    3.055696] [<c055220c>] (gic_handle_irq) from [<c02019f8>] (__irq_svc+0x58/0xa0)
    [    3.055699] Exception stack(0xef0e3f28 to 0xef0e3f70)
    [    3.055705] 3f20:                   00000000 0000070c 00000000 c021a140 ffffe000 c10074bc
    [    3.055710] 3f40: c1007504 00000002 00000001 c10521d6 c0bbbc84 ef0e3f84 ef0e3f88 ef0e3f78
    [    3.055714] 3f60: c0208bf8 c0208bfc 60000113 ffffffff
    [    3.055720]  r9:ef0e2000 r8:00000001 r7:ef0e3f5c r6:ffffffff r5:60000113 r4:c0208bfc
    [    3.055730] [<c0208bbc>] (arch_cpu_idle) from [<c09b9870>] (default_idle_call+0x34/0x40)
    [    3.055739] [<c09b983c>] (default_idle_call) from [<c025b928>] (do_idle+0x110/0x180)
    [    3.055746] [<c025b818>] (do_idle) from [<c025bc84>] (cpu_startup_entry+0x20/0x24)
    [    3.055752]  r10:00000000 r9:412fc0f2 r8:80007000 r7:c1052848 r6:00000001 r5:ef0e2000
    [    3.055754]  r4:00000086 r3:ef0e2000
    [    3.055762] [<c025bc64>] (cpu_startup_entry) from [<c020ed54>] (secondary_start_kernel+0x178/0x180)
    [    3.055768] [<c020ebdc>] (secondary_start_kernel) from [<8020210c>] (0x8020210c)
    [    3.055773]  r7:c1052848 r6:30c0387d r5:00000000 r4:af05e880
    

  • The GPU node is in <Processor SDK>/board-support/linux-<version>/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi file.

  • >> The GPU node is in <Processor SDK>/board-support/linux-<version>/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi file.

    Oh no .. I think I has to modify the DTS´files in u-boot why I have to use the DTS files in linux too?

    It it possible that I can copy the DTS from u-boot to the kernel?

     

    I use now the dtb from kernel:

     

    The output message there are now:

    U-Boot SPL 2019.01 (Oct 21 2019 - 13:31:27 +0200)
    DRA752-GP ES2.0
    Trying to boot from MMC1
    no pinctrl state for default mode
    Loading Environment from FAT... *** Warning - bad CRC, using default environment
    
    Loading Environment from MMC... Card did not respond to voltage select!
    *** Warning - No block device, using default environment
    
    
    
    U-Boot 2019.01 (Oct 21 2019 - 13:31:27 +0200)
    
    CPU  : DRA752-GP ES2.0
    Model: TI AM5726 sec4
    Board: SEC4 
    DRAM:  1 GiB
    Size of DRAM is 1024 MB
    
    beagle_x
    MMC:   OMAP SD/MMC: 0
    Loading Environment from FAT... *** Warning - bad CRC, using default environment
    
    Loading Environment from MMC... MMC Device 1 not found
    *** Warning - No MMC card found, using default environment
    
     *** -> This Board is unknown
    
    late init
    
    late init 2a
    
    invalid mmc device
    late init 2b
    
    end of late init
    
    Net:   No ethernet found.
    Hit any key to stop autoboot:  0 
    => setenv bootargs console=ttyS2,115200 earlyprintk loglevel=3 mem=0x40000000 loglevel=7
    => load mmc 0:1 0x88000000 sec4.dtb
    90426 bytes read in 6 ms (14.4 MiB/s)
    => load mmc 0:1 0x82000000 zImage
    4203008 bytes read in 188 ms (21.3 MiB/s)
    => bootz 0x82000000 - 0x88000000
    ## Flattened Device Tree blob at 88000000
       Booting using the fdt blob at 0x88000000
       Loading Device Tree to 8ffe6000, end 8ffff139 ... OK
    
    Starting kernel ...
    
    [    0.000000] Booting Linux on physical CPU 0x0
    [    0.000000] Linux version 4.19.38-rt19 (rene@ubuntu) (gcc version 8.3.0 (GNU Toolchain for the A-profile Architecture 8.3-2019.03 (arm-rel-8.36))9
    [    0.000000] CPU: ARMv7 Processor [412fc0f2] revision 2 (ARMv7), cr=30c5387d
    [    0.000000] CPU: div instructions available: patching division code
    [    0.000000] CPU: PIPT / VIPT nonaliasing data cache, PIPT instruction cache
    [    0.000000] OF: fdt: Machine model: TI AM5728 BeagleBoard-X15
    [    0.000000] bootconsole [earlycon0] enabled
    [    0.000000] Memory policy: Data cache writealloc
    [    0.000000] efi: Getting EFI parameters from FDT:
    [    0.000000] efi: UEFI not found.
    [    0.000000] Reserved memory: created CMA memory pool at 0x0000000095800000, size 56 MiB
    [    0.000000] OF: reserved mem: initialized node ipu2-memory@95800000, compatible id shared-dma-pool
    [    0.000000] Reserved memory: created CMA memory pool at 0x0000000099000000, size 64 MiB
    [    0.000000] OF: reserved mem: initialized node dsp1-memory@99000000, compatible id shared-dma-pool
    [    0.000000] Reserved memory: created CMA memory pool at 0x000000009d000000, size 32 MiB
    [    0.000000] OF: reserved mem: initialized node ipu1-memory@9d000000, compatible id shared-dma-pool
    [    0.000000] Reserved memory: created CMA memory pool at 0x000000009f000000, size 8 MiB
    [    0.000000] OF: reserved mem: initialized node dsp2-memory@9f000000, compatible id shared-dma-pool
    [    0.000000] cma: Reserved 24 MiB at 0x00000000be400000
    [    0.000000] OMAP4: Map 0x00000000bfd00000 to (ptrval) for dram barrier
    [    0.000000] DRA752 ES2.0
    [    0.000000] random: get_random_bytes called from start_kernel+0xb0/0x480 with crng_init=0
    [    0.000000] percpu: Embedded 15 pages/cpu s32288 r8192 d20960 u61440
    [    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 210496
    [    0.000000] Kernel command line: console=ttyS2,115200 earlyprintk loglevel=3 mem=0x40000000 loglevel=7
    [    0.000000] Dentry cache hash table entries: 131072 (order: 8, 1048576 bytes)
    [    0.000000] Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
    [    0.000000] Memory: 635908K/848896K available (8192K kernel code, 329K rwdata, 2644K rodata, 2048K init, 275K bss, 24572K reserved, 188416K cma-r)
    [    0.000000] Virtual kernel memory layout:
    [    0.000000]     vector  : 0xffff0000 - 0xffff1000   (   4 kB)
    [    0.000000]     fixmap  : 0xffc00000 - 0xfff00000   (3072 kB)
    [    0.000000]     vmalloc : 0xf0800000 - 0xff800000   ( 240 MB)
    [    0.000000]     lowmem  : 0xc0000000 - 0xf0000000   ( 768 MB)
    [    0.000000]     pkmap   : 0xbfe00000 - 0xc0000000   (   2 MB)
    [    0.000000]     modules : 0xbf000000 - 0xbfe00000   (  14 MB)
    [    0.000000]       .text : 0x(ptrval) - 0x(ptrval)   (10208 kB)
    [    0.000000]       .init : 0x(ptrval) - 0x(ptrval)   (2048 kB)
    [    0.000000]       .data : 0x(ptrval) - 0x(ptrval)   ( 330 kB)
    [    0.000000]        .bss : 0x(ptrval) - 0x(ptrval)   ( 276 kB)
    [    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1
    [    0.000000] rcu: Preemptible hierarchical RCU implementation.
    [    0.000000] rcu:     RCU priority boosting: priority 1 delay 500 ms.
    [    0.000000]  No expedited grace period (rcu_normal_after_boot).
    [    0.000000]  Tasks RCU enabled.
    [    0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
    [    0.000000] GIC: Using split EOI/Deactivate mode
    [    0.000000] OMAP clockevent source: timer1 at 32786 Hz
    [    0.000000] arch_timer: cp15 timer(s) running at 6.14MHz (phys).
    [    0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x16af5adb9, max_idle_ns: 440795202250 ns
    [    0.000005] sched_clock: 56 bits at 6MHz, resolution 162ns, wraps every 4398046511023ns
    [    0.000011] Switching to timer-based delay loop, resolution 162ns
    [    0.000275] clocksource: 32k_counter: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 58327039986419 ns
    [    0.000277] OMAP clocksource: 32k_counter at 32768 Hz
    [    0.000706] Console: colour dummy device 80x30
    [    0.321351] Calibrating delay loop (skipped), value calculated using timer frequency.. 12.29 BogoMIPS (lpj=61475)
    [    0.321359] pid_max: default: 32768 minimum: 301
    [    0.321495] Mount-cache hash table entries: 2048 (order: 1, 8192 bytes)
    [    0.321503] Mountpoint-cache hash table entries: 2048 (order: 1, 8192 bytes)
    [    0.322224] CPU: Testing write buffer coherency: ok
    [    0.322254] CPU0: Spectre v2: using ICIALLU workaround
    [    0.322499] /cpus/cpu@0 missing clock-frequency property
    [    0.367450] /cpus/cpu@1 missing clock-frequency property
    [    0.372904] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
    [    0.430219] Setting up static identity map for 0x80200000 - 0x80200060
    [    0.450192] rcu: Hierarchical SRCU implementation.
    [    0.510710] EFI services will not be available.
    [    0.530327] smp: Bringing up secondary CPUs ...
    [    0.650737] CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
    [    0.650741] CPU1: Spectre v2: using ICIALLU workaround
    [    0.650871] smp: Brought up 1 node, 2 CPUs
    [    0.666153] SMP: Total of 2 processors activated (24.59 BogoMIPS).
    [    0.672500] CPU: All CPU(s) started in HYP mode.
    [    0.677233] CPU: Virtualization extensions available.
    [    0.683060] devtmpfs: initialized
    [    0.715447] VFP support v0.3: implementor 41 architecture 4 part 30 variant f rev 0
    [    0.723634] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
    [    0.733727] futex hash table entries: 512 (order: 3, 32768 bytes)
    [    0.743279] pinctrl core: initialized pinctrl subsystem
    [    0.749477] DMI not present or invalid.
    [    0.753926] NET: Registered protocol family 16
    [    0.761244] DMA: preallocated 256 KiB pool for atomic coherent allocations
    [    0.769203] omap_hwmod: l3_main_2 using broken dt data from ocp
    [    0.902698] omap_hwmod: gpu: _wait_target_ready failed: -16
    [    0.908419] omap_hwmod: gpu: cannot be enabled for reset (3)
    [    0.981441] Unhandled fault: asynchronous external abort (0x1211) at 0x00000000
    [    0.981445] pgd = (ptrval)
    [    0.981449] [00000000] *pgd=80000080004003, *pmd=00000000
    [    0.981460] Internal error: : 1211 [#1] PREEMPT SMP ARM
    [    0.981463] Modules linked in:
    [    0.981471] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.19.38-rt19 #1
    [    0.981474] Hardware name: Generic DRA74X (Flattened Device Tree)
    [    0.981485] PC is at _enable_sysc+0x5c/0x25c
    [    0.981490] LR is at _enable_sysc+0x48/0x25c
    [    0.981494] pc : [<c021d908>]    lr : [<c021d8f4>]    psr: 40000013
    [    0.981497] sp : ef0a1e38  ip : ef0a1e38  fp : ef0a1e64
    [    0.981500] r10: c0e58320  r9 : c0e48824  r8 : 00000000
    [    0.981504] r7 : c1012900  r6 : 00000000  r5 : c1007488  r4 : c10123e8
    [    0.981507] r3 : c101246c  r2 : c101248c  r1 : 00000078  r0 : c10123e8
    [    0.981512] Flags: nZcv  IRQs on  FIQs on  Mode SVC_32  ISA ARM  Segment user
    [    0.981516] Control: 30c5387d  Table: 80003000  DAC: fffffffd
    [    0.981519] Process swapper/0 (pid: 1, stack limit = 0x(ptrval))
    [    0.981523] Stack: (0xef0a1e38 to 0xef0a2000)
    [    0.981528] 1e20:                                                       c0224e90 c09b9e08
    [    0.981533] 1e40: ef0a1e64 b3a39597 c10123e8 c1052c10 00000000 c1012900 ef0a1e8c ef0a1e68
    [    0.981538] 1e60: c021dc60 c021d8b8 c10123e8 c100ff70 c10123e8 c101240c c1007488 c1012420
    [    0.981544] 1e80: ef0a1ebc ef0a1e90 c021e184 c021db14 ef0a1ebc ef0a1ea0 00000008 b3a39597
    [    0.981549] 1ea0: c10123e8 c100c728 ffffe000 c0e0cee4 ef0a1ed4 ef0a1ec0 c0e0d004 c021dfd0
    [    0.981554] 1ec0: c10525c0 c1007488 ef0a1f4c ef0a1ed8 c02023fc c0e0cef0 00000000 c0bbb460
    [    0.981559] 1ee0: c0bbb440 c0bbb400 c0bc6a5c c1007488 00000000 c0bbb418 00000002 00000002
    [    0.981564] 1f00: 00000000 c0bb11e8 c0e004f0 c0c933f0 c1018960 ef66457b ef664584 b3a39597
    [    0.981569] 1f20: c027ff88 b3a39597 c10525c0 00000003 c10525c0 c10525c0 c0e004f0 c0e48844
    [    0.981574] 1f40: ef0a1f94 ef0a1f50 c0e01048 c0202384 00000002 00000002 00000000 c0e004f0
    [    0.981579] 1f60: c0c933f0 000000d1 c09b9e5c 00000000 c09b4c88 00000000 00000000 00000000
    [    0.981584] 1f80: 00000000 00000000 ef0a1fac ef0a1f98 c09b4c98 c0e00e40 00000000 c09b4c88
    [    0.981588] 1fa0: 00000000 ef0a1fb0 c02010e0 c09b4c94 00000000 00000000 00000000 00000000
    [    0.981593] 1fc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
    [    0.981598] 1fe0: 00000000 00000000 00000000 00000000 00000013 00000000 00000000 00000000
    [    0.981599] Backtrace: 
    [    0.981610] [<c021d8ac>] (_enable_sysc) from [<c021dc60>] (_enable+0x158/0x284)
    [    0.981616]  r7:c1012900 r6:00000000 r5:c1052c10 r4:c10123e8
    [    0.981623] [<c021db08>] (_enable) from [<c021e184>] (_setup.part.16+0x1c0/0x4e0)
    [    0.981628]  r7:c1012420 r6:c1007488 r5:c101240c r4:c10123e8
    [    0.981639] [<c021dfc4>] (_setup.part.16) from [<c0e0d004>] (__omap_hwmod_setup_all+0x120/0x134)
    [    0.981644]  r7:c0e0cee4 r6:ffffe000 r5:c100c728 r4:c10123e8
    [    0.981653] [<c0e0cee4>] (__omap_hwmod_setup_all) from [<c02023fc>] (do_one_initcall+0x84/0x1b0)
    [    0.981657]  r5:c1007488 r4:c10525c0
    [    0.981664] [<c0202378>] (do_one_initcall) from [<c0e01048>] (kernel_init_freeable+0x214/0x2a8)
    [    0.981669]  r8:c0e48844 r7:c0e004f0 r6:c10525c0 r5:c10525c0 r4:00000003
    [    0.981679] [<c0e00e34>] (kernel_init_freeable) from [<c09b4c98>] (kernel_init+0x10/0x118)
    [    0.981685]  r10:00000000 r9:00000000 r8:00000000 r7:00000000 r6:00000000 r5:c09b4c88
    [    0.981687]  r4:00000000
    [    0.981695] [<c09b4c88>] (kernel_init) from [<c02010e0>] (ret_from_fork+0x14/0x34)
    [    0.981698] Exception stack(0xef0a1fb0 to 0xef0a1ff8)
    [    0.981702] 1fa0:                                     00000000 00000000 00000000 00000000
    [    0.981707] 1fc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
    [    0.981711] 1fe0: 00000000 00000000 00000000 00000000 00000013 00000000
    [    0.981714]  r5:c09b4c88 r4:00000000
    [    0.981720] Code: e3130080 1a000067 e5943004 e1a00004 (e5942044) 
    [    1.345251] ---[ end trace 0000000000000001 ]---
    [    1.345320] Kernel panic - not syncing: Attempted to kill init! exitcode=0x0000000b
    [    1.345320] 
    [    1.345329] CPU1: stopping
    [    1.345336] CPU: 1 PID: 0 Comm: swapper/1 Tainted: G      D           4.19.38-rt19 #1
    [    1.345338] Hardware name: Generic DRA74X (Flattened Device Tree)
    [    1.345340] Backtrace: 
    [    1.345352] [<c020c748>] (dump_backtrace) from [<c020ca80>] (show_stack+0x18/0x1c)
    [    1.345359]  r7:fa212000 r6:60000193 r5:00000000 r4:c10505a4
    [    1.345370] [<c020ca68>] (show_stack) from [<c09a0684>] (dump_stack+0x90/0xa4)
    [    1.345378] [<c09a05f4>] (dump_stack) from [<c020f1b8>] (handle_IPI+0x1bc/0x22c)
    [    1.345382]  r7:fa212000 r6:00000001 r5:00000000 r4:c1052840
    [    1.345392] [<c020effc>] (handle_IPI) from [<c05522a0>] (gic_handle_irq+0x94/0x98)
    [    1.345396]  r6:fa21200c r5:c102707c r4:c100796c
    [    1.345403] [<c055220c>] (gic_handle_irq) from [<c02019f8>] (__irq_svc+0x58/0xa0)
    [    1.345406] Exception stack(0xef0cff28 to 0xef0cff70)
    [    1.345411] ff20:                   00000000 0000018c 00000000 c021a140 ffffe000 c10074bc
    [    1.345417] ff40: c1007504 00000002 00000001 c10521d6 c0bbbc84 ef0cff84 ef0cff88 ef0cff78
    [    1.345420] ff60: c0208bf8 c0208bfc 60000013 ffffffff
    [    1.345426]  r9:ef0ce000 r8:00000001 r7:ef0cff5c r6:ffffffff r5:60000013 r4:c0208bfc
    [    1.345436] [<c0208bbc>] (arch_cpu_idle) from [<c09b9870>] (default_idle_call+0x34/0x40)
    [    1.345444] [<c09b983c>] (default_idle_call) from [<c025b928>] (do_idle+0x110/0x180)
    [    1.345450] [<c025b818>] (do_idle) from [<c025bc84>] (cpu_startup_entry+0x20/0x24)
    [    1.345456]  r10:00000000 r9:412fc0f2 r8:80007000 r7:c1052848 r6:00000001 r5:ef0ce000
    [    1.345459]  r4:00000086 r3:ef0ce000
    [    1.345467] [<c025bc64>] (cpu_startup_entry) from [<c020ed54>] (secondary_start_kernel+0x178/0x180)
    [    1.345473] [<c020ebdc>] (secondary_start_kernel) from [<8020210c>] (0x8020210c)
    [    1.345477]  r7:c1052848 r6:30c0387d r5:00000000 r4:af0771c0
    

    The arch/arm/boot/dts/am57xx-beagle-x15.dts:

    /*
     * Copyright (C) 2014-2016 Texas Instruments Incorporated - http://www.ti.com/
     *
     * This program is free software; you can redistribute it and/or modify
     * it under the terms of the GNU General Public License version 2 as
     * published by the Free Software Foundation.
     */
    
    #include "am57xx-beagle-x15-common.dtsi"
    
    / {
    	/* NOTE: This describes the "original" pre-production A2 revision */
    	model = "TI AM5728 BeagleBoard-X15";
    };
    
    &mmc1 {
    	pinctrl-names = "default", "hs";
    	pinctrl-0 = <&mmc1_pins_default>;
    	pinctrl-1 = <&mmc1_pins_hs>;
    
    	vmmc-supply = <&ldo1_reg>;
    	no-1-8-v;
    };
    
    &mmc2 {
    	status = "disabled";
    };
    
    &gpu {
    	status = "disabled";
    };
    
    
    &tpd12s015 {
    	status = "disabled";
    };
    
    
    /* errata i880 "Ethernet RGMII2 Limited to 10/100 Mbps" */
    &phy1 {
    	status = "disabled";
    	max-speed = <100>;
    };
    
    #include "am57xx-evm-cmem.dtsi"

    And here are the complete converted dts file from dtb.

    /dts-v1/;
    
    / {
    	#address-cells = <0x2>;
    	#size-cells = <0x2>;
    	compatible = "ti,am572x-beagle-x15", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7";
    	interrupt-parent = <0x1>;
    	model = "TI AM5728 BeagleBoard-X15";
    
    	chosen {
    		stdout-path = "/ocp/serial@48020000";
    	};
    
    	aliases {
    		i2c0 = "/ocp/i2c@48070000";
    		i2c1 = "/ocp/i2c@48072000";
    		i2c2 = "/ocp/i2c@48060000";
    		i2c3 = "/ocp/i2c@4807a000";
    		i2c4 = "/ocp/i2c@4807c000";
    		serial0 = "/ocp/serial@4806a000";
    		serial1 = "/ocp/serial@4806c000";
    		serial2 = "/ocp/serial@48020000";
    		serial3 = "/ocp/serial@4806e000";
    		serial4 = "/ocp/serial@48066000";
    		serial5 = "/ocp/serial@48068000";
    		serial6 = "/ocp/serial@48420000";
    		serial7 = "/ocp/serial@48422000";
    		serial8 = "/ocp/serial@48424000";
    		serial9 = "/ocp/serial@4ae2b000";
    		ethernet0 = "/ocp/ethernet@48484000/slave@48480200";
    		ethernet1 = "/ocp/ethernet@48484000/slave@48480300";
    		d_can0 = "/ocp/can@4ae3c000";
    		d_can1 = "/ocp/can@48480000";
    		spi0 = "/ocp/qspi@4b300000";
    		rproc0 = "/ocp/ipu@58820000";
    		rproc1 = "/ocp/ipu@55020000";
    		rproc2 = "/ocp/dsp@40800000";
    		rproc3 = "/ocp/dsp@41000000";
    		rtc0 = "/ocp/i2c@48060000/rtc@6f";
    		rtc1 = "/ocp/i2c@48070000/tps659038@58/tps659038_rtc";
    		rtc2 = "/ocp/rtc@48838000";
    		display0 = "/connector";
    		sound0 = "/sound0";
    		sound1 = "/ocp/dss@58000000/encoder@58060000";
    	};
    
    	timer {
    		compatible = "arm,armv7-timer";
    		interrupts = <0x1 0xd 0x308 0x1 0xe 0x308 0x1 0xb 0x308 0x1 0xa 0x308>;
    		interrupt-parent = <0x2>;
    	};
    
    	interrupt-controller@48211000 {
    		compatible = "arm,cortex-a15-gic";
    		interrupt-controller;
    		#interrupt-cells = <0x3>;
    		reg = <0x0 0x48211000 0x0 0x1000 0x0 0x48212000 0x0 0x2000 0x0 0x48214000 0x0 0x2000 0x0 0x48216000 0x0 0x2000>;
    		interrupts = <0x1 0x9 0x304>;
    		interrupt-parent = <0x2>;
    		phandle = <0x2>;
    	};
    
    	interrupt-controller@48281000 {
    		compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
    		interrupt-controller;
    		#interrupt-cells = <0x3>;
    		reg = <0x0 0x48281000 0x0 0x1000>;
    		interrupt-parent = <0x2>;
    		phandle = <0x8>;
    	};
    
    	cpus {
    		#address-cells = <0x1>;
    		#size-cells = <0x0>;
    
    		cpu@0 {
    			device_type = "cpu";
    			compatible = "arm,cortex-a15";
    			reg = <0x0>;
    			operating-points-v2 = <0x3>;
    			clocks = <0x4>;
    			clock-names = "cpu";
    			clock-latency = <0x493e0>;
    			#cooling-cells = <0x2>;
    			vbb-supply = <0x5>;
    			vdd-supply = <0x6>;
    			voltage-tolerance = <0x1>;
    			phandle = <0xdb>;
    		};
    
    		cpu@1 {
    			device_type = "cpu";
    			compatible = "arm,cortex-a15";
    			reg = <0x1>;
    			operating-points-v2 = <0x3>;
    			clocks = <0x4>;
    			clock-names = "cpu";
    			clock-latency = <0x493e0>;
    			#cooling-cells = <0x2>;
    			vbb-supply = <0x5>;
    		};
    	};
    
    	opp-table {
    		compatible = "operating-points-v2-ti-cpu";
    		syscon = <0x7>;
    		opp-shared;
    		phandle = <0x3>;
    
    		opp_nom-1000000000 {
    			opp-hz = <0x0 0x3b9aca00>;
    			opp-microvolt = <0x102ca0 0xcf850 0x118c30 0x102ca0 0xcf850 0x118c30>;
    			opp-supported-hw = <0xff 0x1>;
    			opp-suspend;
    		};
    
    		opp_od-1176000000 {
    			opp-hz = <0x0 0x46185600>;
    			opp-microvolt = <0x11b340 0xd8108 0x11b340 0x11b340 0xd8108 0x11b340>;
    			opp-supported-hw = <0xff 0x2>;
    		};
    
    		opp_high@1500000000 {
    			opp-hz = <0x0 0x59682f00>;
    			opp-microvolt = <0x127690 0xe7ef0 0x1312d0 0x127690 0xe7ef0 0x1312d0>;
    			opp-supported-hw = <0xff 0x4>;
    		};
    	};
    
    	soc {
    		compatible = "ti,omap-infra";
    
    		mpu {
    			compatible = "ti,omap5-mpu";
    			ti,hwmods = "mpu";
    		};
    	};
    
    	ocp {
    		compatible = "ti,dra7-l3-noc", "simple-bus";
    		#address-cells = <0x1>;
    		#size-cells = <0x1>;
    		ranges = <0x0 0x0 0x0 0xc0000000>;
    		ti,hwmods = "l3_main_1", "l3_main_2";
    		reg = <0x0 0x44000000 0x0 0x1000000 0x0 0x45000000 0x0 0x1000>;
    		interrupts-extended = <0x1 0x0 0x4 0x4 0x8 0x0 0xa 0x4>;
    
    		l4@4a000000 {
    			compatible = "ti,dra7-l4-cfg", "simple-bus";
    			#address-cells = <0x1>;
    			#size-cells = <0x1>;
    			ranges = <0x0 0x4a000000 0x22c000>;
    
    			scm@2000 {
    				compatible = "ti,dra7-scm-core", "simple-bus";
    				reg = <0x2000 0x2000>;
    				#address-cells = <0x1>;
    				#size-cells = <0x1>;
    				ranges = <0x0 0x2000 0x2000>;
    
    				scm_conf@0 {
    					compatible = "syscon", "simple-bus";
    					reg = <0x0 0x1400>;
    					#address-cells = <0x1>;
    					#size-cells = <0x1>;
    					ranges = <0x0 0x0 0x1400>;
    					phandle = <0x9>;
    
    					pbias_regulator@e00 {
    						compatible = "ti,pbias-dra7", "ti,pbias-omap";
    						reg = <0xe00 0x4>;
    						syscon = <0x9>;
    
    						pbias_mmc_omap5 {
    							regulator-name = "pbias_mmc_omap5";
    							regulator-min-microvolt = <0x1b7740>;
    							regulator-max-microvolt = <0x325aa0>;
    							phandle = <0xad>;
    						};
    					};
    
    					clocks {
    						#address-cells = <0x1>;
    						#size-cells = <0x0>;
    
    						dss_deshdcp_clk@558 {
    							#clock-cells = <0x0>;
    							compatible = "ti,gate-clock";
    							clocks = <0xa>;
    							ti,bit-shift = <0x0>;
    							reg = <0x558>;
    						};
    
    						ehrpwm0_tbclk@558 {
    							#clock-cells = <0x0>;
    							compatible = "ti,gate-clock";
    							clocks = <0xb>;
    							ti,bit-shift = <0x14>;
    							reg = <0x558>;
    							phandle = <0xcf>;
    						};
    
    						ehrpwm1_tbclk@558 {
    							#clock-cells = <0x0>;
    							compatible = "ti,gate-clock";
    							clocks = <0xb>;
    							ti,bit-shift = <0x15>;
    							reg = <0x558>;
    							phandle = <0xd0>;
    						};
    
    						ehrpwm2_tbclk@558 {
    							#clock-cells = <0x0>;
    							compatible = "ti,gate-clock";
    							clocks = <0xb>;
    							ti,bit-shift = <0x16>;
    							reg = <0x558>;
    							phandle = <0xd1>;
    						};
    
    						sys_32k_ck {
    							#clock-cells = <0x0>;
    							compatible = "ti,mux-clock";
    							clocks = <0xc 0xd 0xd 0xd>;
    							ti,bit-shift = <0x8>;
    							reg = <0x6c4>;
    							phandle = <0x50>;
    						};
    					};
    				};
    
    				pinmux@1400 {
    					compatible = "ti,dra7-padconf", "pinctrl-single";
    					reg = <0x1400 0x468>;
    					#address-cells = <0x1>;
    					#size-cells = <0x0>;
    					#pinctrl-cells = <0x1>;
    					#interrupt-cells = <0x1>;
    					interrupt-controller;
    					pinctrl-single,register-width = <0x20>;
    					pinctrl-single,function-mask = <0x3fffffff>;
    					phandle = <0x8e>;
    
    					mmc1_pins_default {
    						pinctrl-single,pins = <0x354 0x60000 0x358 0x60000 0x35c 0x60000 0x360 0x60000 0x364 0x60000 0x368 0x60000>;
    						phandle = <0xae>;
    					};
    
    					mmc1_pins_sdr12 {
    						pinctrl-single,pins = <0x354 0x60000 0x358 0x60000 0x35c 0x60000 0x360 0x60000 0x364 0x60000 0x368 0x60000>;
    					};
    
    					mmc1_pins_hs {
    						pinctrl-single,pins = <0x354 0x601b0 0x358 0x601b0 0x35c 0x601b0 0x360 0x601b0 0x364 0x601b0 0x368 0x601b0>;
    						phandle = <0xb0>;
    					};
    
    					mmc1_pins_sdr25 {
    						pinctrl-single,pins = <0x354 0x601b0 0x358 0x601b0 0x35c 0x601b0 0x360 0x601b0 0x364 0x601b0 0x368 0x601b0>;
    					};
    
    					mmc1_pins_sdr50 {
    						pinctrl-single,pins = <0x354 0x601a0 0x358 0x601a0 0x35c 0x601a0 0x360 0x601a0 0x364 0x601a0 0x368 0x601a0>;
    					};
    
    					mmc1_pins_ddr50 {
    						pinctrl-single,pins = <0x354 0x60100 0x358 0x60100 0x35c 0x60100 0x360 0x60100 0x364 0x60100 0x368 0x60100>;
    					};
    
    					mmc1_pins_sdr104 {
    						pinctrl-single,pins = <0x354 0x60100 0x358 0x60100 0x35c 0x60100 0x360 0x60100 0x364 0x60100 0x368 0x60100>;
    					};
    
    					mmc2_pins_default {
    						pinctrl-single,pins = <0x9c 0x60001 0xb0 0x60001 0xa0 0x60001 0xa4 0x60001 0xa8 0x60001 0xac 0x60001 0x8c 0x60001 0x90 0x60001 0x94 0x60001 0x98 0x60001>;
    						phandle = <0xb2>;
    					};
    
    					mmc2_pins_hs {
    						pinctrl-single,pins = <0x9c 0x60001 0xb0 0x60001 0xa0 0x60001 0xa4 0x60001 0xa8 0x60001 0xac 0x60001 0x8c 0x60001 0x90 0x60001 0x94 0x60001 0x98 0x60001>;
    					};
    
    					mmc2_pins_ddr_3_3v_rev11 {
    						pinctrl-single,pins = <0x9c 0x60101 0xb0 0x60101 0xa0 0x60101 0xa4 0x60101 0xa8 0x60101 0xac 0x60101 0x8c 0x60101 0x90 0x60101 0x94 0x60101 0x98 0x60101>;
    					};
    
    					mmc2_pins_ddr_1_8v_rev11 {
    						pinctrl-single,pins = <0x9c 0x60101 0xb0 0x60101 0xa0 0x60101 0xa4 0x60101 0xa8 0x60101 0xac 0x60101 0x8c 0x60101 0x90 0x60101 0x94 0x60101 0x98 0x60101>;
    					};
    
    					mmc2_pins_ddr_rev20 {
    						pinctrl-single,pins = <0x9c 0x60001 0xb0 0x60001 0xa0 0x60001 0xa4 0x60001 0xa8 0x60001 0xac 0x60001 0x8c 0x60001 0x90 0x60001 0x94 0x60001 0x98 0x60001>;
    					};
    
    					mmc2_pins_hs200 {
    						pinctrl-single,pins = <0x9c 0x60101 0xb0 0x60101 0xa0 0x60101 0xa4 0x60101 0xa8 0x60101 0xac 0x60101 0x8c 0x60101 0x90 0x60101 0x94 0x60101 0x98 0x60101>;
    					};
    
    					mmc4_pins_default {
    						pinctrl-single,pins = <0x3e8 0x60103 0x3ec 0x60103 0x3f0 0x60103 0x3f4 0x60103 0x3f8 0x60103 0x3fc 0x60103>;
    					};
    
    					mmc4_pins_hs {
    						pinctrl-single,pins = <0x3e8 0x60103 0x3ec 0x60103 0x3f0 0x60103 0x3f4 0x60103 0x3f8 0x60103 0x3fc 0x60103>;
    					};
    
    					mmc3_pins_default {
    						pinctrl-single,pins = <0x37c 0x60000 0x380 0x60000 0x384 0x60000 0x388 0x60000 0x38c 0x60000 0x390 0x60000>;
    					};
    
    					mmc3_pins_hs {
    						pinctrl-single,pins = <0x37c 0x60000 0x380 0x60000 0x384 0x60000 0x388 0x60000 0x38c 0x60000 0x390 0x60000>;
    					};
    
    					mmc3_pins_sdr12 {
    						pinctrl-single,pins = <0x37c 0x60000 0x380 0x60000 0x384 0x60000 0x388 0x60000 0x38c 0x60000 0x390 0x60000>;
    					};
    
    					mmc3_pins_sdr25 {
    						pinctrl-single,pins = <0x37c 0x60000 0x380 0x60000 0x384 0x60000 0x388 0x60000 0x38c 0x60000 0x390 0x60000>;
    					};
    
    					mmc3_pins_sdr50 {
    						pinctrl-single,pins = <0x37c 0x60100 0x380 0x60100 0x384 0x60100 0x388 0x60100 0x38c 0x60100 0x390 0x60100>;
    					};
    
    					mmc4_pins_sdr12 {
    						pinctrl-single,pins = <0x3e8 0x60103 0x3ec 0x60103 0x3f0 0x60103 0x3f4 0x60103 0x3f8 0x60103 0x3fc 0x60103>;
    					};
    
    					mmc4_pins_sdr25 {
    						pinctrl-single,pins = <0x3e8 0x60103 0x3ec 0x60103 0x3f0 0x60103 0x3f4 0x60103 0x3f8 0x60103 0x3fc 0x60103>;
    					};
    				};
    
    				scm_conf@1c04 {
    					compatible = "syscon";
    					reg = <0x1c04 0x20>;
    					#syscon-cells = <0x2>;
    					phandle = <0x88>;
    				};
    
    				scm_conf@1c24 {
    					compatible = "syscon";
    					reg = <0x1c24 0x24>;
    					phandle = <0x85>;
    				};
    
    				dma-router@b78 {
    					compatible = "ti,dra7-dma-crossbar";
    					reg = <0xb78 0xfc>;
    					#dma-cells = <0x1>;
    					dma-requests = <0xcd>;
    					ti,dma-safe-map = <0x0>;
    					dma-masters = <0xe>;
    					phandle = <0x8d>;
    				};
    
    				dma-router@c78 {
    					compatible = "ti,dra7-dma-crossbar";
    					reg = <0xc78 0x7c>;
    					#dma-cells = <0x2>;
    					dma-requests = <0xcc>;
    					ti,dma-safe-map = <0x0>;
    					dma-masters = <0xf>;
    					phandle = <0xc3>;
    				};
    			};
    
    			cm_core_aon@5000 {
    				compatible = "ti,dra7-cm-core-aon", "simple-bus";
    				#address-cells = <0x1>;
    				#size-cells = <0x1>;
    				reg = <0x5000 0x2000>;
    				ranges = <0x0 0x5000 0x2000>;
    
    				clocks {
    					#address-cells = <0x1>;
    					#size-cells = <0x0>;
    
    					atl_clkin0_ck {
    						#clock-cells = <0x0>;
    						compatible = "ti,dra7-atl-clock";
    						clocks = <0x10 0x0 0x1a>;
    						phandle = <0xc4>;
    					};
    
    					atl_clkin1_ck {
    						#clock-cells = <0x0>;
    						compatible = "ti,dra7-atl-clock";
    						clocks = <0x10 0x0 0x1a>;
    						phandle = <0xc5>;
    					};
    
    					atl_clkin2_ck {
    						#clock-cells = <0x0>;
    						compatible = "ti,dra7-atl-clock";
    						clocks = <0x10 0x0 0x1a>;
    						phandle = <0xc6>;
    					};
    
    					atl_clkin3_ck {
    						#clock-cells = <0x0>;
    						compatible = "ti,dra7-atl-clock";
    						clocks = <0x10 0x0 0x1a>;
    						phandle = <0xc7>;
    					};
    
    					hdmi_clkin_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x0>;
    						phandle = <0x30>;
    					};
    
    					mlb_clkin_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x0>;
    						phandle = <0x81>;
    					};
    
    					mlbp_clkin_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x0>;
    						phandle = <0x82>;
    					};
    
    					pciesref_acs_clk_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x5f5e100>;
    						phandle = <0x40>;
    					};
    
    					ref_clkin0_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x0>;
    					};
    
    					ref_clkin1_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x0>;
    					};
    
    					ref_clkin2_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x0>;
    					};
    
    					ref_clkin3_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x0>;
    					};
    
    					rmii_clk_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x0>;
    					};
    
    					sdvenc_clkin_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x0>;
    					};
    
    					secure_32k_clk_src_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x8000>;
    						phandle = <0x6b>;
    					};
    
    					sys_clk32_crystal_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x8000>;
    						phandle = <0xc>;
    					};
    
    					sys_clk32_pseudo_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x11>;
    						clock-mult = <0x1>;
    						clock-div = <0x262>;
    						phandle = <0xd>;
    					};
    
    					virt_12000000_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0xb71b00>;
    						phandle = <0x59>;
    					};
    
    					virt_13000000_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0xc65d40>;
    					};
    
    					virt_16800000_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x1005900>;
    						phandle = <0x5b>;
    					};
    
    					virt_19200000_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x124f800>;
    						phandle = <0x5c>;
    					};
    
    					virt_20000000_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x1312d00>;
    						phandle = <0x5a>;
    					};
    
    					virt_26000000_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x18cba80>;
    						phandle = <0x5d>;
    					};
    
    					virt_27000000_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x19bfcc0>;
    						phandle = <0x5e>;
    					};
    
    					virt_38400000_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x249f000>;
    						phandle = <0x5f>;
    					};
    
    					sys_clkin2 {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x1588800>;
    						phandle = <0x60>;
    					};
    
    					usb_otg_clkin_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x0>;
    						phandle = <0x68>;
    					};
    
    					video1_clkin_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x0>;
    						phandle = <0x3a>;
    					};
    
    					video1_m2_clkin_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x0>;
    						phandle = <0x2f>;
    					};
    
    					video2_clkin_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x0>;
    						phandle = <0x3b>;
    					};
    
    					video2_m2_clkin_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x0>;
    						phandle = <0x2e>;
    					};
    
    					dpll_abe_ck@1e0 {
    						#clock-cells = <0x0>;
    						compatible = "ti,omap4-dpll-m4xen-clock";
    						clocks = <0x12 0x13>;
    						reg = <0x1e0 0x1e4 0x1ec 0x1e8>;
    						assigned-clocks = <0x14>;
    						assigned-clock-rates = <0x2faf080>;
    						phandle = <0x14>;
    					};
    
    					dpll_abe_x2_ck {
    						#clock-cells = <0x0>;
    						compatible = "ti,omap4-dpll-x2-clock";
    						clocks = <0x14>;
    						phandle = <0x15>;
    					};
    
    					dpll_abe_m2x2_ck@1f0 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x15>;
    						ti,max-div = <0x1f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x1f0>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0x16>;
    					};
    
    					abe_clk@108 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x16>;
    						ti,max-div = <0x4>;
    						reg = <0x108>;
    						ti,index-power-of-two;
    						phandle = <0x62>;
    					};
    
    					dpll_abe_m2_ck@1f0 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x14>;
    						ti,max-div = <0x1f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x1f0>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0x64>;
    					};
    
    					dpll_abe_m3x2_ck@1f4 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x15>;
    						ti,max-div = <0x1f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x1f4>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0x17>;
    					};
    
    					dpll_core_byp_mux@12c {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x11 0x17>;
    						ti,bit-shift = <0x17>;
    						reg = <0x12c>;
    						phandle = <0x18>;
    					};
    
    					dpll_core_ck@120 {
    						#clock-cells = <0x0>;
    						compatible = "ti,omap4-dpll-core-clock";
    						clocks = <0x11 0x18>;
    						reg = <0x120 0x124 0x12c 0x128>;
    						phandle = <0x19>;
    					};
    
    					dpll_core_x2_ck {
    						#clock-cells = <0x0>;
    						compatible = "ti,omap4-dpll-x2-clock";
    						clocks = <0x19>;
    						phandle = <0x1a>;
    					};
    
    					dpll_core_h12x2_ck@13c {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x1a>;
    						ti,max-div = <0x3f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x13c>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0x1b>;
    					};
    
    					mpu_dpll_hs_clk_div {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x1b>;
    						clock-mult = <0x1>;
    						clock-div = <0x1>;
    						phandle = <0x1c>;
    					};
    
    					dpll_mpu_ck@160 {
    						#clock-cells = <0x0>;
    						compatible = "ti,omap5-mpu-dpll-clock";
    						clocks = <0x11 0x1c>;
    						reg = <0x160 0x164 0x16c 0x168>;
    						phandle = <0x4>;
    					};
    
    					dpll_mpu_m2_ck@170 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x4>;
    						ti,max-div = <0x1f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x170>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0x1d>;
    					};
    
    					mpu_dclk_div {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x1d>;
    						clock-mult = <0x1>;
    						clock-div = <0x1>;
    						phandle = <0x6f>;
    					};
    
    					dsp_dpll_hs_clk_div {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x1b>;
    						clock-mult = <0x1>;
    						clock-div = <0x1>;
    						phandle = <0x1e>;
    					};
    
    					dpll_dsp_byp_mux@240 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x11 0x1e>;
    						ti,bit-shift = <0x17>;
    						reg = <0x240>;
    						phandle = <0x1f>;
    					};
    
    					dpll_dsp_ck@234 {
    						#clock-cells = <0x0>;
    						compatible = "ti,omap4-dpll-clock";
    						clocks = <0x11 0x1f>;
    						reg = <0x234 0x238 0x240 0x23c>;
    						assigned-clocks = <0x20>;
    						assigned-clock-rates = <0x23c34600>;
    						phandle = <0x20>;
    					};
    
    					dpll_dsp_m2_ck@244 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x20>;
    						ti,max-div = <0x1f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x244>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						assigned-clocks = <0x21>;
    						assigned-clock-rates = <0x23c34600>;
    						phandle = <0x21>;
    					};
    
    					iva_dpll_hs_clk_div {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x1b>;
    						clock-mult = <0x1>;
    						clock-div = <0x1>;
    						phandle = <0x22>;
    					};
    
    					dpll_iva_byp_mux@1ac {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x11 0x22>;
    						ti,bit-shift = <0x17>;
    						reg = <0x1ac>;
    						phandle = <0x23>;
    					};
    
    					dpll_iva_ck@1a0 {
    						#clock-cells = <0x0>;
    						compatible = "ti,omap4-dpll-clock";
    						clocks = <0x11 0x23>;
    						reg = <0x1a0 0x1a4 0x1ac 0x1a8>;
    						assigned-clocks = <0x24>;
    						assigned-clock-rates = <0x45707d40>;
    						phandle = <0x24>;
    					};
    
    					dpll_iva_m2_ck@1b0 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x24>;
    						ti,max-div = <0x1f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x1b0>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						assigned-clocks = <0x25>;
    						assigned-clock-rates = <0x17257f16>;
    						phandle = <0x25>;
    					};
    
    					iva_dclk {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x25>;
    						clock-mult = <0x1>;
    						clock-div = <0x1>;
    						phandle = <0x71>;
    					};
    
    					dpll_gpu_byp_mux@2e4 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x11 0x17>;
    						ti,bit-shift = <0x17>;
    						reg = <0x2e4>;
    						phandle = <0x26>;
    					};
    
    					dpll_gpu_ck@2d8 {
    						#clock-cells = <0x0>;
    						compatible = "ti,omap4-dpll-clock";
    						clocks = <0x11 0x26>;
    						reg = <0x2d8 0x2dc 0x2e4 0x2e0>;
    						assigned-clocks = <0x27>;
    						assigned-clock-rates = <0x4c1d7940>;
    						phandle = <0x27>;
    					};
    
    					dpll_gpu_m2_ck@2e8 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x27>;
    						ti,max-div = <0x1f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x2e8>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						assigned-clocks = <0x28>;
    						assigned-clock-rates = <0x195f286b>;
    						phandle = <0x28>;
    					};
    
    					dpll_core_m2_ck@130 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x19>;
    						ti,max-div = <0x1f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x130>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0x29>;
    					};
    
    					core_dpll_out_dclk_div {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x29>;
    						clock-mult = <0x1>;
    						clock-div = <0x1>;
    						phandle = <0x73>;
    					};
    
    					dpll_ddr_byp_mux@21c {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x11 0x17>;
    						ti,bit-shift = <0x17>;
    						reg = <0x21c>;
    						phandle = <0x2a>;
    					};
    
    					dpll_ddr_ck@210 {
    						#clock-cells = <0x0>;
    						compatible = "ti,omap4-dpll-clock";
    						clocks = <0x11 0x2a>;
    						reg = <0x210 0x214 0x21c 0x218>;
    						phandle = <0x2b>;
    					};
    
    					dpll_ddr_m2_ck@220 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x2b>;
    						ti,max-div = <0x1f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x220>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0x65>;
    					};
    
    					dpll_gmac_byp_mux@2b4 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x11 0x17>;
    						ti,bit-shift = <0x17>;
    						reg = <0x2b4>;
    						phandle = <0x2c>;
    					};
    
    					dpll_gmac_ck@2a8 {
    						#clock-cells = <0x0>;
    						compatible = "ti,omap4-dpll-clock";
    						clocks = <0x11 0x2c>;
    						reg = <0x2a8 0x2ac 0x2b4 0x2b0>;
    						phandle = <0x2d>;
    					};
    
    					dpll_gmac_m2_ck@2b8 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x2d>;
    						ti,max-div = <0x1f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x2b8>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0x66>;
    					};
    
    					video2_dclk_div {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x2e>;
    						clock-mult = <0x1>;
    						clock-div = <0x1>;
    						phandle = <0x75>;
    					};
    
    					video1_dclk_div {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x2f>;
    						clock-mult = <0x1>;
    						clock-div = <0x1>;
    						phandle = <0x76>;
    					};
    
    					hdmi_dclk_div {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x30>;
    						clock-mult = <0x1>;
    						clock-div = <0x1>;
    						phandle = <0x77>;
    					};
    
    					per_dpll_hs_clk_div {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x17>;
    						clock-mult = <0x1>;
    						clock-div = <0x2>;
    						phandle = <0x43>;
    					};
    
    					usb_dpll_hs_clk_div {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x17>;
    						clock-mult = <0x1>;
    						clock-div = <0x3>;
    						phandle = <0x47>;
    					};
    
    					eve_dpll_hs_clk_div {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x1b>;
    						clock-mult = <0x1>;
    						clock-div = <0x1>;
    						phandle = <0x31>;
    					};
    
    					dpll_eve_byp_mux@290 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x11 0x31>;
    						ti,bit-shift = <0x17>;
    						reg = <0x290>;
    						phandle = <0x32>;
    					};
    
    					dpll_eve_ck@284 {
    						#clock-cells = <0x0>;
    						compatible = "ti,omap4-dpll-clock";
    						clocks = <0x11 0x32>;
    						reg = <0x284 0x288 0x290 0x28c>;
    						phandle = <0x33>;
    					};
    
    					dpll_eve_m2_ck@294 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x33>;
    						ti,max-div = <0x1f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x294>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0x34>;
    					};
    
    					eve_dclk_div {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x34>;
    						clock-mult = <0x1>;
    						clock-div = <0x1>;
    						phandle = <0x80>;
    					};
    
    					dpll_core_h13x2_ck@140 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x1a>;
    						ti,max-div = <0x3f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x140>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    					};
    
    					dpll_core_h14x2_ck@144 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x1a>;
    						ti,max-div = <0x3f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x144>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0x51>;
    					};
    
    					dpll_core_h22x2_ck@154 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x1a>;
    						ti,max-div = <0x3f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x154>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0x3d>;
    					};
    
    					dpll_core_h23x2_ck@158 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x1a>;
    						ti,max-div = <0x3f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x158>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0x56>;
    					};
    
    					dpll_core_h24x2_ck@15c {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x1a>;
    						ti,max-div = <0x3f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x15c>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    					};
    
    					dpll_ddr_x2_ck {
    						#clock-cells = <0x0>;
    						compatible = "ti,omap4-dpll-x2-clock";
    						clocks = <0x2b>;
    						phandle = <0x35>;
    					};
    
    					dpll_ddr_h11x2_ck@228 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x35>;
    						ti,max-div = <0x3f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x228>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    					};
    
    					dpll_dsp_x2_ck {
    						#clock-cells = <0x0>;
    						compatible = "ti,omap4-dpll-x2-clock";
    						clocks = <0x20>;
    						phandle = <0x36>;
    					};
    
    					dpll_dsp_m3x2_ck@248 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x36>;
    						ti,max-div = <0x1f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x248>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						assigned-clocks = <0x37>;
    						assigned-clock-rates = <0x17d78400>;
    						phandle = <0x37>;
    					};
    
    					dpll_gmac_x2_ck {
    						#clock-cells = <0x0>;
    						compatible = "ti,omap4-dpll-x2-clock";
    						clocks = <0x2d>;
    						phandle = <0x38>;
    					};
    
    					dpll_gmac_h11x2_ck@2c0 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x38>;
    						ti,max-div = <0x3f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x2c0>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0x39>;
    					};
    
    					dpll_gmac_h12x2_ck@2c4 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x38>;
    						ti,max-div = <0x3f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x2c4>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    					};
    
    					dpll_gmac_h13x2_ck@2c8 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x38>;
    						ti,max-div = <0x3f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x2c8>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0xb5>;
    					};
    
    					dpll_gmac_m3x2_ck@2bc {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x38>;
    						ti,max-div = <0x1f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x2bc>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    					};
    
    					gmii_m_clk_div {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x39>;
    						clock-mult = <0x1>;
    						clock-div = <0x2>;
    					};
    
    					hdmi_clk2_div {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x30>;
    						clock-mult = <0x1>;
    						clock-div = <0x1>;
    					};
    
    					hdmi_div_clk {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x30>;
    						clock-mult = <0x1>;
    						clock-div = <0x1>;
    					};
    
    					l3_iclk_div@100 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						ti,max-div = <0x2>;
    						ti,bit-shift = <0x4>;
    						reg = <0x100>;
    						clocks = <0x1b>;
    						ti,index-power-of-two;
    						phandle = <0xa>;
    					};
    
    					l4_root_clk_div {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0xa>;
    						clock-mult = <0x1>;
    						clock-div = <0x2>;
    						phandle = <0xb>;
    					};
    
    					video1_clk2_div {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x3a>;
    						clock-mult = <0x1>;
    						clock-div = <0x1>;
    					};
    
    					video1_div_clk {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x3a>;
    						clock-mult = <0x1>;
    						clock-div = <0x1>;
    					};
    
    					video2_clk2_div {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x3b>;
    						clock-mult = <0x1>;
    						clock-div = <0x1>;
    					};
    
    					video2_div_clk {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x3b>;
    						clock-mult = <0x1>;
    						clock-div = <0x1>;
    					};
    
    					dummy_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x0>;
    					};
    				};
    
    				clockdomains {
    				};
    
    				mpu_cm@300 {
    					compatible = "ti,omap4-cm";
    					reg = <0x300 0x100>;
    					#address-cells = <0x1>;
    					#size-cells = <0x1>;
    					ranges = <0x0 0x300 0x100>;
    
    					clk@20 {
    						compatible = "ti,clkctrl";
    						reg = <0x20 0x4>;
    						#clock-cells = <0x2>;
    					};
    				};
    
    				dsp1_cm@400 {
    					compatible = "ti,omap4-cm";
    					reg = <0x400 0x100>;
    					#address-cells = <0x1>;
    					#size-cells = <0x1>;
    					ranges = <0x0 0x400 0x100>;
    
    					clk@20 {
    						compatible = "ti,clkctrl";
    						reg = <0x20 0x4>;
    						#clock-cells = <0x2>;
    					};
    				};
    
    				ipu1_cm@500 {
    					compatible = "ti,omap4-cm";
    					reg = <0x500 0x40>;
    					#address-cells = <0x1>;
    					#size-cells = <0x1>;
    					ranges = <0x0 0x500 0x100>;
    
    					clk@20 {
    						compatible = "ti,clkctrl";
    						reg = <0x20 0x20>;
    						#clock-cells = <0x2>;
    						assigned-clocks = <0x3c 0x0 0x18>;
    						assigned-clock-parents = <0x3d>;
    						phandle = <0x3c>;
    					};
    				};
    
    				ipu_cm@540 {
    					compatible = "ti,omap4-cm";
    					reg = <0x540 0xc0>;
    					#address-cells = <0x1>;
    					#size-cells = <0x1>;
    					ranges = <0x0 0x540 0xc0>;
    
    					clk@0 {
    						compatible = "ti,clkctrl";
    						reg = <0x0 0x44>;
    						#clock-cells = <0x2>;
    						phandle = <0x90>;
    					};
    				};
    
    				dsp2_cm@600 {
    					compatible = "ti,omap4-cm";
    					reg = <0x600 0x100>;
    					#address-cells = <0x1>;
    					#size-cells = <0x1>;
    					ranges = <0x0 0x600 0x100>;
    
    					clk@20 {
    						compatible = "ti,clkctrl";
    						reg = <0x20 0x4>;
    						#clock-cells = <0x2>;
    					};
    				};
    
    				rtc_cm@700 {
    					compatible = "ti,omap4-cm";
    					reg = <0x700 0x100>;
    					#address-cells = <0x1>;
    					#size-cells = <0x1>;
    					ranges = <0x0 0x700 0x100>;
    
    					clk@40 {
    						compatible = "ti,clkctrl";
    						reg = <0x40 0x8>;
    						#clock-cells = <0x2>;
    					};
    				};
    			};
    
    			cm_core@8000 {
    				compatible = "ti,dra7-cm-core", "simple-bus";
    				#address-cells = <0x1>;
    				#size-cells = <0x1>;
    				reg = <0x8000 0x3000>;
    				ranges = <0x0 0x8000 0x3000>;
    
    				clocks {
    					#address-cells = <0x1>;
    					#size-cells = <0x0>;
    
    					dpll_pcie_ref_ck@200 {
    						#clock-cells = <0x0>;
    						compatible = "ti,omap4-dpll-clock";
    						clocks = <0x11 0x11>;
    						reg = <0x200 0x204 0x20c 0x208>;
    						phandle = <0x3e>;
    					};
    
    					dpll_pcie_ref_m2ldo_ck@210 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x3e>;
    						ti,max-div = <0x1f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x210>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0x3f>;
    					};
    
    					apll_pcie_in_clk_mux@4ae06118 {
    						compatible = "ti,mux-clock";
    						clocks = <0x3f 0x40>;
    						#clock-cells = <0x0>;
    						reg = <0x21c 0x4>;
    						ti,bit-shift = <0x7>;
    						phandle = <0x41>;
    					};
    
    					apll_pcie_ck@21c {
    						#clock-cells = <0x0>;
    						compatible = "ti,dra7-apll-clock";
    						clocks = <0x41 0x3e>;
    						reg = <0x21c 0x220>;
    						phandle = <0x42>;
    					};
    
    					optfclk_pciephy_div@4a00821c {
    						compatible = "ti,divider-clock";
    						clocks = <0x42>;
    						#clock-cells = <0x0>;
    						reg = <0x21c>;
    						ti,dividers = <0x2 0x1>;
    						ti,bit-shift = <0x8>;
    						ti,max-div = <0x2>;
    						phandle = <0xb8>;
    					};
    
    					apll_pcie_clkvcoldo {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x42>;
    						clock-mult = <0x1>;
    						clock-div = <0x1>;
    					};
    
    					apll_pcie_clkvcoldo_div {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x42>;
    						clock-mult = <0x1>;
    						clock-div = <0x1>;
    					};
    
    					apll_pcie_m2_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x42>;
    						clock-mult = <0x1>;
    						clock-div = <0x1>;
    						phandle = <0x6a>;
    					};
    
    					dpll_per_byp_mux@14c {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x11 0x43>;
    						ti,bit-shift = <0x17>;
    						reg = <0x14c>;
    						phandle = <0x44>;
    					};
    
    					dpll_per_ck@140 {
    						#clock-cells = <0x0>;
    						compatible = "ti,omap4-dpll-clock";
    						clocks = <0x11 0x44>;
    						reg = <0x140 0x144 0x14c 0x148>;
    						phandle = <0x45>;
    					};
    
    					dpll_per_m2_ck@150 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x45>;
    						ti,max-div = <0x1f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x150>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0x46>;
    					};
    
    					func_96m_aon_dclk_div {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x46>;
    						clock-mult = <0x1>;
    						clock-div = <0x1>;
    						phandle = <0x78>;
    					};
    
    					dpll_usb_byp_mux@18c {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x11 0x47>;
    						ti,bit-shift = <0x17>;
    						reg = <0x18c>;
    						phandle = <0x48>;
    					};
    
    					dpll_usb_ck@180 {
    						#clock-cells = <0x0>;
    						compatible = "ti,omap4-dpll-j-type-clock";
    						clocks = <0x11 0x48>;
    						reg = <0x180 0x184 0x18c 0x188>;
    						phandle = <0x49>;
    					};
    
    					dpll_usb_m2_ck@190 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x49>;
    						ti,max-div = <0x7f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x190>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0x4d>;
    					};
    
    					dpll_pcie_ref_m2_ck@210 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x3e>;
    						ti,max-div = <0x7f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x210>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0x69>;
    					};
    
    					dpll_per_x2_ck {
    						#clock-cells = <0x0>;
    						compatible = "ti,omap4-dpll-x2-clock";
    						clocks = <0x45>;
    						phandle = <0x4a>;
    					};
    
    					dpll_per_h11x2_ck@158 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x4a>;
    						ti,max-div = <0x3f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x158>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0x4b>;
    					};
    
    					dpll_per_h12x2_ck@15c {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x4a>;
    						ti,max-div = <0x3f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x15c>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    					};
    
    					dpll_per_h13x2_ck@160 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x4a>;
    						ti,max-div = <0x3f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x160>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    					};
    
    					dpll_per_h14x2_ck@164 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x4a>;
    						ti,max-div = <0x3f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x164>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0x52>;
    					};
    
    					dpll_per_m2x2_ck@150 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x4a>;
    						ti,max-div = <0x1f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x150>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0x4c>;
    					};
    
    					dpll_usb_clkdcoldo {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x49>;
    						clock-mult = <0x1>;
    						clock-div = <0x1>;
    						phandle = <0x4f>;
    					};
    
    					func_128m_clk {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x4b>;
    						clock-mult = <0x1>;
    						clock-div = <0x2>;
    					};
    
    					func_12m_fclk {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x4c>;
    						clock-mult = <0x1>;
    						clock-div = <0x10>;
    					};
    
    					func_24m_clk {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x46>;
    						clock-mult = <0x1>;
    						clock-div = <0x4>;
    					};
    
    					func_48m_fclk {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x4c>;
    						clock-mult = <0x1>;
    						clock-div = <0x4>;
    					};
    
    					func_96m_fclk {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x4c>;
    						clock-mult = <0x1>;
    						clock-div = <0x2>;
    					};
    
    					l3init_60m_fclk@104 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x4d>;
    						reg = <0x104>;
    						ti,dividers = <0x1 0x8>;
    					};
    
    					clkout2_clk@6b0 {
    						#clock-cells = <0x0>;
    						compatible = "ti,gate-clock";
    						clocks = <0x4e>;
    						ti,bit-shift = <0x8>;
    						reg = <0x6b0>;
    						phandle = <0xea>;
    					};
    
    					l3init_960m_gfclk@6c0 {
    						#clock-cells = <0x0>;
    						compatible = "ti,gate-clock";
    						clocks = <0x4f>;
    						ti,bit-shift = <0x8>;
    						reg = <0x6c0>;
    					};
    
    					usb_phy1_always_on_clk32k@640 {
    						#clock-cells = <0x0>;
    						compatible = "ti,gate-clock";
    						clocks = <0x50>;
    						ti,bit-shift = <0x8>;
    						reg = <0x640>;
    						phandle = <0xba>;
    					};
    
    					usb_phy2_always_on_clk32k@688 {
    						#clock-cells = <0x0>;
    						compatible = "ti,gate-clock";
    						clocks = <0x50>;
    						ti,bit-shift = <0x8>;
    						reg = <0x688>;
    						phandle = <0xbc>;
    					};
    
    					usb_phy3_always_on_clk32k@698 {
    						#clock-cells = <0x0>;
    						compatible = "ti,gate-clock";
    						clocks = <0x50>;
    						ti,bit-shift = <0x8>;
    						reg = <0x698>;
    						phandle = <0xbd>;
    					};
    
    					gpu_core_gclk_mux@1220 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x51 0x52 0x28>;
    						ti,bit-shift = <0x18>;
    						reg = <0x1220>;
    						assigned-clocks = <0x53>;
    						assigned-clock-parents = <0x28>;
    						phandle = <0x53>;
    					};
    
    					gpu_hyd_gclk_mux@1220 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x51 0x52 0x28>;
    						ti,bit-shift = <0x1a>;
    						reg = <0x1220>;
    						assigned-clocks = <0x54>;
    						assigned-clock-parents = <0x28>;
    						phandle = <0x54>;
    					};
    
    					l3instr_ts_gclk_div@e50 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x55>;
    						ti,bit-shift = <0x18>;
    						reg = <0xe50>;
    						ti,dividers = <0x8 0x10 0x20>;
    					};
    
    					vip1_gclk_mux@1020 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0xa 0x56>;
    						ti,bit-shift = <0x18>;
    						reg = <0x1020>;
    					};
    
    					vip2_gclk_mux@1028 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0xa 0x56>;
    						ti,bit-shift = <0x18>;
    						reg = <0x1028>;
    					};
    
    					vip3_gclk_mux@1030 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0xa 0x56>;
    						ti,bit-shift = <0x18>;
    						reg = <0x1030>;
    					};
    				};
    
    				clockdomains {
    
    					coreaon_clkdm {
    						compatible = "ti,clockdomain";
    						clocks = <0x49>;
    					};
    				};
    
    				coreaon_cm@600 {
    					compatible = "ti,omap4-cm";
    					reg = <0x600 0x100>;
    					#address-cells = <0x1>;
    					#size-cells = <0x1>;
    					ranges = <0x0 0x600 0x100>;
    
    					clk@20 {
    						compatible = "ti,clkctrl";
    						reg = <0x20 0x1c>;
    						#clock-cells = <0x2>;
    						phandle = <0xbe>;
    					};
    				};
    
    				l3main1_cm@700 {
    					compatible = "ti,omap4-cm";
    					reg = <0x700 0x100>;
    					#address-cells = <0x1>;
    					#size-cells = <0x1>;
    					ranges = <0x0 0x700 0x100>;
    
    					clk@20 {
    						compatible = "ti,clkctrl";
    						reg = <0x20 0x74>;
    						#clock-cells = <0x2>;
    					};
    				};
    
    				ipu2_cm@900 {
    					compatible = "ti,omap4-cm";
    					reg = <0x900 0x100>;
    					#address-cells = <0x1>;
    					#size-cells = <0x1>;
    					ranges = <0x0 0x900 0x100>;
    
    					clk@20 {
    						compatible = "ti,clkctrl";
    						reg = <0x20 0x4>;
    						#clock-cells = <0x2>;
    					};
    				};
    
    				dma_cm@a00 {
    					compatible = "ti,omap4-cm";
    					reg = <0xa00 0x100>;
    					#address-cells = <0x1>;
    					#size-cells = <0x1>;
    					ranges = <0x0 0xa00 0x100>;
    
    					clk@20 {
    						compatible = "ti,clkctrl";
    						reg = <0x20 0x4>;
    						#clock-cells = <0x2>;
    					};
    				};
    
    				emif_cm@b00 {
    					compatible = "ti,omap4-cm";
    					reg = <0xb00 0x100>;
    					#address-cells = <0x1>;
    					#size-cells = <0x1>;
    					ranges = <0x0 0xb00 0x100>;
    
    					clk@20 {
    						compatible = "ti,clkctrl";
    						reg = <0x20 0x4>;
    						#clock-cells = <0x2>;
    					};
    				};
    
    				atl_cm@c00 {
    					compatible = "ti,omap4-cm";
    					reg = <0xc00 0x100>;
    					#address-cells = <0x1>;
    					#size-cells = <0x1>;
    					ranges = <0x0 0xc00 0x100>;
    
    					clk@0 {
    						compatible = "ti,clkctrl";
    						reg = <0x0 0x4>;
    						#clock-cells = <0x2>;
    						phandle = <0x10>;
    					};
    				};
    
    				l4cfg_cm@d00 {
    					compatible = "ti,omap4-cm";
    					reg = <0xd00 0x100>;
    					#address-cells = <0x1>;
    					#size-cells = <0x1>;
    					ranges = <0x0 0xd00 0x100>;
    
    					clk@20 {
    						compatible = "ti,clkctrl";
    						reg = <0x20 0x84>;
    						#clock-cells = <0x2>;
    					};
    				};
    
    				l3instr_cm@e00 {
    					compatible = "ti,omap4-cm";
    					reg = <0xe00 0x100>;
    					#address-cells = <0x1>;
    					#size-cells = <0x1>;
    					ranges = <0x0 0xe00 0x100>;
    
    					clk@20 {
    						compatible = "ti,clkctrl";
    						reg = <0x20 0xc>;
    						#clock-cells = <0x2>;
    					};
    				};
    
    				dss_cm@1100 {
    					compatible = "ti,omap4-cm";
    					reg = <0x1100 0x100>;
    					#address-cells = <0x1>;
    					#size-cells = <0x1>;
    					ranges = <0x0 0x1100 0x100>;
    
    					clk@20 {
    						compatible = "ti,clkctrl";
    						reg = <0x20 0x14>;
    						#clock-cells = <0x2>;
    						phandle = <0xcb>;
    					};
    				};
    
    				l3init_cm@1300 {
    					compatible = "ti,omap4-cm";
    					reg = <0x1300 0x100>;
    					#address-cells = <0x1>;
    					#size-cells = <0x1>;
    					ranges = <0x0 0x1300 0x100>;
    
    					clk@20 {
    						compatible = "ti,clkctrl";
    						reg = <0x20 0xd4>;
    						#clock-cells = <0x2>;
    						phandle = <0xb7>;
    					};
    				};
    
    				l4per_cm@1700 {
    					compatible = "ti,omap4-cm";
    					reg = <0x1700 0x300>;
    					#address-cells = <0x1>;
    					#size-cells = <0x1>;
    					ranges = <0x0 0x1700 0x300>;
    
    					clk@0 {
    						compatible = "ti,clkctrl";
    						reg = <0x0 0x20c>;
    						#clock-cells = <0x2>;
    						assigned-clocks = <0x57 0x168 0x18>;
    						assigned-clock-parents = <0x58>;
    						phandle = <0x57>;
    					};
    				};
    			};
    		};
    
    		l4@4ae00000 {
    			compatible = "ti,dra7-l4-wkup", "simple-bus";
    			#address-cells = <0x1>;
    			#size-cells = <0x1>;
    			ranges = <0x0 0x4ae00000 0x3f000>;
    
    			counter@4000 {
    				compatible = "ti,omap-counter32k";
    				reg = <0x4000 0x40>;
    				ti,hwmods = "counter_32k";
    			};
    
    			prm@6000 {
    				compatible = "ti,dra7-prm", "simple-bus";
    				reg = <0x6000 0x3000>;
    				interrupts = <0x0 0x6 0x4>;
    				#address-cells = <0x1>;
    				#size-cells = <0x1>;
    				ranges = <0x0 0x6000 0x3000>;
    
    				clocks {
    					#address-cells = <0x1>;
    					#size-cells = <0x0>;
    
    					sys_clkin1@110 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x59 0x5a 0x5b 0x5c 0x5d 0x5e 0x5f>;
    						reg = <0x110>;
    						ti,index-starts-at-one;
    						phandle = <0x11>;
    					};
    
    					abe_dpll_sys_clk_mux@118 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x11 0x60>;
    						reg = <0x118>;
    						phandle = <0x61>;
    					};
    
    					abe_dpll_bypass_clk_mux@114 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x61 0x50>;
    						reg = <0x114>;
    						phandle = <0x13>;
    					};
    
    					abe_dpll_clk_mux@10c {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x61 0x50>;
    						reg = <0x10c>;
    						phandle = <0x12>;
    					};
    
    					abe_24m_fclk@11c {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x16>;
    						reg = <0x11c>;
    						ti,dividers = <0x8 0x10>;
    						phandle = <0x58>;
    					};
    
    					aess_fclk@178 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x62>;
    						reg = <0x178>;
    						ti,max-div = <0x2>;
    						phandle = <0x63>;
    					};
    
    					abe_giclk_div@174 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x63>;
    						reg = <0x174>;
    						ti,max-div = <0x2>;
    						phandle = <0x91>;
    					};
    
    					abe_lp_clk_div@1d8 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x16>;
    						reg = <0x1d8>;
    						ti,dividers = <0x10 0x20>;
    						phandle = <0x83>;
    					};
    
    					abe_sys_clk_div@120 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x11>;
    						reg = <0x120>;
    						ti,max-div = <0x2>;
    					};
    
    					adc_gfclk_mux@1dc {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x11 0x60 0x50>;
    						reg = <0x1dc>;
    					};
    
    					sys_clk1_dclk_div@1c8 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x11>;
    						ti,max-div = <0x40>;
    						reg = <0x1c8>;
    						ti,index-power-of-two;
    						phandle = <0x6c>;
    					};
    
    					sys_clk2_dclk_div@1cc {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x60>;
    						ti,max-div = <0x40>;
    						reg = <0x1cc>;
    						ti,index-power-of-two;
    						phandle = <0x6d>;
    					};
    
    					per_abe_x1_dclk_div@1bc {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x64>;
    						ti,max-div = <0x40>;
    						reg = <0x1bc>;
    						ti,index-power-of-two;
    						phandle = <0x6e>;
    					};
    
    					dsp_gclk_div@18c {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x21>;
    						ti,max-div = <0x40>;
    						reg = <0x18c>;
    						ti,index-power-of-two;
    						phandle = <0x70>;
    					};
    
    					gpu_dclk@1a0 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x28>;
    						ti,max-div = <0x40>;
    						reg = <0x1a0>;
    						ti,index-power-of-two;
    						phandle = <0x72>;
    					};
    
    					emif_phy_dclk_div@190 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x65>;
    						ti,max-div = <0x40>;
    						reg = <0x190>;
    						ti,index-power-of-two;
    						phandle = <0x74>;
    					};
    
    					gmac_250m_dclk_div@19c {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x66>;
    						ti,max-div = <0x40>;
    						reg = <0x19c>;
    						ti,index-power-of-two;
    						phandle = <0x67>;
    					};
    
    					gmac_main_clk {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x67>;
    						clock-mult = <0x1>;
    						clock-div = <0x2>;
    						phandle = <0xc8>;
    					};
    
    					l3init_480m_dclk_div@1ac {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x4d>;
    						ti,max-div = <0x40>;
    						reg = <0x1ac>;
    						ti,index-power-of-two;
    						phandle = <0x79>;
    					};
    
    					usb_otg_dclk_div@184 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x68>;
    						ti,max-div = <0x40>;
    						reg = <0x184>;
    						ti,index-power-of-two;
    						phandle = <0x7a>;
    					};
    
    					sata_dclk_div@1c0 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x11>;
    						ti,max-div = <0x40>;
    						reg = <0x1c0>;
    						ti,index-power-of-two;
    						phandle = <0x7b>;
    					};
    
    					pcie2_dclk_div@1b8 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x69>;
    						ti,max-div = <0x40>;
    						reg = <0x1b8>;
    						ti,index-power-of-two;
    						phandle = <0x7c>;
    					};
    
    					pcie_dclk_div@1b4 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x6a>;
    						ti,max-div = <0x40>;
    						reg = <0x1b4>;
    						ti,index-power-of-two;
    						phandle = <0x7d>;
    					};
    
    					emu_dclk_div@194 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x11>;
    						ti,max-div = <0x40>;
    						reg = <0x194>;
    						ti,index-power-of-two;
    						phandle = <0x7e>;
    					};
    
    					secure_32k_dclk_div@1c4 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x6b>;
    						ti,max-div = <0x40>;
    						reg = <0x1c4>;
    						ti,index-power-of-two;
    						phandle = <0x7f>;
    					};
    
    					clkoutmux0_clk_mux@158 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x6c 0x6d 0x6e 0x6f 0x70 0x71 0x72 0x73 0x74 0x67 0x75 0x76 0x77 0x78 0x79 0x7a 0x7b 0x7c 0x7d 0x7e 0x7f 0x80>;
    						reg = <0x158>;
    					};
    
    					clkoutmux1_clk_mux@15c {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x6c 0x6d 0x6e 0x6f 0x70 0x71 0x72 0x73 0x74 0x67 0x75 0x76 0x77 0x78 0x79 0x7a 0x7b 0x7c 0x7d 0x7e 0x7f 0x80>;
    						reg = <0x15c>;
    					};
    
    					clkoutmux2_clk_mux@160 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x6c 0x6d 0x6e 0x6f 0x70 0x71 0x72 0x73 0x74 0x67 0x75 0x76 0x77 0x78 0x79 0x7a 0x7b 0x7c 0x7d 0x7e 0x7f 0x80>;
    						reg = <0x160>;
    						phandle = <0x4e>;
    					};
    
    					custefuse_sys_gfclk_div {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x11>;
    						clock-mult = <0x1>;
    						clock-div = <0x2>;
    					};
    
    					eve_clk@180 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x34 0x37>;
    						reg = <0x180>;
    					};
    
    					hdmi_dpll_clk_mux@164 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x11 0x60>;
    						reg = <0x164>;
    					};
    
    					mlb_clk@134 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x81>;
    						ti,max-div = <0x40>;
    						reg = <0x134>;
    						ti,index-power-of-two;
    					};
    
    					mlbp_clk@130 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x82>;
    						ti,max-div = <0x40>;
    						reg = <0x130>;
    						ti,index-power-of-two;
    					};
    
    					per_abe_x1_gfclk2_div@138 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x64>;
    						ti,max-div = <0x40>;
    						reg = <0x138>;
    						ti,index-power-of-two;
    					};
    
    					timer_sys_clk_div@144 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x11>;
    						reg = <0x144>;
    						ti,max-div = <0x2>;
    					};
    
    					video1_dpll_clk_mux@168 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x11 0x60>;
    						reg = <0x168>;
    					};
    
    					video2_dpll_clk_mux@16c {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x11 0x60>;
    						reg = <0x16c>;
    					};
    
    					wkupaon_iclk_mux@108 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x11 0x83>;
    						reg = <0x108>;
    						phandle = <0x55>;
    					};
    				};
    
    				clockdomains {
    				};
    
    				wkupaon_cm@1800 {
    					compatible = "ti,omap4-cm";
    					reg = <0x1800 0x100>;
    					#address-cells = <0x1>;
    					#size-cells = <0x1>;
    					ranges = <0x0 0x1800 0x100>;
    
    					clk@20 {
    						compatible = "ti,clkctrl";
    						reg = <0x20 0x6c>;
    						#clock-cells = <0x2>;
    						phandle = <0x8f>;
    					};
    				};
    			};
    
    			scm_conf@c000 {
    				compatible = "syscon";
    				reg = <0xc000 0x1000>;
    				phandle = <0x7>;
    			};
    		};
    
    		axi@0 {
    			compatible = "simple-bus";
    			#size-cells = <0x1>;
    			#address-cells = <0x1>;
    			ranges = <0x51000000 0x51000000 0x3000 0x0 0x20000000 0x10000000>;
    
    			pcie@51000000 {
    				reg = <0x51000000 0x2000 0x51002000 0x14c 0x1000 0x2000>;
    				reg-names = "rc_dbics", "ti_conf", "config";
    				interrupts = <0x0 0xe8 0x4 0x0 0xe9 0x4>;
    				#address-cells = <0x3>;
    				#size-cells = <0x2>;
    				device_type = "pci";
    				ranges = <0x81000000 0x0 0x0 0x3000 0x0 0x10000 0x82000000 0x0 0x20013000 0x13000 0x0 0xffed000>;
    				bus-range = <0x0 0xff>;
    				#interrupt-cells = <0x1>;
    				num-lanes = <0x1>;
    				linux,pci-domain = <0x0>;
    				ti,hwmods = "pcie1";
    				phys = <0x84>;
    				phy-names = "pcie-phy0";
    				ti,syscon-lane-sel = <0x85 0x18>;
    				interrupt-map-mask = <0x0 0x0 0x0 0x7>;
    				interrupt-map = <0x0 0x0 0x0 0x1 0x86 0x1 0x0 0x0 0x0 0x2 0x86 0x2 0x0 0x0 0x0 0x3 0x86 0x3 0x0 0x0 0x0 0x4 0x86 0x4>;
    				status = "ok";
    				compatible = "ti,dra746-pcie-rc", "ti,dra7-pcie";
    				gpios = <0x87 0x8 0x1>;
    
    				interrupt-controller {
    					interrupt-controller;
    					#address-cells = <0x0>;
    					#interrupt-cells = <0x1>;
    					phandle = <0x86>;
    				};
    			};
    
    			pcie_ep@51000000 {
    				reg = <0x51000000 0x28 0x51002000 0x14c 0x51001000 0x28 0x1000 0x10000000>;
    				reg-names = "ep_dbics", "ti_conf", "ep_dbics2", "addr_space";
    				interrupts = <0x0 0xe8 0x4>;
    				num-lanes = <0x1>;
    				num-ib-windows = <0x4>;
    				num-ob-windows = <0x10>;
    				ti,hwmods = "pcie1";
    				phys = <0x84>;
    				phy-names = "pcie-phy0";
    				ti,syscon-unaligned-access = <0x88 0x14 0x1>;
    				ti,syscon-lane-sel = <0x85 0x18>;
    				status = "disabled";
    				compatible = "ti,dra746-pcie-ep", "ti,dra7-pcie-ep";
    			};
    		};
    
    		axi@1 {
    			compatible = "simple-bus";
    			#size-cells = <0x1>;
    			#address-cells = <0x1>;
    			ranges = <0x51800000 0x51800000 0x3000 0x0 0x30000000 0x10000000>;
    			status = "disabled";
    
    			pcie@51800000 {
    				reg = <0x51800000 0x2000 0x51802000 0x14c 0x1000 0x2000>;
    				reg-names = "rc_dbics", "ti_conf", "config";
    				interrupts = <0x0 0x163 0x4 0x0 0x164 0x4>;
    				#address-cells = <0x3>;
    				#size-cells = <0x2>;
    				device_type = "pci";
    				ranges = <0x81000000 0x0 0x0 0x3000 0x0 0x10000 0x82000000 0x0 0x30013000 0x13000 0x0 0xffed000>;
    				bus-range = <0x0 0xff>;
    				#interrupt-cells = <0x1>;
    				num-lanes = <0x1>;
    				linux,pci-domain = <0x1>;
    				ti,hwmods = "pcie2";
    				phys = <0x89>;
    				phy-names = "pcie-phy0";
    				interrupt-map-mask = <0x0 0x0 0x0 0x7>;
    				interrupt-map = <0x0 0x0 0x0 0x1 0x8a 0x1 0x0 0x0 0x0 0x2 0x8a 0x2 0x0 0x0 0x0 0x3 0x8a 0x3 0x0 0x0 0x0 0x4 0x8a 0x4>;
    				compatible = "ti,dra746-pcie-rc", "ti,dra7-pcie";
    
    				interrupt-controller {
    					interrupt-controller;
    					#address-cells = <0x0>;
    					#interrupt-cells = <0x1>;
    					phandle = <0x8a>;
    				};
    			};
    		};
    
    		ocmcram@40300000 {
    			compatible = "mmio-sram";
    			reg = <0x40300000 0x80000>;
    			ranges = <0x0 0x40300000 0x80000>;
    			#address-cells = <0x1>;
    			#size-cells = <0x1>;
    
    			sram-hs@0 {
    				compatible = "ti,secure-ram";
    				reg = <0x0 0x0>;
    			};
    		};
    
    		ocmcram@40400000 {
    			status = "disabled";
    			compatible = "mmio-sram";
    			reg = <0x40400000 0x100000>;
    			ranges = <0x0 0x40400000 0x100000>;
    			#address-cells = <0x1>;
    			#size-cells = <0x1>;
    		};
    
    		ocmcram@40500000 {
    			status = "disabled";
    			compatible = "mmio-sram";
    			reg = <0x40500000 0x100000>;
    			ranges = <0x0 0x40500000 0x100000>;
    			#address-cells = <0x1>;
    			#size-cells = <0x1>;
    		};
    
    		bandgap@4a0021e0 {
    			reg = <0x4a0021e0 0xc 0x4a00232c 0xc 0x4a002380 0x2c 0x4a0023c0 0x3c 0x4a002564 0x8 0x4a002574 0x50>;
    			compatible = "ti,dra752-bandgap";
    			interrupts = <0x0 0x79 0x4>;
    			#thermal-sensor-cells = <0x1>;
    			phandle = <0xd9>;
    		};
    
    		dsp_system@40d00000 {
    			compatible = "syscon";
    			reg = <0x40d00000 0x100>;
    			phandle = <0xb3>;
    		};
    
    		padconf@4844a000 {
    			compatible = "ti,dra7-iodelay";
    			reg = <0x4844a000 0xd1c>;
    			#address-cells = <0x1>;
    			#size-cells = <0x0>;
    			#pinctrl-cells = <0x2>;
    
    			mmc1_iodelay_ddr_rev11_conf {
    				pinctrl-pin-array = <0x618 0x23c 0x21c 0x620 0x5f5 0x0 0x624 0x0 0x258 0x628 0x0 0x0 0x62c 0x37 0x0 0x630 0x193 0x78 0x634 0x0 0x0 0x638 0x0 0x0 0x63c 0x17 0x3c 0x640 0x0 0x0 0x644 0x0 0x0 0x648 0x19 0x3c 0x64c 0x0 0x0 0x650 0x0 0x0 0x654 0x0 0x0 0x658 0x0 0x0 0x65c 0x0 0x0>;
    			};
    
    			mmc1_iodelay_ddr50_rev20_conf {
    				pinctrl-pin-array = <0x618 0x434 0x14a 0x620 0x4f7 0x0 0x624 0x2d2 0x0 0x628 0x0 0x0 0x62c 0x0 0x0 0x630 0x2ef 0x0 0x634 0x0 0x0 0x638 0x14 0x0 0x63c 0x100 0x0 0x640 0x0 0x0 0x644 0x0 0x0 0x648 0x107 0x0 0x64c 0x0 0x0 0x650 0x0 0x0 0x654 0x0 0x0 0x658 0x0 0x0 0x65c 0x0 0x0>;
    			};
    
    			mmc1_iodelay_sdr104_rev11_conf {
    				pinctrl-pin-array = <0x620 0x427 0x11 0x628 0x0 0x0 0x62c 0x17 0x0 0x634 0x0 0x0 0x638 0x0 0x0 0x640 0x0 0x0 0x644 0x2 0x0 0x64c 0x0 0x0 0x650 0x0 0x0 0x658 0x0 0x0 0x65c 0x0 0x0>;
    			};
    
    			mmc1_iodelay_sdr104_rev20_conf {
    				pinctrl-pin-array = <0x620 0x258 0x190 0x628 0x0 0x0 0x62c 0x0 0x0 0x634 0x0 0x0 0x638 0x1e 0x0 0x640 0x0 0x0 0x644 0x0 0x0 0x64c 0x0 0x0 0x650 0x0 0x0 0x658 0x0 0x0 0x65c 0x0 0x0>;
    			};
    
    			mmc2_iodelay_hs200_rev11_conf {
    				pinctrl-pin-array = <0x190 0x26d 0x258 0x194 0x12c 0x0 0x1a8 0x2e3 0x258 0x1ac 0xf0 0x0 0x1b4 0x32c 0x258 0x1b8 0xf0 0x0 0x1c0 0x3ba 0x258 0x1c4 0x3c 0x0 0x1d0 0x53c 0x1a4 0x1d8 0x3a7 0x258 0x1dc 0x0 0x0 0x1e4 0x20d 0x258 0x1e8 0x78 0x0 0x1f0 0x2ff 0x258 0x1f4 0xe1 0x0 0x1fc 0x235 0x258 0x200 0x3c 0x0 0x364 0x3c9 0x258 0x368 0xb4 0x0>;
    			};
    
    			mmc2_iodelay_hs200_rev20_conf {
    				pinctrl-pin-array = <0x190 0x112 0x0 0x194 0xa2 0x0 0x1a8 0x191 0x0 0x1ac 0x49 0x0 0x1b4 0x1d1 0x0 0x1b8 0x73 0x0 0x1c0 0x279 0x0 0x1c4 0x2f 0x0 0x1d0 0x3a7 0x118 0x1d8 0x26d 0x0 0x1dc 0x0 0x0 0x1e4 0xb7 0x0 0x1e8 0x0 0x0 0x1f0 0x1d3 0x0 0x1f4 0x0 0x0 0x1fc 0x106 0x0 0x200 0x2e 0x0 0x364 0x2ac 0x0 0x368 0x4c 0x0>;
    			};
    
    			mmc2_iodelay_ddr_3_3v_rev11_conf {
    				pinctrl-pin-array = <0x18c 0x0 0x78 0x190 0x0 0x0 0x194 0xae 0x0 0x1a4 0x109 0x168 0x1a8 0x0 0x0 0x1ac 0xa8 0x0 0x1b0 0x0 0x78 0x1b4 0x0 0x0 0x1b8 0x88 0x0 0x1bc 0x0 0x78 0x1c0 0x0 0x0 0x1c4 0x0 0x0 0x1c8 0x11f 0x1a4 0x1d0 0x36f 0x0 0x1d4 0x90 0xf0 0x1d8 0x0 0x0 0x1dc 0x0 0x0 0x1e0 0x0 0x0 0x1e4 0x0 0x0 0x1e8 0x22 0x0 0x1ec 0x0 0x78 0x1f0 0x0 0x0 0x1f4 0x78 0x0 0x1f8 0x78 0xb4 0x1fc 0x0 0x0 0x200 0x0 0x0 0x360 0x0 0x0 0x364 0x0 0x0 0x368 0xb 0x0>;
    			};
    
    			mmc2_iodelay_ddr_1_8v_rev11_conf {
    				pinctrl-pin-array = <0x18c 0x0 0x0 0x190 0x0 0x0 0x194 0xae 0x0 0x1a4 0x112 0xf0 0x1a8 0x0 0x0 0x1ac 0xa8 0x0 0x1b0 0x0 0x3c 0x1b4 0x0 0x0 0x1b8 0x88 0x0 0x1bc 0x0 0x3c 0x1c0 0x0 0x0 0x1c4 0x0 0x0 0x1c8 0x202 0x168 0x1d0 0x36f 0x0 0x1d4 0xbb 0x78 0x1d8 0x0 0x0 0x1dc 0x0 0x0 0x1e0 0x0 0x0 0x1e4 0x0 0x0 0x1e8 0x22 0x0 0x1ec 0x0 0x3c 0x1f0 0x0 0x0 0x1f4 0x78 0x0 0x1f8 0x79 0x3c 0x1fc 0x0 0x0 0x200 0x0 0x0 0x360 0x0 0x0 0x364 0x0 0x0 0x368 0xb 0x0>;
    			};
    
    			mmc3_iodelay_manual1_conf {
    				pinctrl-pin-array = <0x678 0x196 0x0 0x680 0x293 0x0 0x684 0x0 0x0 0x688 0x0 0x0 0x68c 0x0 0x0 0x690 0x82 0x0 0x694 0x0 0x0 0x698 0x0 0x0 0x69c 0xa9 0x0 0x6a0 0x0 0x0 0x6a4 0x0 0x0 0x6a8 0x0 0x0 0x6ac 0x0 0x0 0x6b0 0x0 0x0 0x6b4 0x1c9 0x0 0x6b8 0x0 0x0 0x6bc 0x0 0x0>;
    			};
    
    			mmc4_iodelay_ds_rev11_conf {
    				pinctrl-pin-array = <0x840 0x0 0x0 0x848 0x0 0x0 0x84c 0x60 0x0 0x850 0x0 0x0 0x854 0x0 0x0 0x870 0x246 0x0 0x874 0x0 0x0 0x878 0x0 0x0 0x87c 0x187 0x0 0x880 0x0 0x0 0x884 0x0 0x0 0x888 0x231 0x0 0x88c 0x0 0x0 0x890 0x0 0x0 0x894 0x24c 0x0 0x898 0x0 0x0 0x89c 0x0 0x0>;
    			};
    
    			mmc4_iodelay_ds_rev20_conf {
    				pinctrl-pin-array = <0x840 0x0 0x0 0x848 0x0 0x0 0x84c 0x133 0x0 0x850 0x0 0x0 0x854 0x0 0x0 0x870 0x311 0x0 0x874 0x0 0x0 0x878 0x0 0x0 0x87c 0x265 0x0 0x880 0x0 0x0 0x884 0x0 0x0 0x888 0x2ab 0x0 0x88c 0x0 0x0 0x890 0x0 0x0 0x894 0x343 0x0 0x898 0x0 0x0 0x89c 0x0 0x0>;
    			};
    
    			mmc4_iodelay_sdr12_hs_sdr25_rev11_conf {
    				pinctrl-pin-array = <0x840 0x0 0x0 0x848 0xa5b 0x0 0x84c 0x624 0x0 0x850 0x0 0x0 0x854 0x0 0x0 0x870 0x779 0x0 0x874 0x0 0x0 0x878 0x0 0x0 0x87c 0x6b9 0x0 0x880 0x0 0x0 0x884 0x0 0x0 0x888 0x763 0x0 0x88c 0x0 0x0 0x890 0x0 0x0 0x894 0x77f 0x0 0x898 0x0 0x0 0x89c 0x0 0x0>;
    			};
    
    			mmc4_iodelay_sdr12_hs_sdr25_rev20_conf {
    				pinctrl-pin-array = <0x840 0x0 0x0 0x848 0x47b 0x0 0x84c 0x72a 0x0 0x850 0x0 0x0 0x854 0x0 0x0 0x870 0x875 0x0 0x874 0x0 0x0 0x878 0x0 0x0 0x87c 0x789 0x40 0x880 0x0 0x0 0x884 0x0 0x0 0x888 0x78f 0x80 0x88c 0x0 0x0 0x890 0x0 0x0 0x894 0x87c 0x2c 0x898 0x0 0x0 0x89c 0x0 0x0>;
    			};
    		};
    
    		dma-controller@4a056000 {
    			compatible = "ti,omap4430-sdma";
    			reg = <0x4a056000 0x1000>;
    			interrupts = <0x0 0x7 0x4 0x0 0x8 0x4 0x0 0x9 0x4 0x0 0xa 0x4>;
    			#dma-cells = <0x1>;
    			dma-channels = <0x20>;
    			dma-requests = <0x7f>;
    			ti,hwmods = "dma_system";
    			phandle = <0xe>;
    		};
    
    		edma@43300000 {
    			compatible = "ti,edma3-tpcc";
    			ti,hwmods = "tpcc";
    			reg = <0x43300000 0x100000>;
    			reg-names = "edma3_cc";
    			interrupts = <0x0 0x169 0x4 0x0 0x168 0x4 0x0 0x167 0x4>;
    			interrupt-names = "edma3_ccint", "edma3_mperr", "edma3_ccerrint";
    			dma-requests = <0x40>;
    			#dma-cells = <0x2>;
    			ti,tptcs = <0x8b 0x7 0x8c 0x0>;
    			phandle = <0xf>;
    		};
    
    		tptc@43400000 {
    			compatible = "ti,edma3-tptc";
    			ti,hwmods = "tptc0";
    			reg = <0x43400000 0x100000>;
    			interrupts = <0x0 0x172 0x4>;
    			interrupt-names = "edma3_tcerrint";
    			phandle = <0x8b>;
    		};
    
    		tptc@43500000 {
    			compatible = "ti,edma3-tptc";
    			ti,hwmods = "tptc1";
    			reg = <0x43500000 0x100000>;
    			interrupts = <0x0 0x173 0x4>;
    			interrupt-names = "edma3_tcerrint";
    			phandle = <0x8c>;
    		};
    
    		gpio@4ae10000 {
    			compatible = "ti,omap4-gpio";
    			reg = <0x4ae10000 0x200>;
    			interrupts = <0x0 0x18 0x4>;
    			ti,hwmods = "gpio1";
    			gpio-controller;
    			#gpio-cells = <0x2>;
    			interrupt-controller;
    			#interrupt-cells = <0x2>;
    			phandle = <0xa7>;
    		};
    
    		gpio@48055000 {
    			compatible = "ti,omap4-gpio";
    			reg = <0x48055000 0x200>;
    			interrupts = <0x0 0x19 0x4>;
    			ti,hwmods = "gpio2";
    			gpio-controller;
    			#gpio-cells = <0x2>;
    			interrupt-controller;
    			#interrupt-cells = <0x2>;
    			phandle = <0x87>;
    		};
    
    		gpio@48057000 {
    			compatible = "ti,omap4-gpio";
    			reg = <0x48057000 0x200>;
    			interrupts = <0x0 0x1a 0x4>;
    			ti,hwmods = "gpio3";
    			gpio-controller;
    			#gpio-cells = <0x2>;
    			interrupt-controller;
    			#interrupt-cells = <0x2>;
    		};
    
    		gpio@48059000 {
    			compatible = "ti,omap4-gpio";
    			reg = <0x48059000 0x200>;
    			interrupts = <0x0 0x1b 0x4>;
    			ti,hwmods = "gpio4";
    			gpio-controller;
    			#gpio-cells = <0x2>;
    			interrupt-controller;
    			#interrupt-cells = <0x2>;
    			phandle = <0xa9>;
    		};
    
    		gpio@4805b000 {
    			compatible = "ti,omap4-gpio";
    			reg = <0x4805b000 0x200>;
    			interrupts = <0x0 0x1c 0x4>;
    			ti,hwmods = "gpio5";
    			gpio-controller;
    			#gpio-cells = <0x2>;
    			interrupt-controller;
    			#interrupt-cells = <0x2>;
    		};
    
    		gpio@4805d000 {
    			compatible = "ti,omap4-gpio";
    			reg = <0x4805d000 0x200>;
    			interrupts = <0x0 0x1d 0x4>;
    			ti,hwmods = "gpio6";
    			gpio-controller;
    			#gpio-cells = <0x2>;
    			interrupt-controller;
    			#interrupt-cells = <0x2>;
    			phandle = <0xaf>;
    		};
    
    		gpio@48051000 {
    			compatible = "ti,omap4-gpio";
    			reg = <0x48051000 0x200>;
    			interrupts = <0x0 0x1e 0x4>;
    			ti,hwmods = "gpio7";
    			gpio-controller;
    			#gpio-cells = <0x2>;
    			interrupt-controller;
    			#interrupt-cells = <0x2>;
    			ti,no-reset-on-init;
    			ti,no-idle-on-init;
    			phandle = <0xaa>;
    		};
    
    		gpio@48053000 {
    			compatible = "ti,omap4-gpio";
    			reg = <0x48053000 0x200>;
    			interrupts = <0x0 0x74 0x4>;
    			ti,hwmods = "gpio8";
    			gpio-controller;
    			#gpio-cells = <0x2>;
    			interrupt-controller;
    			#interrupt-cells = <0x2>;
    		};
    
    		serial@4806a000 {
    			compatible = "ti,dra742-uart", "ti,omap4-uart";
    			reg = <0x4806a000 0x100>;
    			interrupts-extended = <0x1 0x0 0x43 0x4>;
    			ti,hwmods = "uart1";
    			clock-frequency = <0x2dc6c00>;
    			status = "disabled";
    			dmas = <0x8d 0x31 0x8d 0x32>;
    			dma-names = "tx", "rx";
    		};
    
    		serial@4806c000 {
    			compatible = "ti,dra742-uart", "ti,omap4-uart";
    			reg = <0x4806c000 0x100>;
    			interrupts = <0x0 0x44 0x4>;
    			ti,hwmods = "uart2";
    			clock-frequency = <0x2dc6c00>;
    			status = "disabled";
    			dmas = <0x8d 0x33 0x8d 0x34>;
    			dma-names = "tx", "rx";
    		};
    
    		serial@48020000 {
    			compatible = "ti,dra742-uart", "ti,omap4-uart";
    			reg = <0x48020000 0x100>;
    			interrupts = <0x0 0x45 0x4>;
    			ti,hwmods = "uart3";
    			clock-frequency = <0x2dc6c00>;
    			status = "okay";
    			dmas = <0x8d 0x35 0x8d 0x36>;
    			dma-names = "tx", "rx";
    			interrupts-extended = <0x1 0x0 0x45 0x4 0x8e 0x3f8>;
    		};
    
    		serial@4806e000 {
    			compatible = "ti,dra742-uart", "ti,omap4-uart";
    			reg = <0x4806e000 0x100>;
    			interrupts = <0x0 0x41 0x4>;
    			ti,hwmods = "uart4";
    			clock-frequency = <0x2dc6c00>;
    			status = "disabled";
    			dmas = <0x8d 0x37 0x8d 0x38>;
    			dma-names = "tx", "rx";
    		};
    
    		serial@48066000 {
    			compatible = "ti,dra742-uart", "ti,omap4-uart";
    			reg = <0x48066000 0x100>;
    			interrupts = <0x0 0x64 0x4>;
    			ti,hwmods = "uart5";
    			clock-frequency = <0x2dc6c00>;
    			status = "disabled";
    			dmas = <0x8d 0x3f 0x8d 0x40>;
    			dma-names = "tx", "rx";
    		};
    
    		serial@48068000 {
    			compatible = "ti,dra742-uart", "ti,omap4-uart";
    			reg = <0x48068000 0x100>;
    			interrupts = <0x0 0x65 0x4>;
    			ti,hwmods = "uart6";
    			clock-frequency = <0x2dc6c00>;
    			status = "disabled";
    			dmas = <0x8d 0x4f 0x8d 0x50>;
    			dma-names = "tx", "rx";
    		};
    
    		serial@48420000 {
    			compatible = "ti,dra742-uart", "ti,omap4-uart";
    			reg = <0x48420000 0x100>;
    			interrupts = <0x0 0xda 0x4>;
    			ti,hwmods = "uart7";
    			clock-frequency = <0x2dc6c00>;
    			status = "disabled";
    		};
    
    		serial@48422000 {
    			compatible = "ti,dra742-uart", "ti,omap4-uart";
    			reg = <0x48422000 0x100>;
    			interrupts = <0x0 0xdb 0x4>;
    			ti,hwmods = "uart8";
    			clock-frequency = <0x2dc6c00>;
    			status = "disabled";
    		};
    
    		serial@48424000 {
    			compatible = "ti,dra742-uart", "ti,omap4-uart";
    			reg = <0x48424000 0x100>;
    			interrupts = <0x0 0xdc 0x4>;
    			ti,hwmods = "uart9";
    			clock-frequency = <0x2dc6c00>;
    			status = "disabled";
    		};
    
    		serial@4ae2b000 {
    			compatible = "ti,dra742-uart", "ti,omap4-uart";
    			reg = <0x4ae2b000 0x100>;
    			interrupts = <0x0 0xdd 0x4>;
    			ti,hwmods = "uart10";
    			clock-frequency = <0x2dc6c00>;
    			status = "disabled";
    		};
    
    		mailbox@4a0f4000 {
    			compatible = "ti,omap4-mailbox";
    			reg = <0x4a0f4000 0x200>;
    			interrupts = <0x0 0x15 0x4 0x0 0x87 0x4 0x0 0x86 0x4>;
    			ti,hwmods = "mailbox1";
    			#mbox-cells = <0x1>;
    			ti,mbox-num-users = <0x3>;
    			ti,mbox-num-fifos = <0x8>;
    			status = "disabled";
    		};
    
    		mailbox@4883a000 {
    			compatible = "ti,omap4-mailbox";
    			reg = <0x4883a000 0x200>;
    			interrupts = <0x0 0xed 0x4 0x0 0xee 0x4 0x0 0xef 0x4 0x0 0xf0 0x4>;
    			ti,hwmods = "mailbox2";
    			#mbox-cells = <0x1>;
    			ti,mbox-num-users = <0x4>;
    			ti,mbox-num-fifos = <0xc>;
    			status = "disabled";
    		};
    
    		mailbox@4883c000 {
    			compatible = "ti,omap4-mailbox";
    			reg = <0x4883c000 0x200>;
    			interrupts = <0x0 0xf1 0x4 0x0 0xf2 0x4 0x0 0xf3 0x4 0x0 0xf4 0x4>;
    			ti,hwmods = "mailbox3";
    			#mbox-cells = <0x1>;
    			ti,mbox-num-users = <0x4>;
    			ti,mbox-num-fifos = <0xc>;
    			status = "disabled";
    		};
    
    		mailbox@4883e000 {
    			compatible = "ti,omap4-mailbox";
    			reg = <0x4883e000 0x200>;
    			interrupts = <0x0 0xf5 0x4 0x0 0xf6 0x4 0x0 0xf7 0x4 0x0 0xf8 0x4>;
    			ti,hwmods = "mailbox4";
    			#mbox-cells = <0x1>;
    			ti,mbox-num-users = <0x4>;
    			ti,mbox-num-fifos = <0xc>;
    			status = "disabled";
    		};
    
    		mailbox@48840000 {
    			compatible = "ti,omap4-mailbox";
    			reg = <0x48840000 0x200>;
    			interrupts = <0x0 0xf9 0x4 0x0 0xfa 0x4 0x0 0xfb 0x4 0x0 0xfc 0x4>;
    			ti,hwmods = "mailbox5";
    			#mbox-cells = <0x1>;
    			ti,mbox-num-users = <0x4>;
    			ti,mbox-num-fifos = <0xc>;
    			status = "okay";
    			phandle = <0x93>;
    
    			mbox_ipu1_ipc3x {
    				ti,mbox-tx = <0x6 0x2 0x2>;
    				ti,mbox-rx = <0x4 0x2 0x2>;
    				status = "okay";
    				phandle = <0x94>;
    			};
    
    			mbox_dsp1_ipc3x {
    				ti,mbox-tx = <0x5 0x2 0x2>;
    				ti,mbox-rx = <0x1 0x2 0x2>;
    				status = "okay";
    				phandle = <0xa3>;
    			};
    		};
    
    		mailbox@48842000 {
    			compatible = "ti,omap4-mailbox";
    			reg = <0x48842000 0x200>;
    			interrupts = <0x0 0xfd 0x4 0x0 0xfe 0x4 0x0 0xff 0x4 0x0 0x100 0x4>;
    			ti,hwmods = "mailbox6";
    			#mbox-cells = <0x1>;
    			ti,mbox-num-users = <0x4>;
    			ti,mbox-num-fifos = <0xc>;
    			status = "okay";
    			phandle = <0x9b>;
    
    			mbox_ipu2_ipc3x {
    				ti,mbox-tx = <0x6 0x2 0x2>;
    				ti,mbox-rx = <0x4 0x2 0x2>;
    				status = "okay";
    				phandle = <0x9c>;
    			};
    
    			mbox_dsp2_ipc3x {
    				ti,mbox-tx = <0x5 0x2 0x2>;
    				ti,mbox-rx = <0x1 0x2 0x2>;
    				status = "okay";
    				phandle = <0xd5>;
    			};
    		};
    
    		mailbox@48844000 {
    			compatible = "ti,omap4-mailbox";
    			reg = <0x48844000 0x200>;
    			interrupts = <0x0 0x101 0x4 0x0 0x102 0x4 0x0 0x103 0x4 0x0 0x104 0x4>;
    			ti,hwmods = "mailbox7";
    			#mbox-cells = <0x1>;
    			ti,mbox-num-users = <0x4>;
    			ti,mbox-num-fifos = <0xc>;
    			status = "disabled";
    		};
    
    		mailbox@48846000 {
    			compatible = "ti,omap4-mailbox";
    			reg = <0x48846000 0x200>;
    			interrupts = <0x0 0x105 0x4 0x0 0x106 0x4 0x0 0x107 0x4 0x0 0x108 0x4>;
    			ti,hwmods = "mailbox8";
    			#mbox-cells = <0x1>;
    			ti,mbox-num-users = <0x4>;
    			ti,mbox-num-fifos = <0xc>;
    			status = "disabled";
    		};
    
    		mailbox@4885e000 {
    			compatible = "ti,omap4-mailbox";
    			reg = <0x4885e000 0x200>;
    			interrupts = <0x0 0x109 0x4 0x0 0x10a 0x4 0x0 0x10b 0x4 0x0 0x10c 0x4>;
    			ti,hwmods = "mailbox9";
    			#mbox-cells = <0x1>;
    			ti,mbox-num-users = <0x4>;
    			ti,mbox-num-fifos = <0xc>;
    			status = "disabled";
    		};
    
    		mailbox@48860000 {
    			compatible = "ti,omap4-mailbox";
    			reg = <0x48860000 0x200>;
    			interrupts = <0x0 0x10d 0x4 0x0 0x10e 0x4 0x0 0x10f 0x4 0x0 0x110 0x4>;
    			ti,hwmods = "mailbox10";
    			#mbox-cells = <0x1>;
    			ti,mbox-num-users = <0x4>;
    			ti,mbox-num-fifos = <0xc>;
    			status = "disabled";
    		};
    
    		mailbox@48862000 {
    			compatible = "ti,omap4-mailbox";
    			reg = <0x48862000 0x200>;
    			interrupts = <0x0 0x111 0x4 0x0 0x112 0x4 0x0 0x113 0x4 0x0 0x114 0x4>;
    			ti,hwmods = "mailbox11";
    			#mbox-cells = <0x1>;
    			ti,mbox-num-users = <0x4>;
    			ti,mbox-num-fifos = <0xc>;
    			status = "disabled";
    		};
    
    		mailbox@48864000 {
    			compatible = "ti,omap4-mailbox";
    			reg = <0x48864000 0x200>;
    			interrupts = <0x0 0x115 0x4 0x0 0x116 0x4 0x0 0x117 0x4 0x0 0x118 0x4>;
    			ti,hwmods = "mailbox12";
    			#mbox-cells = <0x1>;
    			ti,mbox-num-users = <0x4>;
    			ti,mbox-num-fifos = <0xc>;
    			status = "disabled";
    		};
    
    		mailbox@48802000 {
    			compatible = "ti,omap4-mailbox";
    			reg = <0x48802000 0x200>;
    			interrupts = <0x0 0x17b 0x4 0x0 0x17c 0x4 0x0 0x17d 0x4 0x0 0x17e 0x4>;
    			ti,hwmods = "mailbox13";
    			#mbox-cells = <0x1>;
    			ti,mbox-num-users = <0x4>;
    			ti,mbox-num-fifos = <0xc>;
    			status = "disabled";
    		};
    
    		timer@4ae18000 {
    			compatible = "ti,omap5430-timer";
    			reg = <0x4ae18000 0x80>;
    			interrupts = <0x0 0x20 0x4>;
    			ti,hwmods = "timer1";
    			ti,timer-alwon;
    			clock-names = "fck";
    			clocks = <0x8f 0x20 0x18>;
    		};
    
    		timer@48032000 {
    			compatible = "ti,omap5430-timer";
    			reg = <0x48032000 0x80>;
    			interrupts = <0x0 0x21 0x4>;
    			ti,hwmods = "timer2";
    			clocks = <0x57 0x38 0x18>;
    			clock-names = "fck";
    		};
    
    		timer@48034000 {
    			compatible = "ti,omap5430-timer";
    			reg = <0x48034000 0x80>;
    			interrupts = <0x0 0x22 0x4>;
    			ti,hwmods = "timer3";
    			clocks = <0x57 0x40 0x18>;
    			clock-names = "fck";
    			phandle = <0x9d>;
    		};
    
    		timer@48036000 {
    			compatible = "ti,omap5430-timer";
    			reg = <0x48036000 0x80>;
    			interrupts = <0x0 0x23 0x4>;
    			ti,hwmods = "timer4";
    			clocks = <0x57 0x48 0x18>;
    			clock-names = "fck";
    			phandle = <0x9e>;
    		};
    
    		timer@48820000 {
    			compatible = "ti,omap5430-timer";
    			reg = <0x48820000 0x80>;
    			interrupts = <0x0 0x24 0x4>;
    			ti,hwmods = "timer5";
    			clocks = <0x90 0x18 0x18>;
    			clock-names = "fck";
    			phandle = <0xa4>;
    		};
    
    		timer@48822000 {
    			compatible = "ti,omap5430-timer";
    			reg = <0x48822000 0x80>;
    			interrupts = <0x0 0x25 0x4>;
    			ti,hwmods = "timer6";
    			clocks = <0x90 0x20 0x18>;
    			clock-names = "fck";
    			phandle = <0xd6>;
    		};
    
    		timer@48824000 {
    			compatible = "ti,omap5430-timer";
    			reg = <0x48824000 0x80>;
    			interrupts = <0x0 0x26 0x4>;
    			ti,hwmods = "timer7";
    			clocks = <0x90 0x28 0x18>;
    			clock-names = "fck";
    			phandle = <0x97>;
    		};
    
    		timer@48826000 {
    			compatible = "ti,omap5430-timer";
    			reg = <0x48826000 0x80>;
    			interrupts = <0x0 0x27 0x4>;
    			ti,hwmods = "timer8";
    			clocks = <0x90 0x30 0x18>;
    			clock-names = "fck";
    			phandle = <0x98>;
    		};
    
    		timer@4803e000 {
    			compatible = "ti,omap5430-timer";
    			reg = <0x4803e000 0x80>;
    			interrupts = <0x0 0x28 0x4>;
    			ti,hwmods = "timer9";
    			clocks = <0x57 0x50 0x18>;
    			clock-names = "fck";
    			phandle = <0x9f>;
    		};
    
    		timer@48086000 {
    			compatible = "ti,omap5430-timer";
    			reg = <0x48086000 0x80>;
    			interrupts = <0x0 0x29 0x4>;
    			ti,hwmods = "timer10";
    			clocks = <0x57 0x28 0x18>;
    			clock-names = "fck";
    			phandle = <0xa5>;
    		};
    
    		timer@48088000 {
    			compatible = "ti,omap5430-timer";
    			reg = <0x48088000 0x80>;
    			interrupts = <0x0 0x2a 0x4>;
    			ti,hwmods = "timer11";
    			clocks = <0x57 0x30 0x18>;
    			clock-names = "fck";
    			phandle = <0x95>;
    		};
    
    		timer@4ae20000 {
    			compatible = "ti,omap5430-timer";
    			reg = <0x4ae20000 0x80>;
    			interrupts = <0x0 0x5a 0x4>;
    			ti,hwmods = "timer12";
    			ti,timer-alwon;
    			ti,timer-secure;
    			clocks = <0x8f 0x28 0x18>;
    			clock-names = "fck";
    		};
    
    		timer@48828000 {
    			compatible = "ti,omap5430-timer";
    			reg = <0x48828000 0x80>;
    			interrupts = <0x0 0x153 0x4>;
    			ti,hwmods = "timer13";
    			clocks = <0x57 0xc8 0x18>;
    			clock-names = "fck";
    			phandle = <0xd7>;
    		};
    
    		timer@4882a000 {
    			compatible = "ti,omap5430-timer";
    			reg = <0x4882a000 0x80>;
    			interrupts = <0x0 0x154 0x4>;
    			ti,hwmods = "timer14";
    			clocks = <0x57 0xd0 0x18>;
    			clock-names = "fck";
    			phandle = <0x96>;
    		};
    
    		timer@4882c000 {
    			compatible = "ti,omap5430-timer";
    			reg = <0x4882c000 0x80>;
    			interrupts = <0x0 0x155 0x4>;
    			ti,hwmods = "timer15";
    			clocks = <0x57 0xd8 0x18>;
    			clock-names = "fck";
    		};
    
    		timer@4882e000 {
    			compatible = "ti,omap5430-timer";
    			reg = <0x4882e000 0x80>;
    			interrupts = <0x0 0x156 0x4>;
    			ti,hwmods = "timer16";
    			clocks = <0x57 0x130 0x18>;
    			clock-names = "fck";
    			assigned-clocks = <0x57 0x130 0x18>;
    			assigned-clock-parents = <0x91>;
    		};
    
    		wdt@4ae14000 {
    			compatible = "ti,omap3-wdt";
    			reg = <0x4ae14000 0x80>;
    			interrupts = <0x0 0x4b 0x4>;
    			ti,hwmods = "wd_timer2";
    		};
    
    		spinlock@4a0f6000 {
    			compatible = "ti,omap4-hwspinlock";
    			reg = <0x4a0f6000 0x1000>;
    			ti,hwmods = "spinlock";
    			#hwlock-cells = <0x1>;
    		};
    
    		dmm@4e000000 {
    			compatible = "ti,omap5-dmm";
    			reg = <0x4e000000 0x800>;
    			interrupts = <0x0 0x6c 0x4>;
    			ti,hwmods = "dmm";
    		};
    
    		ipu@58820000 {
    			compatible = "ti,dra7-ipu";
    			reg = <0x58820000 0x10000>;
    			reg-names = "l2ram";
    			ti,hwmods = "ipu1";
    			iommus = <0x92>;
    			ti,rproc-standby-info = <0x4a005520>;
    			status = "okay";
    			mboxes = <0x93 0x94>;
    			timers = <0x95 0x96>;
    			watchdog-timers = <0x97 0x98>;
    			memory-region = <0x99>;
    		};
    
    		ipu@55020000 {
    			compatible = "ti,dra7-ipu";
    			reg = <0x55020000 0x10000>;
    			reg-names = "l2ram";
    			ti,hwmods = "ipu2";
    			iommus = <0x9a>;
    			ti,rproc-standby-info = <0x4a008920>;
    			status = "okay";
    			mboxes = <0x9b 0x9c>;
    			timers = <0x9d>;
    			watchdog-timers = <0x9e 0x9f>;
    			memory-region = <0xa0>;
    		};
    
    		dsp@40800000 {
    			compatible = "ti,dra7-dsp";
    			reg = <0x40800000 0x48000 0x40e00000 0x8000 0x40f00000 0x8000>;
    			reg-names = "l2ram", "l1pram", "l1dram";
    			ti,hwmods = "dsp1";
    			syscon-bootreg = <0x9 0x55c>;
    			iommus = <0xa1 0xa2>;
    			ti,rproc-standby-info = <0x4a005420>;
    			status = "okay";
    			mboxes = <0x93 0xa3>;
    			timers = <0xa4>;
    			watchdog-timers = <0xa5>;
    			memory-region = <0xa6>;
    		};
    
    		i2c@48070000 {
    			compatible = "ti,omap4-i2c";
    			reg = <0x48070000 0x100>;
    			interrupts = <0x0 0x33 0x4>;
    			#address-cells = <0x1>;
    			#size-cells = <0x0>;
    			ti,hwmods = "i2c1";
    			status = "okay";
    			clock-frequency = <0x61a80>;
    
    			tps659038@58 {
    				compatible = "ti,tps659038";
    				reg = <0x58>;
    				interrupt-parent = <0xa7>;
    				interrupts = <0x0 0x8>;
    				#interrupt-cells = <0x2>;
    				interrupt-controller;
    				ti,system-power-controller;
    				ti,palmas-override-powerhold;
    				phandle = <0xa8>;
    
    				tps659038_pmic {
    					compatible = "ti,tps659038-pmic";
    
    					regulators {
    
    						smps12 {
    							regulator-name = "smps12";
    							regulator-min-microvolt = <0xcf850>;
    							regulator-max-microvolt = <0x1312d0>;
    							regulator-always-on;
    							regulator-boot-on;
    							phandle = <0x6>;
    						};
    
    						smps3 {
    							regulator-name = "smps3";
    							regulator-min-microvolt = <0x149970>;
    							regulator-max-microvolt = <0x149970>;
    							regulator-always-on;
    							regulator-boot-on;
    							phandle = <0xe2>;
    						};
    
    						smps45 {
    							regulator-name = "smps45";
    							regulator-min-microvolt = <0xcf850>;
    							regulator-max-microvolt = <0x1312d0>;
    							regulator-always-on;
    							regulator-boot-on;
    						};
    
    						smps6 {
    							regulator-name = "smps6";
    							regulator-min-microvolt = <0xcf850>;
    							regulator-max-microvolt = <0x118c30>;
    							regulator-always-on;
    							regulator-boot-on;
    						};
    
    						smps8 {
    							regulator-name = "smps8";
    							regulator-min-microvolt = <0x1b7740>;
    							regulator-max-microvolt = <0x1b7740>;
    							regulator-always-on;
    							regulator-boot-on;
    						};
    
    						ldo1 {
    							regulator-name = "ldo1";
    							regulator-min-microvolt = <0x1b7740>;
    							regulator-max-microvolt = <0x325aa0>;
    							regulator-boot-on;
    							regulator-always-on;
    							phandle = <0xb1>;
    						};
    
    						ldo2 {
    							regulator-name = "ldo2";
    							regulator-min-microvolt = <0x325aa0>;
    							regulator-max-microvolt = <0x325aa0>;
    							regulator-always-on;
    							regulator-boot-on;
    						};
    
    						ldo3 {
    							regulator-name = "ldo3";
    							regulator-min-microvolt = <0x1b7740>;
    							regulator-max-microvolt = <0x1b7740>;
    							regulator-always-on;
    							regulator-boot-on;
    						};
    
    						ldo4 {
    							regulator-name = "ldo4";
    							regulator-min-microvolt = <0x1b7740>;
    							regulator-max-microvolt = <0x1b7740>;
    							regulator-always-on;
    							regulator-boot-on;
    							phandle = <0xcd>;
    						};
    
    						ldo9 {
    							regulator-name = "ldo9";
    							regulator-min-microvolt = <0x100590>;
    							regulator-max-microvolt = <0x100590>;
    							regulator-always-on;
    							regulator-boot-on;
    						};
    
    						ldoln {
    							regulator-name = "ldoln";
    							regulator-min-microvolt = <0x1b7740>;
    							regulator-max-microvolt = <0x1b7740>;
    							regulator-always-on;
    							regulator-boot-on;
    							phandle = <0xcc>;
    						};
    
    						ldousb {
    							regulator-name = "ldousb";
    							regulator-min-microvolt = <0x325aa0>;
    							regulator-max-microvolt = <0x325aa0>;
    							regulator-boot-on;
    							phandle = <0xbb>;
    						};
    
    						regen1 {
    							regulator-name = "regen1";
    							regulator-boot-on;
    							regulator-always-on;
    							phandle = <0xe1>;
    						};
    					};
    				};
    
    				tps659038_rtc {
    					compatible = "ti,palmas-rtc";
    					interrupt-parent = <0xa8>;
    					interrupts = <0x8 0x2>;
    					wakeup-source;
    				};
    
    				tps659038_pwr_button {
    					compatible = "ti,palmas-pwrbutton";
    					interrupt-parent = <0xa8>;
    					interrupts = <0x1 0x2>;
    					wakeup-source;
    					ti,palmas-long-press-seconds = <0xc>;
    				};
    
    				tps659038_gpio {
    					compatible = "ti,palmas-gpio";
    					gpio-controller;
    					#gpio-cells = <0x2>;
    					phandle = <0xe3>;
    				};
    
    				tps659038_usb {
    					compatible = "ti,palmas-usb-vid";
    					ti,enable-vbus-detection;
    					vbus-gpio = <0xa9 0x15 0x0>;
    					phandle = <0xc1>;
    				};
    			};
    
    			tmp102@48 {
    				compatible = "ti,tmp102";
    				reg = <0x48>;
    				interrupt-parent = <0xaa>;
    				interrupts = <0x10 0x8>;
    				#thermal-sensor-cells = <0x1>;
    				phandle = <0xde>;
    			};
    
    			tlv320aic3104@18 {
    				#sound-dai-cells = <0x0>;
    				compatible = "ti,tlv320aic3104";
    				reg = <0x18>;
    				assigned-clocks = <0x4e>;
    				assigned-clock-parents = <0x6d>;
    				status = "okay";
    				adc-settle-ms = <0x28>;
    				AVDD-supply = <0xab>;
    				IOVDD-supply = <0xab>;
    				DRVDD-supply = <0xab>;
    				DVDD-supply = <0xac>;
    				phandle = <0xe9>;
    			};
    
    			eeprom@50 {
    				compatible = "atmel,24c32";
    				reg = <0x50>;
    			};
    		};
    
    		i2c@48072000 {
    			compatible = "ti,omap4-i2c";
    			reg = <0x48072000 0x100>;
    			interrupts = <0x0 0x34 0x4>;
    			#address-cells = <0x1>;
    			#size-cells = <0x0>;
    			ti,hwmods = "i2c2";
    			status = "disabled";
    		};
    
    		i2c@48060000 {
    			compatible = "ti,omap4-i2c";
    			reg = <0x48060000 0x100>;
    			interrupts = <0x0 0x38 0x4>;
    			#address-cells = <0x1>;
    			#size-cells = <0x0>;
    			ti,hwmods = "i2c3";
    			status = "okay";
    			clock-frequency = <0x61a80>;
    
    			rtc@6f {
    				compatible = "microchip,mcp7941x";
    				reg = <0x6f>;
    				interrupts-extended = <0x1 0x0 0x2 0x1 0x8e 0x424>;
    				interrupt-names = "irq", "wakeup";
    				vcc-supply = <0xab>;
    				wakeup-source;
    			};
    		};
    
    		i2c@4807a000 {
    			compatible = "ti,omap4-i2c";
    			reg = <0x4807a000 0x100>;
    			interrupts = <0x0 0x39 0x4>;
    			#address-cells = <0x1>;
    			#size-cells = <0x0>;
    			ti,hwmods = "i2c4";
    			status = "disabled";
    		};
    
    		i2c@4807c000 {
    			compatible = "ti,omap4-i2c";
    			reg = <0x4807c000 0x100>;
    			interrupts = <0x0 0x37 0x4>;
    			#address-cells = <0x1>;
    			#size-cells = <0x0>;
    			ti,hwmods = "i2c5";
    			status = "disabled";
    		};
    
    		mmc@4809c000 {
    			compatible = "ti,dra7-sdhci";
    			reg = <0x4809c000 0x400>;
    			interrupts = <0x0 0x4e 0x4>;
    			ti,hwmods = "mmc1";
    			status = "okay";
    			pbias-supply = <0xad>;
    			max-frequency = <0xb71b000>;
    			mmc-ddr-1_8v;
    			mmc-ddr-3_3v;
    			pinctrl-names = "default", "hs";
    			pinctrl-0 = <0xae>;
    			bus-width = <0x4>;
    			cd-gpios = <0xaf 0x1b 0x1>;
    			pinctrl-1 = <0xb0>;
    			vmmc-supply = <0xb1>;
    			no-1-8-v;
    		};
    
    		1w@480b2000 {
    			compatible = "ti,omap3-1w";
    			reg = <0x480b2000 0x1000>;
    			interrupts = <0x0 0x35 0x4>;
    			ti,hwmods = "hdq1w";
    		};
    
    		mmc@480b4000 {
    			compatible = "ti,dra7-sdhci";
    			reg = <0x480b4000 0x400>;
    			interrupts = <0x0 0x51 0x4>;
    			ti,hwmods = "mmc2";
    			status = "disabled";
    			max-frequency = <0xb71b000>;
    			sdhci-caps-mask = <0x7 0x0>;
    			mmc-hs200-1_8v;
    			mmc-ddr-1_8v;
    			mmc-ddr-3_3v;
    			pinctrl-names = "default";
    			pinctrl-0 = <0xb2>;
    			vmmc-supply = <0xab>;
    			vqmmc-supply = <0xab>;
    			bus-width = <0x8>;
    			non-removable;
    			no-1-8-v;
    		};
    
    		mmc@480ad000 {
    			compatible = "ti,dra7-sdhci";
    			reg = <0x480ad000 0x400>;
    			interrupts = <0x0 0x59 0x4>;
    			ti,hwmods = "mmc3";
    			status = "disabled";
    			max-frequency = <0x3d09000>;
    			sdhci-caps-mask = <0x0 0x400000>;
    		};
    
    		mmc@480d1000 {
    			compatible = "ti,dra7-sdhci";
    			reg = <0x480d1000 0x400>;
    			interrupts = <0x0 0x5b 0x4>;
    			ti,hwmods = "mmc4";
    			status = "disabled";
    			max-frequency = <0xb71b000>;
    			sdhci-caps-mask = <0x0 0x400000>;
    		};
    
    		mmu@40d01000 {
    			compatible = "ti,dra7-dsp-iommu";
    			reg = <0x40d01000 0x100>;
    			interrupts = <0x0 0x17 0x4>;
    			ti,hwmods = "mmu0_dsp1";
    			#iommu-cells = <0x0>;
    			ti,syscon-mmuconfig = <0xb3 0x0>;
    			phandle = <0xa1>;
    		};
    
    		mmu@40d02000 {
    			compatible = "ti,dra7-dsp-iommu";
    			reg = <0x40d02000 0x100>;
    			interrupts = <0x0 0x91 0x4>;
    			ti,hwmods = "mmu1_dsp1";
    			#iommu-cells = <0x0>;
    			ti,syscon-mmuconfig = <0xb3 0x1>;
    			phandle = <0xa2>;
    		};
    
    		mmu@58882000 {
    			compatible = "ti,dra7-iommu";
    			reg = <0x58882000 0x100>;
    			interrupts = <0x0 0x18b 0x4>;
    			ti,hwmods = "mmu_ipu1";
    			#iommu-cells = <0x0>;
    			ti,iommu-bus-err-back;
    			phandle = <0x92>;
    		};
    
    		mmu@55082000 {
    			compatible = "ti,dra7-iommu";
    			reg = <0x55082000 0x100>;
    			interrupts = <0x0 0x18c 0x4>;
    			ti,hwmods = "mmu_ipu2";
    			#iommu-cells = <0x0>;
    			ti,iommu-bus-err-back;
    			phandle = <0x9a>;
    		};
    
    		pruss-soc-bus@4b226004 {
    			compatible = "ti,am5728-pruss-soc-bus";
    			reg = <0x4b226004 0x4>;
    			ti,hwmods = "pruss1";
    			#address-cells = <0x1>;
    			#size-cells = <0x1>;
    			ranges;
    			status = "okay";
    
    			pruss@4b200000 {
    				compatible = "ti,am5728-pruss";
    				reg = <0x4b200000 0x80000>;
    				interrupts = <0x0 0xba 0x4 0x0 0xbb 0x4 0x0 0xbc 0x4 0x0 0xbd 0x4 0x0 0xbe 0x4 0x0 0xbf 0x4 0x0 0xc0 0x4 0x0 0xc1 0x4>;
    				interrupt-names = "host2", "host3", "host4", "host5", "host6", "host7", "host8", "host9";
    				#address-cells = <0x1>;
    				#size-cells = <0x1>;
    				ranges;
    				status = "okay";
    
    				memories@4b200000 {
    					reg = <0x4b200000 0x2000 0x4b202000 0x2000 0x4b210000 0x8000 0x4b22e000 0x31c 0x4b230000 0x60>;
    					reg-names = "dram0", "dram1", "shrdram2", "iep", "ecap";
    				};
    
    				cfg@4b226000 {
    					compatible = "syscon";
    					reg = <0x4b226000 0x2000>;
    				};
    
    				mii-rt@4b232000 {
    					compatible = "syscon";
    					reg = <0x4b232000 0x58>;
    				};
    
    				interrupt-controller@4b220000 {
    					compatible = "ti,am5728-pruss-intc";
    					reg = <0x4b220000 0x2000>;
    					interrupt-controller;
    					#interrupt-cells = <0x1>;
    					phandle = <0xb4>;
    				};
    
    				pru@4b234000 {
    					compatible = "ti,am5728-pru";
    					reg = <0x4b234000 0x3000 0x4b222000 0x400 0x4b222400 0x100>;
    					reg-names = "iram", "control", "debug";
    					firmware-name = "am57xx-pru1_0-fw";
    					interrupt-parent = <0xb4>;
    					interrupts = <0x10 0x11>;
    					interrupt-names = "vring", "kick";
    				};
    
    				pru@4b238000 {
    					compatible = "ti,am5728-pru";
    					reg = <0x4b238000 0x3000 0x4b224000 0x400 0x4b224400 0x100>;
    					reg-names = "iram", "control", "debug";
    					firmware-name = "am57xx-pru1_1-fw";
    					interrupt-parent = <0xb4>;
    					interrupts = <0x12 0x13>;
    					interrupt-names = "vring", "kick";
    				};
    
    				mdio@4b232400 {
    					compatible = "ti,davinci_mdio";
    					reg = <0x4b232400 0x90>;
    					#address-cells = <0x1>;
    					#size-cells = <0x0>;
    					clocks = <0xb5>;
    					clock-names = "fck";
    					bus_freq = <0xf4240>;
    					status = "disabled";
    				};
    			};
    		};
    
    		pruss-soc-bus@4b2a6004 {
    			compatible = "ti,am5728-pruss-soc-bus";
    			reg = <0x4b2a6004 0x4>;
    			ti,hwmods = "pruss2";
    			#address-cells = <0x1>;
    			#size-cells = <0x1>;
    			ranges;
    			status = "okay";
    
    			pruss@4b280000 {
    				compatible = "ti,am5728-pruss";
    				reg = <0x4b280000 0x80000>;
    				interrupts = <0x0 0xc4 0x4 0x0 0xc5 0x4 0x0 0xc6 0x4 0x0 0xc7 0x4 0x0 0xc8 0x4 0x0 0xc9 0x4 0x0 0xca 0x4 0x0 0xcb 0x4>;
    				interrupt-names = "host2", "host3", "host4", "host5", "host6", "host7", "host8", "host9";
    				#address-cells = <0x1>;
    				#size-cells = <0x1>;
    				ranges;
    				status = "okay";
    
    				memories@4b280000 {
    					reg = <0x4b280000 0x2000 0x4b282000 0x2000 0x4b290000 0x8000 0x4b2ae000 0x31c 0x4b2b0000 0x60>;
    					reg-names = "dram0", "dram1", "shrdram2", "iep", "ecap";
    				};
    
    				cfg@4b2a6000 {
    					compatible = "syscon";
    					reg = <0x4b2a6000 0x2000>;
    				};
    
    				mii-rt@4b2b2000 {
    					compatible = "syscon";
    					reg = <0x4b2b2000 0x58>;
    				};
    
    				interrupt-controller@4b2a0000 {
    					compatible = "ti,am5728-pruss-intc";
    					reg = <0x4b2a0000 0x2000>;
    					interrupt-controller;
    					#interrupt-cells = <0x1>;
    					phandle = <0xb6>;
    				};
    
    				pru@4b2b4000 {
    					compatible = "ti,am5728-pru";
    					reg = <0x4b2b4000 0x3000 0x4b2a2000 0x400 0x4b2a2400 0x100>;
    					reg-names = "iram", "control", "debug";
    					firmware-name = "am57xx-pru2_0-fw";
    					interrupt-parent = <0xb6>;
    					interrupts = <0x10 0x11>;
    					interrupt-names = "vring", "kick";
    				};
    
    				pru@4b2b8000 {
    					compatible = "ti,am5728-pru";
    					reg = <0x4b2b8000 0x3000 0x4b2a4000 0x400 0x4b2a4400 0x100>;
    					reg-names = "iram", "control", "debug";
    					firmware-name = "am57xx-pru2_1-fw";
    					interrupt-parent = <0xb6>;
    					interrupts = <0x12 0x13>;
    					interrupt-names = "vring", "kick";
    				};
    
    				mdio@4b2b2400 {
    					compatible = "ti,davinci_mdio";
    					reg = <0x4b2b2400 0x90>;
    					#address-cells = <0x1>;
    					#size-cells = <0x0>;
    					clocks = <0xb5>;
    					clock-names = "fck";
    					bus_freq = <0xf4240>;
    					status = "disabled";
    				};
    			};
    		};
    
    		regulator-abb-mpu {
    			compatible = "ti,abb-v3";
    			regulator-name = "abb_mpu";
    			#address-cells = <0x0>;
    			#size-cells = <0x0>;
    			clocks = <0x11>;
    			ti,settling-time = <0x32>;
    			ti,clock-cycles = <0x10>;
    			reg = <0x4ae07ddc 0x4 0x4ae07de0 0x4 0x4ae06014 0x4 0x4a003b20 0xc 0x4ae0c158 0x4>;
    			reg-names = "setup-address", "control-address", "int-address", "efuse-address", "ldo-address";
    			ti,tranxdone-status-mask = <0x80>;
    			ti,ldovbb-override-mask = <0x400>;
    			ti,ldovbb-vset-mask = <0x1f>;
    			ti,abb_info = <0x102ca0 0x0 0x0 0x0 0x2000000 0x1f00000 0x11b340 0x0 0x4 0x0 0x2000000 0x1f00000 0x127690 0x0 0x8 0x0 0x2000000 0x1f00000>;
    			phandle = <0x5>;
    		};
    
    		regulator-abb-ivahd {
    			compatible = "ti,abb-v3";
    			regulator-name = "abb_ivahd";
    			#address-cells = <0x0>;
    			#size-cells = <0x0>;
    			clocks = <0x11>;
    			ti,settling-time = <0x32>;
    			ti,clock-cycles = <0x10>;
    			reg = <0x4ae07e34 0x4 0x4ae07e24 0x4 0x4ae06010 0x4 0x4a0025cc 0xc 0x4a002470 0x4>;
    			reg-names = "setup-address", "control-address", "int-address", "efuse-address", "ldo-address";
    			ti,tranxdone-status-mask = <0x40000000>;
    			ti,ldovbb-override-mask = <0x400>;
    			ti,ldovbb-vset-mask = <0x1f>;
    			ti,abb_info = <0x101918 0x0 0x0 0x0 0x2000000 0x1f00000 0x118c30 0x0 0x4 0x0 0x2000000 0x1f00000 0x1312d0 0x0 0x8 0x0 0x2000000 0x1f00000>;
    		};
    
    		regulator-abb-dspeve {
    			compatible = "ti,abb-v3";
    			regulator-name = "abb_dspeve";
    			#address-cells = <0x0>;
    			#size-cells = <0x0>;
    			clocks = <0x11>;
    			ti,settling-time = <0x32>;
    			ti,clock-cycles = <0x10>;
    			reg = <0x4ae07e30 0x4 0x4ae07e20 0x4 0x4ae06010 0x4 0x4a0025e0 0xc 0x4a00246c 0x4>;
    			reg-names = "setup-address", "control-address", "int-address", "efuse-address", "ldo-address";
    			ti,tranxdone-status-mask = <0x20000000>;
    			ti,ldovbb-override-mask = <0x400>;
    			ti,ldovbb-vset-mask = <0x1f>;
    			ti,abb_info = <0x101918 0x0 0x0 0x0 0x2000000 0x1f00000 0x118c30 0x0 0x4 0x0 0x2000000 0x1f00000 0x1312d0 0x0 0x8 0x0 0x2000000 0x1f00000>;
    		};
    
    		regulator-abb-gpu {
    			compatible = "ti,abb-v3";
    			regulator-name = "abb_gpu";
    			#address-cells = <0x0>;
    			#size-cells = <0x0>;
    			clocks = <0x11>;
    			ti,settling-time = <0x32>;
    			ti,clock-cycles = <0x10>;
    			reg = <0x4ae07de4 0x4 0x4ae07de8 0x4 0x4ae06010 0x4 0x4a003b08 0xc 0x4ae0c154 0x4>;
    			reg-names = "setup-address", "control-address", "int-address", "efuse-address", "ldo-address";
    			ti,tranxdone-status-mask = <0x10000000>;
    			ti,ldovbb-override-mask = <0x400>;
    			ti,ldovbb-vset-mask = <0x1f>;
    			ti,abb_info = <0x10a1d0 0x0 0x0 0x0 0x2000000 0x1f00000 0x127690 0x0 0x4 0x0 0x2000000 0x1f00000 0x138800 0x0 0x8 0x0 0x2000000 0x1f00000>;
    		};
    
    		spi@48098000 {
    			compatible = "ti,omap4-mcspi";
    			reg = <0x48098000 0x200>;
    			interrupts = <0x0 0x3c 0x4>;
    			#address-cells = <0x1>;
    			#size-cells = <0x0>;
    			ti,hwmods = "mcspi1";
    			ti,spi-num-cs = <0x4>;
    			dmas = <0x8d 0x23 0x8d 0x24 0x8d 0x25 0x8d 0x26 0x8d 0x27 0x8d 0x28 0x8d 0x29 0x8d 0x2a>;
    			dma-names = "tx0", "rx0", "tx1", "rx1", "tx2", "rx2", "tx3", "rx3";
    			status = "disabled";
    		};
    
    		spi@4809a000 {
    			compatible = "ti,omap4-mcspi";
    			reg = <0x4809a000 0x200>;
    			interrupts = <0x0 0x3d 0x4>;
    			#address-cells = <0x1>;
    			#size-cells = <0x0>;
    			ti,hwmods = "mcspi2";
    			ti,spi-num-cs = <0x2>;
    			dmas = <0x8d 0x2b 0x8d 0x2c 0x8d 0x2d 0x8d 0x2e>;
    			dma-names = "tx0", "rx0", "tx1", "rx1";
    			status = "disabled";
    		};
    
    		spi@480b8000 {
    			compatible = "ti,omap4-mcspi";
    			reg = <0x480b8000 0x200>;
    			interrupts = <0x0 0x56 0x4>;
    			#address-cells = <0x1>;
    			#size-cells = <0x0>;
    			ti,hwmods = "mcspi3";
    			ti,spi-num-cs = <0x2>;
    			dmas = <0x8d 0xf 0x8d 0x10>;
    			dma-names = "tx0", "rx0";
    			status = "disabled";
    		};
    
    		spi@480ba000 {
    			compatible = "ti,omap4-mcspi";
    			reg = <0x480ba000 0x200>;
    			interrupts = <0x0 0x2b 0x4>;
    			#address-cells = <0x1>;
    			#size-cells = <0x0>;
    			ti,hwmods = "mcspi4";
    			ti,spi-num-cs = <0x1>;
    			dmas = <0x8d 0x46 0x8d 0x47>;
    			dma-names = "tx0", "rx0";
    			status = "disabled";
    		};
    
    		qspi@4b300000 {
    			compatible = "ti,dra7xxx-qspi";
    			reg = <0x4b300000 0x100 0x5c000000 0x4000000>;
    			reg-names = "qspi_base", "qspi_mmap";
    			syscon-chipselects = <0x9 0x558>;
    			#address-cells = <0x1>;
    			#size-cells = <0x0>;
    			ti,hwmods = "qspi";
    			clocks = <0x57 0x138 0x19>;
    			clock-names = "fck";
    			num-cs = <0x4>;
    			interrupts = <0x0 0x157 0x4>;
    			status = "disabled";
    		};
    
    		ocp2scp@4a090000 {
    			compatible = "ti,omap-ocp2scp";
    			#address-cells = <0x1>;
    			#size-cells = <0x1>;
    			ranges;
    			reg = <0x4a090000 0x20>;
    			ti,hwmods = "ocp2scp3";
    
    			phy@4a096000 {
    				compatible = "ti,phy-pipe3-sata";
    				reg = <0x4a096000 0x80 0x4a096400 0x64 0x4a096800 0x40>;
    				reg-names = "phy_rx", "phy_tx", "pll_ctrl";
    				syscon-phy-power = <0x9 0x374>;
    				clocks = <0x11 0xb7 0x68 0x8>;
    				clock-names = "sysclk", "refclk";
    				syscon-pllreset = <0x9 0x3fc>;
    				#phy-cells = <0x0>;
    				phandle = <0xb9>;
    			};
    
    			pciephy@4a094000 {
    				compatible = "ti,phy-pipe3-pcie";
    				reg = <0x4a094000 0x80 0x4a094400 0x64>;
    				reg-names = "phy_rx", "phy_tx";
    				syscon-phy-power = <0x85 0x1c>;
    				syscon-pcs = <0x85 0x10>;
    				clocks = <0x3e 0x3f 0xb7 0x90 0x8 0xb7 0x90 0x9 0xb7 0x90 0xa 0xb8 0x11>;
    				clock-names = "dpll_ref", "dpll_ref_m2", "wkupclk", "refclk", "div-clk", "phy-div", "sysclk";
    				#phy-cells = <0x0>;
    				phandle = <0x84>;
    			};
    
    			pciephy@4a095000 {
    				compatible = "ti,phy-pipe3-pcie";
    				reg = <0x4a095000 0x80 0x4a095400 0x64>;
    				reg-names = "phy_rx", "phy_tx";
    				syscon-phy-power = <0x85 0x20>;
    				syscon-pcs = <0x85 0x10>;
    				clocks = <0x3e 0x3f 0xb7 0x98 0x8 0xb7 0x98 0x9 0xb7 0x98 0xa 0xb8 0x11>;
    				clock-names = "dpll_ref", "dpll_ref_m2", "wkupclk", "refclk", "div-clk", "phy-div", "sysclk";
    				#phy-cells = <0x0>;
    				status = "disabled";
    				phandle = <0x89>;
    			};
    		};
    
    		sata@4a141100 {
    			compatible = "snps,dwc-ahci";
    			reg = <0x4a140000 0x1100 0x4a141100 0x7>;
    			interrupts = <0x0 0x31 0x4>;
    			phys = <0xb9>;
    			phy-names = "sata-phy";
    			clocks = <0xb7 0x68 0x8>;
    			ti,hwmods = "sata";
    			ports-implemented = <0x1>;
    			status = "okay";
    		};
    
    		rtc@48838000 {
    			compatible = "ti,am3352-rtc";
    			reg = <0x48838000 0x100>;
    			interrupts = <0x0 0xd9 0x4 0x0 0xd9 0x4>;
    			ti,hwmods = "rtcss";
    			clocks = <0x50>;
    		};
    
    		ocp2scp@4a080000 {
    			compatible = "ti,omap-ocp2scp";
    			#address-cells = <0x1>;
    			#size-cells = <0x1>;
    			ranges;
    			reg = <0x4a080000 0x20>;
    			ti,hwmods = "ocp2scp1";
    
    			phy@4a084000 {
    				compatible = "ti,dra7x-usb2", "ti,omap-usb2";
    				reg = <0x4a084000 0x400>;
    				syscon-phy-power = <0x9 0x300>;
    				clocks = <0xba 0xb7 0xd0 0x8>;
    				clock-names = "wkupclk", "refclk";
    				#phy-cells = <0x0>;
    				phy-supply = <0xbb>;
    				phandle = <0xbf>;
    			};
    
    			phy@4a085000 {
    				compatible = "ti,dra7x-usb2-phy2", "ti,omap-usb2";
    				reg = <0x4a085000 0x400>;
    				syscon-phy-power = <0x9 0xe74>;
    				clocks = <0xbc 0xb7 0x20 0x8>;
    				clock-names = "wkupclk", "refclk";
    				#phy-cells = <0x0>;
    				phy-supply = <0xbb>;
    				phandle = <0xc2>;
    			};
    
    			phy@4a084400 {
    				compatible = "ti,omap-usb3";
    				reg = <0x4a084400 0x80 0x4a084800 0x64 0x4a084c00 0x40>;
    				reg-names = "phy_rx", "phy_tx", "pll_ctrl";
    				syscon-phy-power = <0x9 0x370>;
    				clocks = <0xbd 0x11 0xb7 0xd0 0x8>;
    				clock-names = "wkupclk", "sysclk", "refclk";
    				#phy-cells = <0x0>;
    				phandle = <0xc0>;
    			};
    		};
    
    		target-module@4a0dd000 {
    			compatible = "ti,sysc-omap4-sr", "ti,sysc";
    			ti,hwmods = "smartreflex_core";
    			reg = <0x4a0dd038 0x4>;
    			reg-names = "sysc";
    			ti,sysc-mask = <0x4000000>;
    			ti,sysc-sidle = <0x0 0x1 0x2 0x3>;
    			clocks = <0xbe 0x18 0x0>;
    			clock-names = "fck";
    			#address-cells = <0x1>;
    			#size-cells = <0x1>;
    			ranges = <0x0 0x4a0dd000 0x1000>;
    		};
    
    		target-module@4a0d9000 {
    			compatible = "ti,sysc-omap4-sr", "ti,sysc";
    			ti,hwmods = "smartreflex_mpu";
    			reg = <0x4a0d9038 0x4>;
    			reg-names = "sysc";
    			ti,sysc-mask = <0x4000000>;
    			ti,sysc-sidle = <0x0 0x1 0x2 0x3>;
    			clocks = <0xbe 0x8 0x0>;
    			clock-names = "fck";
    			#address-cells = <0x1>;
    			#size-cells = <0x1>;
    			ranges = <0x0 0x4a0d9000 0x1000>;
    		};
    
    		omap_dwc3_1@48880000 {
    			compatible = "ti,dwc3";
    			ti,hwmods = "usb_otg_ss1";
    			reg = <0x48880000 0x10000>;
    			interrupts = <0x0 0x48 0x4>;
    			#address-cells = <0x1>;
    			#size-cells = <0x1>;
    			utmi-mode = <0x2>;
    			ranges;
    
    			usb@48890000 {
    				compatible = "snps,dwc3";
    				reg = <0x48890000 0x17000>;
    				interrupts = <0x0 0x47 0x4 0x0 0x47 0x4 0x0 0x48 0x4>;
    				interrupt-names = "peripheral", "host", "otg";
    				phys = <0xbf 0xc0>;
    				phy-names = "usb2-phy", "usb3-phy";
    				maximum-speed = "super-speed";
    				dr_mode = "host";
    				snps,dis_u3_susphy_quirk;
    				snps,dis_u2_susphy_quirk;
    			};
    		};
    
    		omap_dwc3_2@488c0000 {
    			compatible = "ti,dwc3";
    			ti,hwmods = "usb_otg_ss2";
    			reg = <0x488c0000 0x10000>;
    			interrupts = <0x0 0x57 0x4>;
    			#address-cells = <0x1>;
    			#size-cells = <0x1>;
    			utmi-mode = <0x2>;
    			ranges;
    			extcon = <0xc1>;
    
    			usb@488d0000 {
    				compatible = "snps,dwc3";
    				reg = <0x488d0000 0x17000>;
    				interrupts = <0x0 0x49 0x4 0x0 0x49 0x4 0x0 0x57 0x4>;
    				interrupt-names = "peripheral", "host", "otg";
    				phys = <0xc2>;
    				phy-names = "usb2-phy";
    				maximum-speed = "high-speed";
    				dr_mode = "peripheral";
    				snps,dis_u3_susphy_quirk;
    				snps,dis_u2_susphy_quirk;
    				snps,dis_metastability_quirk;
    			};
    		};
    
    		omap_dwc3_3@48900000 {
    			compatible = "ti,dwc3";
    			ti,hwmods = "usb_otg_ss3";
    			reg = <0x48900000 0x10000>;
    			interrupts = <0x0 0x158 0x4>;
    			#address-cells = <0x1>;
    			#size-cells = <0x1>;
    			utmi-mode = <0x2>;
    			ranges;
    			status = "disabled";
    
    			usb@48910000 {
    				compatible = "snps,dwc3";
    				reg = <0x48910000 0x17000>;
    				interrupts = <0x0 0x58 0x4 0x0 0x58 0x4 0x0 0x158 0x4>;
    				interrupt-names = "peripheral", "host", "otg";
    				maximum-speed = "high-speed";
    				dr_mode = "otg";
    				snps,dis_u3_susphy_quirk;
    				snps,dis_u2_susphy_quirk;
    			};
    		};
    
    		elm@48078000 {
    			compatible = "ti,am3352-elm";
    			reg = <0x48078000 0xfc0>;
    			interrupts = <0x0 0x1 0x4>;
    			ti,hwmods = "elm";
    			status = "disabled";
    		};
    
    		gpmc@50000000 {
    			compatible = "ti,am3352-gpmc";
    			ti,hwmods = "gpmc";
    			reg = <0x50000000 0x37c>;
    			interrupts = <0x0 0xf 0x4>;
    			dmas = <0xc3 0x4 0x0>;
    			dma-names = "rxtx";
    			gpmc,num-cs = <0x8>;
    			gpmc,num-waitpins = <0x2>;
    			#address-cells = <0x2>;
    			#size-cells = <0x1>;
    			interrupt-controller;
    			#interrupt-cells = <0x2>;
    			gpio-controller;
    			#gpio-cells = <0x2>;
    			status = "disabled";
    		};
    
    		atl@4843c000 {
    			compatible = "ti,dra7-atl";
    			reg = <0x4843c000 0x3ff>;
    			ti,hwmods = "atl";
    			ti,provided-clocks = <0xc4 0xc5 0xc6 0xc7>;
    			clocks = <0x10 0x0 0x1a>;
    			clock-names = "fck";
    			status = "disabled";
    		};
    
    		mcasp@48460000 {
    			compatible = "ti,dra7-mcasp-audio";
    			ti,hwmods = "mcasp1";
    			reg = <0x48460000 0x2000 0x45800000 0x1000>;
    			reg-names = "mpu", "dat";
    			interrupts = <0x0 0x68 0x4 0x0 0x67 0x4>;
    			interrupt-names = "tx", "rx";
    			dmas = <0xc3 0x81 0x1 0xc3 0x80 0x1>;
    			dma-names = "tx", "rx";
    			clocks = <0x90 0x10 0x16 0x90 0x10 0x18 0x90 0x10 0x1c>;
    			clock-names = "fck", "ahclkx", "ahclkr";
    			status = "disabled";
    		};
    
    		mcasp@48464000 {
    			compatible = "ti,dra7-mcasp-audio";
    			ti,hwmods = "mcasp2";
    			reg = <0x48464000 0x2000 0x45c00000 0x1000>;
    			reg-names = "mpu", "dat";
    			interrupts = <0x0 0x95 0x4 0x0 0x94 0x4>;
    			interrupt-names = "tx", "rx";
    			dmas = <0xc3 0x83 0x1 0xc3 0x82 0x1>;
    			dma-names = "tx", "rx";
    			clocks = <0x57 0x160 0x16 0x57 0x160 0x18 0x57 0x160 0x1c>;
    			clock-names = "fck", "ahclkx", "ahclkr";
    			status = "disabled";
    		};
    
    		mcasp@48468000 {
    			compatible = "ti,dra7-mcasp-audio";
    			ti,hwmods = "mcasp3";
    			reg = <0x48468000 0x2000 0x46000000 0x1000>;
    			reg-names = "mpu", "dat";
    			interrupts = <0x0 0x97 0x4 0x0 0x96 0x4>;
    			interrupt-names = "tx", "rx";
    			dmas = <0xc3 0x85 0x1 0xc3 0x84 0x1>;
    			dma-names = "tx", "rx";
    			clocks = <0x57 0x168 0x16 0x57 0x168 0x18>;
    			clock-names = "fck", "ahclkx";
    			status = "okay";
    			#sound-dai-cells = <0x0>;
    			assigned-clocks = <0x57 0x168 0x18>;
    			assigned-clock-parents = <0x60>;
    			op-mode = <0x0>;
    			tdm-slots = <0x2>;
    			serial-dir = <0x1 0x2 0x0 0x0>;
    			tx-num-evt = <0x20>;
    			rx-num-evt = <0x20>;
    			phandle = <0xe8>;
    		};
    
    		mcasp@4846c000 {
    			compatible = "ti,dra7-mcasp-audio";
    			ti,hwmods = "mcasp4";
    			reg = <0x4846c000 0x2000 0x48436000 0x1000>;
    			reg-names = "mpu", "dat";
    			interrupts = <0x0 0x99 0x4 0x0 0x98 0x4>;
    			interrupt-names = "tx", "rx";
    			dmas = <0xc3 0x87 0x1 0xc3 0x86 0x1>;
    			dma-names = "tx", "rx";
    			clocks = <0x57 0x198 0x16 0x57 0x198 0x18>;
    			clock-names = "fck", "ahclkx";
    			status = "disabled";
    		};
    
    		mcasp@48470000 {
    			compatible = "ti,dra7-mcasp-audio";
    			ti,hwmods = "mcasp5";
    			reg = <0x48470000 0x2000 0x4843a000 0x1000>;
    			reg-names = "mpu", "dat";
    			interrupts = <0x0 0x9b 0x4 0x0 0x9a 0x4>;
    			interrupt-names = "tx", "rx";
    			dmas = <0xc3 0x89 0x1 0xc3 0x88 0x1>;
    			dma-names = "tx", "rx";
    			clocks = <0x57 0x178 0x16 0x57 0x178 0x18>;
    			clock-names = "fck", "ahclkx";
    			status = "disabled";
    		};
    
    		mcasp@48474000 {
    			compatible = "ti,dra7-mcasp-audio";
    			ti,hwmods = "mcasp6";
    			reg = <0x48474000 0x2000 0x4844c000 0x1000>;
    			reg-names = "mpu", "dat";
    			interrupts = <0x0 0x9d 0x4 0x0 0x9c 0x4>;
    			interrupt-names = "tx", "rx";
    			dmas = <0xc3 0x8b 0x1 0xc3 0x8a 0x1>;
    			dma-names = "tx", "rx";
    			clocks = <0x57 0x204 0x16 0x57 0x204 0x18>;
    			clock-names = "fck", "ahclkx";
    			status = "disabled";
    		};
    
    		mcasp@48478000 {
    			compatible = "ti,dra7-mcasp-audio";
    			ti,hwmods = "mcasp7";
    			reg = <0x48478000 0x2000 0x48450000 0x1000>;
    			reg-names = "mpu", "dat";
    			interrupts = <0x0 0x9f 0x4 0x0 0x9e 0x4>;
    			interrupt-names = "tx", "rx";
    			dmas = <0xc3 0x8d 0x1 0xc3 0x8c 0x1>;
    			dma-names = "tx", "rx";
    			clocks = <0x57 0x208 0x16 0x57 0x208 0x18>;
    			clock-names = "fck", "ahclkx";
    			status = "disabled";
    		};
    
    		mcasp@4847c000 {
    			compatible = "ti,dra7-mcasp-audio";
    			ti,hwmods = "mcasp8";
    			reg = <0x4847c000 0x2000 0x48454000 0x1000>;
    			reg-names = "mpu", "dat";
    			interrupts = <0x0 0xa1 0x4 0x0 0xa0 0x4>;
    			interrupt-names = "tx", "rx";
    			dmas = <0xc3 0x8f 0x1 0xc3 0x8e 0x1>;
    			dma-names = "tx", "rx";
    			clocks = <0x57 0x190 0x16 0x57 0x190 0x18>;
    			clock-names = "fck", "ahclkx";
    			status = "disabled";
    		};
    
    		crossbar@4a002a48 {
    			compatible = "ti,irq-crossbar";
    			reg = <0x4a002a48 0x130>;
    			interrupt-controller;
    			interrupt-parent = <0x8>;
    			#interrupt-cells = <0x3>;
    			ti,max-irqs = <0xa0>;
    			ti,max-crossbar-sources = <0x190>;
    			ti,reg-size = <0x2>;
    			ti,irqs-reserved = <0x0 0x1 0x2 0x3 0x5 0x6 0x83 0x84>;
    			ti,irqs-skip = <0xa 0x85 0x8b 0x8c>;
    			ti,irqs-safe-map = <0x0>;
    			phandle = <0x1>;
    		};
    
    		ethernet@48484000 {
    			compatible = "ti,dra7-cpsw", "ti,cpsw";
    			ti,hwmods = "gmac";
    			clocks = <0xc8 0xb7 0xb0 0x19>;
    			clock-names = "fck", "cpts";
    			cpdma_channels = <0x8>;
    			ale_entries = <0x400>;
    			bd_ram_size = <0x2000>;
    			mac_control = <0x20>;
    			slaves = <0x2>;
    			active_slave = <0x0>;
    			cpts_clock_mult = <0x784cfe14>;
    			cpts_clock_shift = <0x1d>;
    			reg = <0x48484000 0x1000 0x48485200 0x2e00>;
    			#address-cells = <0x1>;
    			#size-cells = <0x1>;
    			ti,no-idle;
    			interrupts = <0x0 0x14e 0x4 0x0 0x14f 0x4 0x0 0x150 0x4 0x0 0x151 0x4>;
    			ranges;
    			syscon = <0x9>;
    			status = "okay";
    			dual_emac;
    
    			mdio@48485000 {
    				compatible = "ti,cpsw-mdio", "ti,davinci_mdio";
    				#address-cells = <0x1>;
    				#size-cells = <0x0>;
    				ti,hwmods = "davinci_mdio";
    				bus_freq = <0xf4240>;
    				reg = <0x48485000 0x100>;
    
    				ethernet-phy@1 {
    					reg = <0x1>;
    					phandle = <0xc9>;
    				};
    
    				ethernet-phy@2 {
    					reg = <0x2>;
    					status = "disabled";
    					max-speed = <0x64>;
    					phandle = <0xca>;
    				};
    			};
    
    			slave@48480200 {
    				mac-address = [00 00 00 00 00 00];
    				phy-handle = <0xc9>;
    				phy-mode = "rgmii";
    				dual_emac_res_vlan = <0x1>;
    			};
    
    			slave@48480300 {
    				mac-address = [00 00 00 00 00 00];
    				phy-handle = <0xca>;
    				phy-mode = "rgmii";
    				dual_emac_res_vlan = <0x2>;
    			};
    
    			cpsw-phy-sel@4a002554 {
    				compatible = "ti,dra7xx-cpsw-phy-sel";
    				reg = <0x4a002554 0x4>;
    				reg-names = "gmii-sel";
    			};
    		};
    
    		can@4ae3c000 {
    			compatible = "ti,dra7-d_can";
    			ti,hwmods = "dcan1";
    			reg = <0x4ae3c000 0x2000>;
    			syscon-raminit = <0x9 0x558 0x0>;
    			interrupts = <0x0 0xde 0x4>;
    			clocks = <0x8f 0x68 0x18>;
    			status = "disabled";
    		};
    
    		can@48480000 {
    			compatible = "ti,dra7-d_can";
    			ti,hwmods = "dcan2";
    			reg = <0x48480000 0x2000>;
    			syscon-raminit = <0x9 0x558 0x1>;
    			interrupts = <0x0 0xe1 0x4>;
    			clocks = <0x11>;
    			status = "disabled";
    		};
    
    		gpu@56000000 {
    			compatible = "ti,dra7-sgx544", "img,sgx544";
    			reg = <0x56000000 0x10000>;
    			reg-names = "gpu_ocp_base";
    			interrupts = <0x0 0x10 0x4>;
    			ti,hwmods = "gpu";
    			clocks = <0xa 0x53 0x54>;
    			clock-names = "iclk", "fclk1", "fclk2";
    			status = "disabled";
    		};
    
    		bb2d@59000000 {
    			compatible = "ti,dra7-bb2d";
    			reg = <0x59000000 0x700>;
    			interrupts = <0x0 0x78 0x4>;
    			ti,hwmods = "bb2d";
    			clocks = <0xcb 0x10 0x0>;
    			clock-names = "fck";
    			status = "okay";
    		};
    
    		dss@58000000 {
    			compatible = "ti,dra7-dss";
    			status = "ok";
    			ti,hwmods = "dss_core";
    			syscon-pll-ctrl = <0x9 0x538>;
    			#address-cells = <0x1>;
    			#size-cells = <0x1>;
    			ranges;
    			reg = <0x58000000 0x80 0x58004054 0x4 0x58004300 0x20 0x58009054 0x4 0x58009300 0x20>;
    			reg-names = "dss", "pll1_clkctrl", "pll1", "pll2_clkctrl", "pll2";
    			clocks = <0xcb 0x0 0x8 0xcb 0x0 0xc 0xcb 0x0 0xd>;
    			clock-names = "fck", "video1_clk", "video2_clk";
    			vdda_video-supply = <0xcc>;
    
    			dispc@58001000 {
    				compatible = "ti,dra7-dispc";
    				reg = <0x58001000 0x1000>;
    				interrupts = <0x0 0x14 0x4>;
    				ti,hwmods = "dss_dispc";
    				clocks = <0xcb 0x0 0x8>;
    				clock-names = "fck";
    				syscon-pol = <0x9 0x534>;
    			};
    
    			encoder@58060000 {
    				compatible = "ti,dra7-hdmi";
    				reg = <0x58040000 0x200 0x58040200 0x80 0x58040300 0x80 0x58060000 0x19000>;
    				reg-names = "wp", "pll", "phy", "core";
    				interrupts = <0x0 0x60 0x4>;
    				status = "ok";
    				ti,hwmods = "dss_hdmi";
    				clocks = <0xcb 0x0 0x9 0xcb 0x0 0xa>;
    				clock-names = "fck", "sys_clk";
    				dmas = <0x8d 0x4c>;
    				dma-names = "audio_tx";
    				vdda-supply = <0xcd>;
    
    				port {
    
    					endpoint {
    						remote-endpoint = <0xce>;
    						phandle = <0xe5>;
    					};
    				};
    			};
    		};
    
    		epwmss@4843e000 {
    			compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
    			reg = <0x4843e000 0x30>;
    			ti,hwmods = "epwmss0";
    			#address-cells = <0x1>;
    			#size-cells = <0x1>;
    			status = "disabled";
    			ranges;
    
    			pwm@4843e200 {
    				compatible = "ti,dra746-ehrpwm", "ti,am3352-ehrpwm";
    				#pwm-cells = <0x3>;
    				reg = <0x4843e200 0x80>;
    				clocks = <0xcf 0xb>;
    				clock-names = "tbclk", "fck";
    				status = "disabled";
    			};
    
    			ecap@4843e100 {
    				compatible = "ti,dra746-ecap", "ti,am3352-ecap";
    				#pwm-cells = <0x3>;
    				reg = <0x4843e100 0x80>;
    				clocks = <0xb>;
    				clock-names = "fck";
    				status = "disabled";
    			};
    		};
    
    		epwmss@48440000 {
    			compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
    			reg = <0x48440000 0x30>;
    			ti,hwmods = "epwmss1";
    			#address-cells = <0x1>;
    			#size-cells = <0x1>;
    			status = "disabled";
    			ranges;
    
    			pwm@48440200 {
    				compatible = "ti,dra746-ehrpwm", "ti,am3352-ehrpwm";
    				#pwm-cells = <0x3>;
    				reg = <0x48440200 0x80>;
    				clocks = <0xd0 0xb>;
    				clock-names = "tbclk", "fck";
    				status = "disabled";
    			};
    
    			ecap@48440100 {
    				compatible = "ti,dra746-ecap", "ti,am3352-ecap";
    				#pwm-cells = <0x3>;
    				reg = <0x48440100 0x80>;
    				clocks = <0xb>;
    				clock-names = "fck";
    				status = "disabled";
    			};
    		};
    
    		epwmss@48442000 {
    			compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
    			reg = <0x48442000 0x30>;
    			ti,hwmods = "epwmss2";
    			#address-cells = <0x1>;
    			#size-cells = <0x1>;
    			status = "disabled";
    			ranges;
    
    			pwm@48442200 {
    				compatible = "ti,dra746-ehrpwm", "ti,am3352-ehrpwm";
    				#pwm-cells = <0x3>;
    				reg = <0x48442200 0x80>;
    				clocks = <0xd1 0xb>;
    				clock-names = "tbclk", "fck";
    				status = "disabled";
    			};
    
    			ecap@48442100 {
    				compatible = "ti,dra746-ecap", "ti,am3352-ecap";
    				#pwm-cells = <0x3>;
    				reg = <0x48442100 0x80>;
    				clocks = <0xb>;
    				clock-names = "fck";
    				status = "disabled";
    			};
    		};
    
    		aes@4b500000 {
    			compatible = "ti,omap4-aes";
    			ti,hwmods = "aes1";
    			reg = <0x4b500000 0xa0>;
    			interrupts = <0x0 0x50 0x4>;
    			dmas = <0xc3 0x6f 0x0 0xc3 0x6e 0x0>;
    			dma-names = "tx", "rx";
    			clocks = <0xa>;
    			clock-names = "fck";
    		};
    
    		aes@4b700000 {
    			compatible = "ti,omap4-aes";
    			ti,hwmods = "aes2";
    			reg = <0x4b700000 0xa0>;
    			interrupts = <0x0 0x3b 0x4>;
    			dmas = <0xc3 0x72 0x0 0xc3 0x71 0x0>;
    			dma-names = "tx", "rx";
    			clocks = <0xa>;
    			clock-names = "fck";
    		};
    
    		des@480a5000 {
    			compatible = "ti,omap4-des";
    			ti,hwmods = "des";
    			reg = <0x480a5000 0xa0>;
    			interrupts = <0x0 0x4d 0x4>;
    			dmas = <0x8d 0x75 0x8d 0x74>;
    			dma-names = "tx", "rx";
    			clocks = <0xa>;
    			clock-names = "fck";
    		};
    
    		sham@53100000 {
    			compatible = "ti,omap5-sham";
    			ti,hwmods = "sham";
    			reg = <0x4b101000 0x300>;
    			interrupts = <0x0 0x2e 0x4>;
    			dmas = <0xc3 0x77 0x0>;
    			dma-names = "rx";
    			clocks = <0xa>;
    			clock-names = "fck";
    		};
    
    		rng@48090000 {
    			compatible = "ti,omap4-rng";
    			ti,hwmods = "rng";
    			reg = <0x48090000 0x2000>;
    			interrupts = <0x0 0x2f 0x4>;
    			clocks = <0xa>;
    			clock-names = "fck";
    		};
    
    		opp-supply@4a003b20 {
    			compatible = "ti,omap5-opp-supply";
    			reg = <0x4a003b20 0xc>;
    			ti,efuse-settings = <0x102ca0 0x0 0x11b340 0x4 0x127690 0x8>;
    			ti,absolute-max-voltage-uv = <0x16e360>;
    		};
    
    		vpe {
    			compatible = "ti,vpe";
    			ti,hwmods = "vpe";
    			clocks = <0x56>;
    			clock-names = "fck";
    			reg = <0x489d0000 0x120 0x489d0700 0x80 0x489d5700 0x18 0x489dd000 0x400>;
    			reg-names = "vpe_top", "sc", "csc", "vpdma";
    			interrupts = <0x0 0x162 0x4>;
    			#address-cells = <0x1>;
    			#size-cells = <0x0>;
    		};
    
    		vip@0x48970000 {
    			compatible = "ti,vip1";
    			reg = <0x48970000 0x114 0x48975500 0xd8 0x48975700 0x18 0x48975800 0x80 0x48975a00 0xd8 0x48975c00 0x18 0x48975d00 0x80 0x4897d000 0x400>;
    			reg-names = "vip", "parser0", "csc0", "sc0", "parser1", "csc1", "sc1", "vpdma";
    			ti,hwmods = "vip1";
    			interrupts = <0x0 0x15f 0x4 0x0 0x188 0x4>;
    			syscon-pol = <0x9 0x534>;
    			#address-cells = <0x1>;
    			#size-cells = <0x0>;
    			status = "disabled";
    
    			ports {
    				#address-cells = <0x1>;
    				#size-cells = <0x0>;
    
    				port@0 {
    					reg = <0x0>;
    				};
    
    				port@1 {
    					reg = <0x1>;
    				};
    
    				port@2 {
    					reg = <0x2>;
    				};
    
    				port@3 {
    					reg = <0x3>;
    				};
    			};
    		};
    
    		dsp_system@41500000 {
    			compatible = "syscon";
    			reg = <0x41500000 0x100>;
    			phandle = <0xd2>;
    		};
    
    		omap_dwc3_4@48940000 {
    			compatible = "ti,dwc3";
    			ti,hwmods = "usb_otg_ss4";
    			reg = <0x48940000 0x10000>;
    			interrupts = <0x0 0x15a 0x4>;
    			#address-cells = <0x1>;
    			#size-cells = <0x1>;
    			utmi-mode = <0x2>;
    			ranges;
    			status = "disabled";
    
    			usb@48950000 {
    				compatible = "snps,dwc3";
    				reg = <0x48950000 0x17000>;
    				interrupts = <0x0 0x159 0x4 0x0 0x159 0x4 0x0 0x15a 0x4>;
    				interrupt-names = "peripheral", "host", "otg";
    				maximum-speed = "high-speed";
    				dr_mode = "otg";
    			};
    		};
    
    		mmu@41501000 {
    			compatible = "ti,dra7-dsp-iommu";
    			reg = <0x41501000 0x100>;
    			interrupts = <0x0 0x92 0x4>;
    			ti,hwmods = "mmu0_dsp2";
    			#iommu-cells = <0x0>;
    			ti,syscon-mmuconfig = <0xd2 0x0>;
    			phandle = <0xd3>;
    		};
    
    		mmu@41502000 {
    			compatible = "ti,dra7-dsp-iommu";
    			reg = <0x41502000 0x100>;
    			interrupts = <0x0 0x93 0x4>;
    			ti,hwmods = "mmu1_dsp2";
    			#iommu-cells = <0x0>;
    			ti,syscon-mmuconfig = <0xd2 0x1>;
    			phandle = <0xd4>;
    		};
    
    		dsp@41000000 {
    			compatible = "ti,dra7-dsp";
    			reg = <0x41000000 0x48000 0x41600000 0x8000 0x41700000 0x8000>;
    			reg-names = "l2ram", "l1pram", "l1dram";
    			ti,hwmods = "dsp2";
    			syscon-bootreg = <0x9 0x560>;
    			iommus = <0xd3 0xd4>;
    			ti,rproc-standby-info = <0x4a005620>;
    			status = "okay";
    			mboxes = <0x9b 0xd5>;
    			timers = <0xd6>;
    			watchdog-timers = <0xd7>;
    			memory-region = <0xd8>;
    		};
    
    		vip@0x48990000 {
    			compatible = "ti,vip2";
    			reg = <0x48990000 0x114 0x48995500 0xd8 0x48995700 0x18 0x48995800 0x80 0x48995a00 0xd8 0x48995c00 0x18 0x48995d00 0x80 0x4899d000 0x400>;
    			reg-names = "vip", "parser0", "csc0", "sc0", "parser1", "csc1", "sc1", "vpdma";
    			ti,hwmods = "vip2";
    			interrupts = <0x0 0x160 0x4 0x0 0x189 0x4>;
    			syscon-pol = <0x9 0x534>;
    			#address-cells = <0x1>;
    			#size-cells = <0x0>;
    			status = "disabled";
    
    			ports {
    				#address-cells = <0x1>;
    				#size-cells = <0x0>;
    
    				port@0 {
    					reg = <0x0>;
    				};
    
    				port@1 {
    					reg = <0x1>;
    				};
    
    				port@2 {
    					reg = <0x2>;
    				};
    
    				port@3 {
    					reg = <0x3>;
    				};
    			};
    		};
    
    		vip@0x489b0000 {
    			compatible = "ti,vip3";
    			reg = <0x489b0000 0x114 0x489b5500 0xd8 0x489b5700 0x18 0x489b5800 0x80 0x489b5a00 0xd8 0x489b5c00 0x18 0x489b5d00 0x80 0x489bd000 0x400>;
    			reg-names = "vip", "parser0", "csc0", "sc0", "parser1", "csc1", "sc1", "vpdma";
    			ti,hwmods = "vip3";
    			interrupts = <0x0 0x161 0x4 0x0 0x18a 0x4>;
    			syscon-pol = <0x9 0x534>;
    			#address-cells = <0x1>;
    			#size-cells = <0x0>;
    			status = "disabled";
    
    			ports {
    				#address-cells = <0x1>;
    				#size-cells = <0x0>;
    
    				port@0 {
    					reg = <0x0>;
    				};
    
    				port@1 {
    					reg = <0x1>;
    				};
    			};
    		};
    	};
    
    	thermal-zones {
    
    		cpu_thermal {
    			polling-delay-passive = <0xfa>;
    			polling-delay = <0x1f4>;
    			thermal-sensors = <0xd9 0x0>;
    			coefficients = <0x0 0x7d0>;
    
    			trips {
    
    				cpu_alert {
    					temperature = <0x13880>;
    					hysteresis = <0x7d0>;
    					type = "passive";
    					phandle = <0xda>;
    				};
    
    				cpu_crit {
    					temperature = <0x15f90>;
    					hysteresis = <0x7d0>;
    					type = "critical";
    				};
    
    				cpu_alert1 {
    					temperature = <0xc350>;
    					hysteresis = <0x7d0>;
    					type = "active";
    					phandle = <0xdc>;
    				};
    			};
    
    			cooling-maps {
    
    				map0 {
    					trip = <0xda>;
    					cooling-device = <0xdb 0xffffffff 0xffffffff>;
    				};
    
    				map1 {
    					trip = <0xdc>;
    					cooling-device = <0xdd 0xffffffff 0xffffffff>;
    				};
    			};
    		};
    
    		gpu_thermal {
    			polling-delay-passive = <0xfa>;
    			polling-delay = <0x1f4>;
    			thermal-sensors = <0xd9 0x1>;
    			coefficients = <0x0 0x7d0>;
    
    			trips {
    
    				gpu_crit {
    					temperature = <0x15f90>;
    					hysteresis = <0x7d0>;
    					type = "critical";
    				};
    			};
    		};
    
    		core_thermal {
    			polling-delay-passive = <0xfa>;
    			polling-delay = <0x1f4>;
    			thermal-sensors = <0xd9 0x2>;
    			coefficients = <0x0 0x7d0>;
    
    			trips {
    
    				core_crit {
    					temperature = <0x15f90>;
    					hysteresis = <0x7d0>;
    					type = "critical";
    				};
    			};
    		};
    
    		dspeve_thermal {
    			polling-delay-passive = <0xfa>;
    			polling-delay = <0x1f4>;
    			thermal-sensors = <0xd9 0x3>;
    			coefficients = <0x0 0x7d0>;
    
    			trips {
    
    				dspeve_crit {
    					temperature = <0x15f90>;
    					hysteresis = <0x7d0>;
    					type = "critical";
    				};
    			};
    		};
    
    		iva_thermal {
    			polling-delay-passive = <0xfa>;
    			polling-delay = <0x1f4>;
    			thermal-sensors = <0xd9 0x4>;
    			coefficients = <0x0 0x7d0>;
    
    			trips {
    
    				iva_crit {
    					temperature = <0x15f90>;
    					hysteresis = <0x7d0>;
    					type = "critical";
    				};
    			};
    		};
    
    		board_thermal {
    			polling-delay-passive = <0x4e2>;
    			polling-delay = <0x5dc>;
    			thermal-sensors = <0xde 0x0>;
    
    			trips {
    
    				board_alert {
    					temperature = <0x9c40>;
    					hysteresis = <0x7d0>;
    					type = "active";
    					phandle = <0xdf>;
    				};
    
    				board_crit {
    					temperature = <0x19a28>;
    					hysteresis = <0x0>;
    					type = "critical";
    				};
    			};
    
    			cooling-maps {
    
    				map0 {
    					trip = <0xdf>;
    					cooling-device = <0xdd 0xffffffff 0xffffffff>;
    				};
    			};
    		};
    	};
    
    	pmu {
    		compatible = "arm,cortex-a15-pmu";
    		interrupt-parent = <0x8>;
    		interrupts = <0x0 0x83 0x4 0x0 0x84 0x4>;
    	};
    
    	memory@0 {
    		device_type = "memory";
    		reg = <0x0 0x80000000 0x0 0x80000000>;
    	};
    
    	reserved-memory {
    		#address-cells = <0x2>;
    		#size-cells = <0x2>;
    		ranges;
    
    		ipu2-memory@95800000 {
    			compatible = "shared-dma-pool";
    			reg = <0x0 0x95800000 0x0 0x3800000>;
    			reusable;
    			status = "okay";
    			phandle = <0xa0>;
    		};
    
    		dsp1-memory@99000000 {
    			compatible = "shared-dma-pool";
    			reg = <0x0 0x99000000 0x0 0x4000000>;
    			reusable;
    			status = "okay";
    			phandle = <0xa6>;
    		};
    
    		ipu1-memory@9d000000 {
    			compatible = "shared-dma-pool";
    			reg = <0x0 0x9d000000 0x0 0x2000000>;
    			reusable;
    			status = "okay";
    			phandle = <0x99>;
    		};
    
    		dsp2-memory@9f000000 {
    			compatible = "shared-dma-pool";
    			reg = <0x0 0x9f000000 0x0 0x800000>;
    			reusable;
    			status = "okay";
    			phandle = <0xd8>;
    		};
    
    		cmem_block_mem@a0000000 {
    			reg = <0x0 0xa0000000 0x0 0xc000000>;
    			no-map;
    			status = "okay";
    			phandle = <0xeb>;
    		};
    
    		cmem_block_mem@40500000 {
    			reg = <0x0 0x40500000 0x0 0x100000>;
    			no-map;
    			status = "okay";
    			phandle = <0xec>;
    		};
    	};
    
    	fixedregulator-main_12v0 {
    		compatible = "regulator-fixed";
    		regulator-name = "main_12v0";
    		regulator-min-microvolt = <0xb71b00>;
    		regulator-max-microvolt = <0xb71b00>;
    		regulator-always-on;
    		regulator-boot-on;
    		phandle = <0xe0>;
    	};
    
    	fixedregulator-evm_5v0 {
    		compatible = "regulator-fixed";
    		regulator-name = "evm_5v0";
    		regulator-min-microvolt = <0x4c4b40>;
    		regulator-max-microvolt = <0x4c4b40>;
    		vin-supply = <0xe0>;
    		regulator-always-on;
    		regulator-boot-on;
    	};
    
    	fixedregulator-vdd_3v3 {
    		compatible = "regulator-fixed";
    		regulator-name = "vdd_3v3";
    		vin-supply = <0xe1>;
    		regulator-min-microvolt = <0x325aa0>;
    		regulator-max-microvolt = <0x325aa0>;
    		phandle = <0xab>;
    	};
    
    	fixedregulator-aic_dvdd {
    		compatible = "regulator-fixed";
    		regulator-name = "aic_dvdd_fixed";
    		vin-supply = <0xab>;
    		regulator-min-microvolt = <0x1b7740>;
    		regulator-max-microvolt = <0x1b7740>;
    		phandle = <0xac>;
    	};
    
    	fixedregulator-vtt {
    		compatible = "regulator-fixed";
    		regulator-name = "vtt_fixed";
    		vin-supply = <0xe2>;
    		regulator-min-microvolt = <0x325aa0>;
    		regulator-max-microvolt = <0x325aa0>;
    		regulator-always-on;
    		regulator-boot-on;
    		enable-active-high;
    		gpio = <0xaa 0xb 0x0>;
    	};
    
    	leds {
    		compatible = "gpio-leds";
    
    		led0 {
    			label = "beagle-x15:usr0";
    			gpios = <0xaa 0x9 0x0>;
    			linux,default-trigger = "heartbeat";
    			default-state = "off";
    		};
    
    		led1 {
    			label = "beagle-x15:usr1";
    			gpios = <0xaa 0x8 0x0>;
    			linux,default-trigger = "cpu0";
    			default-state = "off";
    		};
    
    		led2 {
    			label = "beagle-x15:usr2";
    			gpios = <0xaa 0xe 0x0>;
    			linux,default-trigger = "mmc0";
    			default-state = "off";
    		};
    
    		led3 {
    			label = "beagle-x15:usr3";
    			gpios = <0xaa 0xf 0x0>;
    			linux,default-trigger = "disk-activity";
    			default-state = "off";
    		};
    	};
    
    	gpio_fan {
    		compatible = "gpio-fan";
    		gpios = <0xe3 0x2 0x0>;
    		gpio-fan,speed-map = <0x0 0x0 0x32c8 0x1>;
    		#cooling-cells = <0x2>;
    		phandle = <0xdd>;
    	};
    
    	connector {
    		compatible = "hdmi-connector";
    		label = "hdmi";
    		type = [61 00];
    
    		port {
    
    			endpoint {
    				remote-endpoint = <0xe4>;
    				phandle = <0xe6>;
    			};
    		};
    	};
    
    	encoder {
    		compatible = "ti,tpd12s015";
    		status = "disabled";
    
    		ports {
    			#address-cells = <0x1>;
    			#size-cells = <0x0>;
    
    			port@0 {
    				reg = <0x0>;
    
    				endpoint {
    					remote-endpoint = <0xe5>;
    					phandle = <0xce>;
    				};
    			};
    
    			port@1 {
    				reg = <0x1>;
    
    				endpoint {
    					remote-endpoint = <0xe6>;
    					phandle = <0xe4>;
    				};
    			};
    		};
    	};
    
    	sound0 {
    		compatible = "simple-audio-card";
    		simple-audio-card,name = "BeagleBoard-X15";
    		simple-audio-card,widgets = "Line", "Line Out", "Line", "Line In";
    		simple-audio-card,routing = "Line Out", "LLOUT", "Line Out", "RLOUT", "MIC2L", "Line In", "MIC2R", "Line In";
    		simple-audio-card,format = "dsp_b";
    		simple-audio-card,bitclock-master = <0xe7>;
    		simple-audio-card,frame-master = <0xe7>;
    		simple-audio-card,bitclock-inversion;
    
    		simple-audio-card,cpu {
    			sound-dai = <0xe8>;
    		};
    
    		simple-audio-card,codec {
    			sound-dai = <0xe9>;
    			clocks = <0xea>;
    			phandle = <0xe7>;
    		};
    	};
    
    	cmem {
    		compatible = "ti,cmem";
    		#address-cells = <0x1>;
    		#size-cells = <0x0>;
    		#pool-size-cells = <0x2>;
    		status = "okay";
    
    		cmem_block@0 {
    			reg = <0x0>;
    			memory-region = <0xeb>;
    			cmem-buf-pools = <0x1 0x0 0xc000000>;
    		};
    
    		cmem_block@1 {
    			reg = <0x1>;
    			memory-region = <0xec>;
    		};
    	};
    };

    It looks like it is not enough to "disable" a non-exist GPU, because the AM5726 doesn`t has a GPU. I have to delete this node?

     

     

     

     

     

     

  • The U-Boot and the kernel has their respective device trees. It is not okay to use the U-Boot's device tree in kernel or vice versa.

  • >> The U-Boot and the kernel has their respective device trees. It is not okay to use the U-Boot's device tree in kernel or vice versa.

    Ok no problem, I use now the DTB/DTS from the kernel.

     

    Error Kernel-message

    [    0.535907] NET: Registered protocol family 16
    [    0.543176] DMA: preallocated 256 KiB pool for atomic coherent allocations
    [    0.551258] omap_hwmod: l3_main_2 using broken dt data from ocp
    [    0.767351] Unhandled fault: asynchronous external abort (0x1211) at 0x00000000
    [    0.767354] pgd = (ptrval)
    [    0.767357] [00000000] *pgd=80000080004003, *pmd=00000000
    [    0.767369] Internal error: : 1211 [#1] PREEMPT SMP ARM
    [    0.767372] Modules linked in:

    The output message there are now:

    U-Boot SPL 2019.01 (Oct 21 2019 - 13:31:27 +0200)
    DRA752-GP ES2.0
    Trying to boot from MMC1
    no pinctrl state for default mode
    no pinctrl state for default mode
    Loading Environment from FAT... *** Warning - bad CRC, using default environment
    
    Loading Environment from MMC... Card did not respond to voltage select!
    *** Warning - No block device, using default environment
    
    
    
    U-Boot 2019.01 (Oct 21 2019 - 13:31:27 +0200)
    
    CPU  : DRA752-GP ES2.0
    Model: TI AM5726 sec4
    Board: SEC4 
    DRAM:  1 GiB
    Size of DRAM is 1024 MB
    
    beagle_x
    MMC:   OMAP SD/MMC: 0
    Loading Environment from FAT... *** Warning - bad CRC, using default environment
    
    Loading Environment from MMC... MMC Device 1 not found
    *** Warning - No MMC card found, using default environment
    
     *** -> This Board is unknown
    
    late init
    
    late init 2a
    
    invalid mmc device
    late init 2b
    
    end of late init
    
    Net:   No ethernet found.
    Hit any key to stop autoboot:  0 
    => 
    => setenv bootargs console=ttyS2,115200 earlyprintk loglevel=3 mem=0x40000000 loglevel=7
    => load mmc 0:1 0x88000000 sec4.dtb
    90430 bytes read in 5 ms (17.2 MiB/s)
    => load mmc 0:1 0x82000000 zImage
    3723776 bytes read in 169 ms (21 MiB/s)
    => bootz 0x82000000 - 0x88000000
    ## Flattened Device Tree blob at 88000000
       Booting using the fdt blob at 0x88000000
       Loading Device Tree to 8ffe6000, end 8ffff13d ... OK
    
    Starting kernel ...
    
    [    0.000000] Booting Linux on physical CPU 0x0
    [    0.000000] Linux version 4.19.38-rt19 (rene@ubuntu) (gcc version 8.3.0 (GNU Toolchain for the A-profile Architecture 8.3-2019.03 (arm-rel-8.36))9
    [    0.000000] CPU: ARMv7 Processor [412fc0f2] revision 2 (ARMv7), cr=30c5387d
    [    0.000000] CPU: div instructions available: patching division code
    [    0.000000] CPU: PIPT / VIPT nonaliasing data cache, PIPT instruction cache
    [    0.000000] OF: fdt: Machine model: TI AM5728 BeagleBoard-X15
    [    0.000000] bootconsole [earlycon0] enabled
    [    0.000000] Memory policy: Data cache writealloc
    [    0.000000] efi: Getting EFI parameters from FDT:
    [    0.000000] efi: UEFI not found.
    [    0.000000] Reserved memory: created CMA memory pool at 0x0000000095800000, size 56 MiB
    [    0.000000] OF: reserved mem: initialized node ipu2-memory@95800000, compatible id shared-dma-pool
    [    0.000000] Reserved memory: created CMA memory pool at 0x0000000099000000, size 64 MiB
    [    0.000000] OF: reserved mem: initialized node dsp1-memory@99000000, compatible id shared-dma-pool
    [    0.000000] Reserved memory: created CMA memory pool at 0x000000009d000000, size 32 MiB
    [    0.000000] OF: reserved mem: initialized node ipu1-memory@9d000000, compatible id shared-dma-pool
    [    0.000000] Reserved memory: created CMA memory pool at 0x000000009f000000, size 8 MiB
    [    0.000000] OF: reserved mem: initialized node dsp2-memory@9f000000, compatible id shared-dma-pool
    [    0.000000] cma: Reserved 24 MiB at 0x00000000be400000
    [    0.000000] OMAP4: Map 0x00000000bfd00000 to (ptrval) for dram barrier
    [    0.000000] DRA752 ES2.0
    [    0.000000] random: get_random_bytes called from start_kernel+0xb0/0x480 with crng_init=0
    [    0.000000] percpu: Embedded 15 pages/cpu s32544 r8192 d20704 u61440
    [    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 210496
    [    0.000000] Kernel command line: console=ttyS2,115200 earlyprintk loglevel=3 mem=0x40000000 loglevel=7
    [    0.000000] Dentry cache hash table entries: 131072 (order: 8, 1048576 bytes)
    [    0.000000] Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
    [    0.000000] Memory: 635936K/848896K available (8192K kernel code, 315K rwdata, 2180K rodata, 2048K init, 264K bss, 24544K reserved, 188416K cma-r)
    [    0.000000] Virtual kernel memory layout:
    [    0.000000]     vector  : 0xffff0000 - 0xffff1000   (   4 kB)
    [    0.000000]     fixmap  : 0xffc00000 - 0xfff00000   (3072 kB)
    [    0.000000]     vmalloc : 0xf0800000 - 0xff800000   ( 240 MB)
    [    0.000000]     lowmem  : 0xc0000000 - 0xf0000000   ( 768 MB)
    [    0.000000]     pkmap   : 0xbfe00000 - 0xc0000000   (   2 MB)
    [    0.000000]     modules : 0xbf000000 - 0xbfe00000   (  14 MB)
    [    0.000000]       .text : 0x(ptrval) - 0x(ptrval)   (10208 kB)
    [    0.000000]       .init : 0x(ptrval) - 0x(ptrval)   (2048 kB)
    [    0.000000]       .data : 0x(ptrval) - 0x(ptrval)   ( 316 kB)
    [    0.000000]        .bss : 0x(ptrval) - 0x(ptrval)   ( 265 kB)
    [    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1
    [    0.000000] rcu: Preemptible hierarchical RCU implementation.
    [    0.000000] rcu:     RCU priority boosting: priority 1 delay 500 ms.
    [    0.000000]  No expedited grace period (rcu_normal_after_boot).
    [    0.000000]  Tasks RCU enabled.
    [    0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
    [    0.000000] GIC: Using split EOI/Deactivate mode
    [    0.000000] OMAP clockevent source: timer1 at 32786 Hz
    [    0.000000] arch_timer: cp15 timer(s) running at 6.14MHz (phys).
    [    0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x16af5adb9, max_idle_ns: 440795202250 ns
    [    0.000005] sched_clock: 56 bits at 6MHz, resolution 162ns, wraps every 4398046511023ns
    [    0.000011] Switching to timer-based delay loop, resolution 162ns
    [    0.000287] clocksource: 32k_counter: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 58327039986419 ns
    [    0.000291] OMAP clocksource: 32k_counter at 32768 Hz
    [    0.000732] Console: colour dummy device 80x30
    [    0.321576] Calibrating delay loop (skipped), value calculated using timer frequency.. 12.29 BogoMIPS (lpj=6147)
    [    0.321585] pid_max: default: 32768 minimum: 301
    [    0.321729] Mount-cache hash table entries: 2048 (order: 1, 8192 bytes)
    [    0.321738] Mountpoint-cache hash table entries: 2048 (order: 1, 8192 bytes)
    [    0.322467] CPU: Testing write buffer coherency: ok
    [    0.322497] CPU0: Spectre v2: using ICIALLU workaround
    [    0.322741] /cpus/cpu@0 missing clock-frequency property
    [    0.367632] /cpus/cpu@1 missing clock-frequency property
    [    0.373086] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
    [    0.384930] Setting up static identity map for 0x80200000 - 0x80200060
    [    0.394988] rcu: Hierarchical SRCU implementation.
    [    0.406534] EFI services will not be available.
    [    0.413219] smp: Bringing up secondary CPUs ...
    [    0.431681] CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
    [    0.431685] CPU1: Spectre v2: using ICIALLU workaround
    [    0.431814] smp: Brought up 1 node, 2 CPUs
    [    0.447311] SMP: Total of 2 processors activated (24.58 BogoMIPS).
    [    0.453686] CPU: All CPU(s) started in HYP mode.
    [    0.458442] CPU: Virtualization extensions available.
    [    0.464292] devtmpfs: initialized
    [    0.497321] VFP support v0.3: implementor 41 architecture 4 part 30 variant f rev 0
    [    0.505550] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 1911260446275000 ns
    [    0.515631] futex hash table entries: 512 (order: 3, 32768 bytes)
    [    0.525232] pinctrl core: initialized pinctrl subsystem
    [    0.531422] DMI not present or invalid.
    [    0.535907] NET: Registered protocol family 16
    [    0.543176] DMA: preallocated 256 KiB pool for atomic coherent allocations
    [    0.551258] omap_hwmod: l3_main_2 using broken dt data from ocp
    [    0.767351] Unhandled fault: asynchronous external abort (0x1211) at 0x00000000
    [    0.767354] pgd = (ptrval)
    [    0.767357] [00000000] *pgd=80000080004003, *pmd=00000000
    [    0.767369] Internal error: : 1211 [#1] PREEMPT SMP ARM
    [    0.767372] Modules linked in:
    [    0.767381] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.19.38-rt19 #4
    [    0.767384] Hardware name: Generic DRA74X (Flattened Device Tree)
    [    0.767395] PC is at _enable_sysc+0x6c/0x228
    [    0.767400] LR is at _enable_sysc+0x50/0x228
    [    0.767405] pc : [<c021f790>]    lr : [<c021f774>]    psr: 40000013
    [    0.767408] sp : ef0a1e40  ip : ef0a1e40  fp : ef0a1e64
    [    0.767411] r10: c0e563a8  r9 : c0e47824  r8 : 00000000
    [    0.767414] r7 : c10126dc  r6 : c1007488  r5 : 00000000  r4 : c10121c4
    [    0.767417] r3 : c1012248  r2 : b3a39597  r1 : c1012248  r0 : c10121c4
    [    0.767422] Flags: nZcv  IRQs on  FIQs on  Mode SVC_32  ISA ARM  Segment user
    [    0.767426] Control: 30c5387d  Table: 80003000  DAC: fffffffd
    [    0.767430] Process swapper/0 (pid: 1, stack limit = 0x(ptrval))
    [    0.767434] Stack: (0xef0a1e40 to 0xef0a2000)
    [    0.767440] 1e40: ef0a1e64 b3a39597 c10121c4 00000000 c104f4d0 c10126dc ef0a1e8c ef0a1e68
    [    0.767446] 1e60: c021fb38 c021f730 c100fd70 c1007488 c10121e8 c1007488 c10121c4 c10121fc
    [    0.767451] 1e80: ef0a1ebc ef0a1e90 c021d660 c021f958 ef0a1ebc ef0a1ea0 00000008 b3a39597
    [    0.767456] 1ea0: c10121c4 c100c528 ffffe000 c0e0d020 ef0a1ed4 ef0a1ec0 c0e0d134 c021d51c
    [    0.767461] 1ec0: c104ee80 c1007488 ef0a1f4c ef0a1ed8 c02023fc c0e0d02c 00000000 c0b6e964
    [    0.767466] 1ee0: c0b6e944 c0b6e900 c0b79f50 c1007488 00000000 c0b6e91c 00000002 00000002
    [    0.767471] 1f00: 00000000 c0b64160 c0e004f0 c0c1fb9c c10186a0 ef66457b ef664584 b3a39597
    [    0.767476] 1f20: c0280168 b3a39597 c104ee80 00000003 c104ee80 c104ee80 c0e004f0 c0e47844
    [    0.767481] 1f40: ef0a1f94 ef0a1f50 c0e01048 c0202384 00000002 00000002 00000000 c0e004f0
    [    0.767486] 1f60: c0c1fb9c 000000b4 c08d80bc 00000000 c08d2ee8 00000000 00000000 00000000
    [    0.767491] 1f80: 00000000 00000000 ef0a1fac ef0a1f98 c08d2ef8 c0e00e40 00000000 c08d2ee8
    [    0.767496] 1fa0: 00000000 ef0a1fb0 c02010e0 c08d2ef4 00000000 00000000 00000000 00000000
    [    0.767500] 1fc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
    [    0.767505] 1fe0: 00000000 00000000 00000000 00000000 00000013 00000000 00000000 00000000
    [    0.767507] Backtrace: 
    [    0.767518] [<c021f724>] (_enable_sysc) from [<c021fb38>] (_enable+0x1ec/0x25c)
    [    0.767524]  r7:c10126dc r6:c104f4d0 r5:00000000 r4:c10121c4
    [    0.767533] [<c021f94c>] (_enable) from [<c021d660>] (_setup.constprop.25+0x150/0x4e8)
    [    0.767538]  r7:c10121fc r6:c10121c4 r5:c1007488 r4:c10121e8
    [    0.767550] [<c021d510>] (_setup.constprop.25) from [<c0e0d134>] (__omap_hwmod_setup_all+0x114/0x12c)
    [    0.767555]  r7:c0e0d020 r6:ffffe000 r5:c100c528 r4:c10121c4
    [    0.767565] [<c0e0d020>] (__omap_hwmod_setup_all) from [<c02023fc>] (do_one_initcall+0x84/0x1b0)
    [    0.767568]  r5:c1007488 r4:c104ee80
    [    0.767576] [<c0202378>] (do_one_initcall) from [<c0e01048>] (kernel_init_freeable+0x214/0x2a8)
    [    0.767581]  r8:c0e47844 r7:c0e004f0 r6:c104ee80 r5:c104ee80 r4:00000003
    [    0.767589] [<c0e00e34>] (kernel_init_freeable) from [<c08d2ef8>] (kernel_init+0x10/0x118)
    [    0.767595]  r10:00000000 r9:00000000 r8:00000000 r7:00000000 r6:00000000 r5:c08d2ee8
    [    0.767597]  r4:00000000
    [    0.767604] [<c08d2ee8>] (kernel_init) from [<c02010e0>] (ret_from_fork+0x14/0x34)
    [    0.767607] Exception stack(0xef0a1fb0 to 0xef0a1ff8)
    [    0.767611] 1fa0:                                     00000000 00000000 00000000 00000000
    [    0.767616] 1fc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
    [    0.767620] 1fe0: 00000000 00000000 00000000 00000000 00000013 00000000
    [    0.767624]  r5:c08d2ee8 r4:00000000
    [    0.767631] Code: e1a00004 ebfffeb3 e5943004 e1a00004 (e5942044) 
    [    1.123695] ---[ end trace 0000000000000001 ]---
    [    1.123765] Kernel panic - not syncing: Attempted to kill init! exitcode=0x0000000b
    [    1.123765] 
    [    1.123775] CPU1: stopping
    [    1.123782] CPU: 1 PID: 0 Comm: swapper/1 Tainted: G      D           4.19.38-rt19 #4
    [    1.123785] Hardware name: Generic DRA74X (Flattened Device Tree)
    [    1.123787] Backtrace: 
    [    1.123799] [<c020c778>] (dump_backtrace) from [<c020cab0>] (show_stack+0x18/0x1c)
    [    1.123806]  r7:fa212000 r6:60000193 r5:00000000 r4:c104ce64
    [    1.123821] [<c020ca98>] (show_stack) from [<c08be8e4>] (dump_stack+0x90/0xa4)
    [    1.123831] [<c08be854>] (dump_stack) from [<c020f1f8>] (handle_IPI+0x1bc/0x22c)
    [    1.123837]  r7:fa212000 r6:00000001 r5:00000000 r4:c104f100
    [    1.123848] [<c020f03c>] (handle_IPI) from [<c0551f58>] (gic_handle_irq+0x94/0x98)
    [    1.123852]  r6:fa21200c r5:c1026dbc r4:c100796c
    [    1.123859] [<c0551ec4>] (gic_handle_irq) from [<c02019f8>] (__irq_svc+0x58/0xa0)
    [    1.123862] Exception stack(0xef0cff28 to 0xef0cff70)
    [    1.123868] ff20:                   00000000 00000b74 00000000 c021a180 ffffe000 c10074bc
    [    1.123873] ff40: c1007504 00000002 00000001 c104ea96 c0b6f188 ef0cff84 ef0cff88 ef0cff78
    [    1.123877] ff60: c0208c20 c0208c24 60000013 ffffffff
    [    1.123882]  r9:ef0ce000 r8:00000001 r7:ef0cff5c r6:ffffffff r5:60000013 r4:c0208c24
    [    1.123893] [<c0208be4>] (arch_cpu_idle) from [<c08d7ad0>] (default_idle_call+0x34/0x40)
    [    1.123903] [<c08d7a9c>] (default_idle_call) from [<c025bb04>] (do_idle+0x110/0x180)
    [    1.123909] [<c025b9f4>] (do_idle) from [<c025be60>] (cpu_startup_entry+0x20/0x28)
    [    1.123915]  r10:00000000 r9:412fc0f2 r8:80007000 r7:c104f108 r6:00000001 r5:ef0ce000
    [    1.123918]  r4:00000086 r3:ef0ce000
    [    1.123926] [<c025be40>] (cpu_startup_entry) from [<c020ed94>] (secondary_start_kernel+0x178/0x180)
    [    1.123932] [<c020ec1c>] (secondary_start_kernel) from [<8020210c>] (0x8020210c)
    [    1.123936]  r7:c104f108 r6:30c0387d r5:00000000 r4:af0771c0
    

     

     

    The converted DTS from DTB:

    /dts-v1/;
    
    / {
    	#address-cells = <0x2>;
    	#size-cells = <0x2>;
    	compatible = "ti,am572x-beagle-x15", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7";
    	interrupt-parent = <0x1>;
    	model = "TI AM5728 BeagleBoard-X15";
    
    	chosen {
    		stdout-path = "/ocp/serial@48020000";
    	};
    
    	aliases {
    		i2c0 = "/ocp/i2c@48070000";
    		i2c1 = "/ocp/i2c@48072000";
    		i2c2 = "/ocp/i2c@48060000";
    		i2c3 = "/ocp/i2c@4807a000";
    		i2c4 = "/ocp/i2c@4807c000";
    		serial0 = "/ocp/serial@4806a000";
    		serial1 = "/ocp/serial@4806c000";
    		serial2 = "/ocp/serial@48020000";
    		serial3 = "/ocp/serial@4806e000";
    		serial4 = "/ocp/serial@48066000";
    		serial5 = "/ocp/serial@48068000";
    		serial6 = "/ocp/serial@48420000";
    		serial7 = "/ocp/serial@48422000";
    		serial8 = "/ocp/serial@48424000";
    		serial9 = "/ocp/serial@4ae2b000";
    		ethernet0 = "/ocp/ethernet@48484000/slave@48480200";
    		ethernet1 = "/ocp/ethernet@48484000/slave@48480300";
    		d_can0 = "/ocp/can@4ae3c000";
    		d_can1 = "/ocp/can@48480000";
    		spi0 = "/ocp/qspi@4b300000";
    		rproc0 = "/ocp/ipu@58820000";
    		rproc1 = "/ocp/ipu@55020000";
    		rproc2 = "/ocp/dsp@40800000";
    		rproc3 = "/ocp/dsp@41000000";
    		rtc0 = "/ocp/i2c@48060000/rtc@6f";
    		rtc1 = "/ocp/i2c@48070000/tps659038@58/tps659038_rtc";
    		rtc2 = "/ocp/rtc@48838000";
    		display0 = "/connector";
    		sound0 = "/sound0";
    		sound1 = "/ocp/dss@58000000/encoder@58060000";
    	};
    
    	timer {
    		compatible = "arm,armv7-timer";
    		interrupts = <0x1 0xd 0x308 0x1 0xe 0x308 0x1 0xb 0x308 0x1 0xa 0x308>;
    		interrupt-parent = <0x2>;
    	};
    
    	interrupt-controller@48211000 {
    		compatible = "arm,cortex-a15-gic";
    		interrupt-controller;
    		#interrupt-cells = <0x3>;
    		reg = <0x0 0x48211000 0x0 0x1000 0x0 0x48212000 0x0 0x2000 0x0 0x48214000 0x0 0x2000 0x0 0x48216000 0x0 0x2000>;
    		interrupts = <0x1 0x9 0x304>;
    		interrupt-parent = <0x2>;
    		phandle = <0x2>;
    	};
    
    	interrupt-controller@48281000 {
    		compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
    		interrupt-controller;
    		#interrupt-cells = <0x3>;
    		reg = <0x0 0x48281000 0x0 0x1000>;
    		interrupt-parent = <0x2>;
    		phandle = <0x8>;
    	};
    
    	cpus {
    		#address-cells = <0x1>;
    		#size-cells = <0x0>;
    
    		cpu@0 {
    			device_type = "cpu";
    			compatible = "arm,cortex-a15";
    			reg = <0x0>;
    			operating-points-v2 = <0x3>;
    			clocks = <0x4>;
    			clock-names = "cpu";
    			clock-latency = <0x493e0>;
    			#cooling-cells = <0x2>;
    			vbb-supply = <0x5>;
    			vdd-supply = <0x6>;
    			voltage-tolerance = <0x1>;
    			phandle = <0xdb>;
    		};
    
    		cpu@1 {
    			device_type = "cpu";
    			compatible = "arm,cortex-a15";
    			reg = <0x1>;
    			operating-points-v2 = <0x3>;
    			clocks = <0x4>;
    			clock-names = "cpu";
    			clock-latency = <0x493e0>;
    			#cooling-cells = <0x2>;
    			vbb-supply = <0x5>;
    		};
    	};
    
    	opp-table {
    		compatible = "operating-points-v2-ti-cpu";
    		syscon = <0x7>;
    		opp-shared;
    		phandle = <0x3>;
    
    		opp_nom-1000000000 {
    			opp-hz = <0x0 0x3b9aca00>;
    			opp-microvolt = <0x102ca0 0xcf850 0x118c30 0x102ca0 0xcf850 0x118c30>;
    			opp-supported-hw = <0xff 0x1>;
    			opp-suspend;
    		};
    
    		opp_od-1176000000 {
    			opp-hz = <0x0 0x46185600>;
    			opp-microvolt = <0x11b340 0xd8108 0x11b340 0x11b340 0xd8108 0x11b340>;
    			opp-supported-hw = <0xff 0x2>;
    		};
    
    		opp_high@1500000000 {
    			opp-hz = <0x0 0x59682f00>;
    			opp-microvolt = <0x127690 0xe7ef0 0x1312d0 0x127690 0xe7ef0 0x1312d0>;
    			opp-supported-hw = <0xff 0x4>;
    		};
    	};
    
    	soc {
    		compatible = "ti,omap-infra";
    
    		mpu {
    			compatible = "ti,omap5-mpu";
    			ti,hwmods = "mpu";
    		};
    	};
    
    	ocp {
    		compatible = "ti,omap5-l3-noc", "simple-bus";
    		#address-cells = <0x1>;
    		#size-cells = <0x1>;
    		ranges = <0x0 0x0 0x0 0xc0000000>;
    		ti,hwmods = "l3_main_1", "l3_main_3";
    		reg = <0x0 0x44000000 0x0 0x1000000 0x0 0x45000000 0x0 0x1000>;
    		interrupts-extended = <0x1 0x0 0x4 0x4 0x8 0x0 0xa 0x4>;
    
    		l4@4a000000 {
    			compatible = "ti,dra7-l4-cfg", "simple-bus";
    			#address-cells = <0x1>;
    			#size-cells = <0x1>;
    			ranges = <0x0 0x4a000000 0x22c000>;
    
    			scm@2000 {
    				compatible = "ti,dra7-scm-core", "simple-bus";
    				reg = <0x2000 0x2000>;
    				#address-cells = <0x1>;
    				#size-cells = <0x1>;
    				ranges = <0x0 0x2000 0x2000>;
    
    				scm_conf@0 {
    					compatible = "syscon", "simple-bus";
    					reg = <0x0 0x1400>;
    					#address-cells = <0x1>;
    					#size-cells = <0x1>;
    					ranges = <0x0 0x0 0x1400>;
    					phandle = <0x9>;
    
    					pbias_regulator@e00 {
    						compatible = "ti,pbias-dra7", "ti,pbias-omap";
    						reg = <0xe00 0x4>;
    						syscon = <0x9>;
    
    						pbias_mmc_omap5 {
    							regulator-name = "pbias_mmc_omap5";
    							regulator-min-microvolt = <0x1b7740>;
    							regulator-max-microvolt = <0x325aa0>;
    							phandle = <0xad>;
    						};
    					};
    
    					clocks {
    						#address-cells = <0x1>;
    						#size-cells = <0x0>;
    
    						dss_deshdcp_clk@558 {
    							#clock-cells = <0x0>;
    							compatible = "ti,gate-clock";
    							clocks = <0xa>;
    							ti,bit-shift = <0x0>;
    							reg = <0x558>;
    						};
    
    						ehrpwm0_tbclk@558 {
    							#clock-cells = <0x0>;
    							compatible = "ti,gate-clock";
    							clocks = <0xb>;
    							ti,bit-shift = <0x14>;
    							reg = <0x558>;
    							phandle = <0xcf>;
    						};
    
    						ehrpwm1_tbclk@558 {
    							#clock-cells = <0x0>;
    							compatible = "ti,gate-clock";
    							clocks = <0xb>;
    							ti,bit-shift = <0x15>;
    							reg = <0x558>;
    							phandle = <0xd0>;
    						};
    
    						ehrpwm2_tbclk@558 {
    							#clock-cells = <0x0>;
    							compatible = "ti,gate-clock";
    							clocks = <0xb>;
    							ti,bit-shift = <0x16>;
    							reg = <0x558>;
    							phandle = <0xd1>;
    						};
    
    						sys_32k_ck {
    							#clock-cells = <0x0>;
    							compatible = "ti,mux-clock";
    							clocks = <0xc 0xd 0xd 0xd>;
    							ti,bit-shift = <0x8>;
    							reg = <0x6c4>;
    							phandle = <0x50>;
    						};
    					};
    				};
    
    				pinmux@1400 {
    					compatible = "ti,dra7-padconf", "pinctrl-single";
    					reg = <0x1400 0x468>;
    					#address-cells = <0x1>;
    					#size-cells = <0x0>;
    					#pinctrl-cells = <0x1>;
    					#interrupt-cells = <0x1>;
    					interrupt-controller;
    					pinctrl-single,register-width = <0x20>;
    					pinctrl-single,function-mask = <0x3fffffff>;
    					phandle = <0x8e>;
    
    					mmc1_pins_default {
    						pinctrl-single,pins = <0x354 0x60000 0x358 0x60000 0x35c 0x60000 0x360 0x60000 0x364 0x60000 0x368 0x60000>;
    						phandle = <0xae>;
    					};
    
    					mmc1_pins_sdr12 {
    						pinctrl-single,pins = <0x354 0x60000 0x358 0x60000 0x35c 0x60000 0x360 0x60000 0x364 0x60000 0x368 0x60000>;
    					};
    
    					mmc1_pins_hs {
    						pinctrl-single,pins = <0x354 0x601b0 0x358 0x601b0 0x35c 0x601b0 0x360 0x601b0 0x364 0x601b0 0x368 0x601b0>;
    						phandle = <0xb0>;
    					};
    
    					mmc1_pins_sdr25 {
    						pinctrl-single,pins = <0x354 0x601b0 0x358 0x601b0 0x35c 0x601b0 0x360 0x601b0 0x364 0x601b0 0x368 0x601b0>;
    					};
    
    					mmc1_pins_sdr50 {
    						pinctrl-single,pins = <0x354 0x601a0 0x358 0x601a0 0x35c 0x601a0 0x360 0x601a0 0x364 0x601a0 0x368 0x601a0>;
    					};
    
    					mmc1_pins_ddr50 {
    						pinctrl-single,pins = <0x354 0x60100 0x358 0x60100 0x35c 0x60100 0x360 0x60100 0x364 0x60100 0x368 0x60100>;
    					};
    
    					mmc1_pins_sdr104 {
    						pinctrl-single,pins = <0x354 0x60100 0x358 0x60100 0x35c 0x60100 0x360 0x60100 0x364 0x60100 0x368 0x60100>;
    					};
    
    					mmc2_pins_default {
    						pinctrl-single,pins = <0x9c 0x60001 0xb0 0x60001 0xa0 0x60001 0xa4 0x60001 0xa8 0x60001 0xac 0x60001 0x8c 0x60001 0x90 0x60001 0x94 0x60001 0x98 0x60001>;
    						phandle = <0xb2>;
    					};
    
    					mmc2_pins_hs {
    						pinctrl-single,pins = <0x9c 0x60001 0xb0 0x60001 0xa0 0x60001 0xa4 0x60001 0xa8 0x60001 0xac 0x60001 0x8c 0x60001 0x90 0x60001 0x94 0x60001 0x98 0x60001>;
    					};
    
    					mmc2_pins_ddr_3_3v_rev11 {
    						pinctrl-single,pins = <0x9c 0x60101 0xb0 0x60101 0xa0 0x60101 0xa4 0x60101 0xa8 0x60101 0xac 0x60101 0x8c 0x60101 0x90 0x60101 0x94 0x60101 0x98 0x60101>;
    					};
    
    					mmc2_pins_ddr_1_8v_rev11 {
    						pinctrl-single,pins = <0x9c 0x60101 0xb0 0x60101 0xa0 0x60101 0xa4 0x60101 0xa8 0x60101 0xac 0x60101 0x8c 0x60101 0x90 0x60101 0x94 0x60101 0x98 0x60101>;
    					};
    
    					mmc2_pins_ddr_rev20 {
    						pinctrl-single,pins = <0x9c 0x60001 0xb0 0x60001 0xa0 0x60001 0xa4 0x60001 0xa8 0x60001 0xac 0x60001 0x8c 0x60001 0x90 0x60001 0x94 0x60001 0x98 0x60001>;
    					};
    
    					mmc2_pins_hs200 {
    						pinctrl-single,pins = <0x9c 0x60101 0xb0 0x60101 0xa0 0x60101 0xa4 0x60101 0xa8 0x60101 0xac 0x60101 0x8c 0x60101 0x90 0x60101 0x94 0x60101 0x98 0x60101>;
    					};
    
    					mmc4_pins_default {
    						pinctrl-single,pins = <0x3e8 0x60103 0x3ec 0x60103 0x3f0 0x60103 0x3f4 0x60103 0x3f8 0x60103 0x3fc 0x60103>;
    					};
    
    					mmc4_pins_hs {
    						pinctrl-single,pins = <0x3e8 0x60103 0x3ec 0x60103 0x3f0 0x60103 0x3f4 0x60103 0x3f8 0x60103 0x3fc 0x60103>;
    					};
    
    					mmc3_pins_default {
    						pinctrl-single,pins = <0x37c 0x60000 0x380 0x60000 0x384 0x60000 0x388 0x60000 0x38c 0x60000 0x390 0x60000>;
    					};
    
    					mmc3_pins_hs {
    						pinctrl-single,pins = <0x37c 0x60000 0x380 0x60000 0x384 0x60000 0x388 0x60000 0x38c 0x60000 0x390 0x60000>;
    					};
    
    					mmc3_pins_sdr12 {
    						pinctrl-single,pins = <0x37c 0x60000 0x380 0x60000 0x384 0x60000 0x388 0x60000 0x38c 0x60000 0x390 0x60000>;
    					};
    
    					mmc3_pins_sdr25 {
    						pinctrl-single,pins = <0x37c 0x60000 0x380 0x60000 0x384 0x60000 0x388 0x60000 0x38c 0x60000 0x390 0x60000>;
    					};
    
    					mmc3_pins_sdr50 {
    						pinctrl-single,pins = <0x37c 0x60100 0x380 0x60100 0x384 0x60100 0x388 0x60100 0x38c 0x60100 0x390 0x60100>;
    					};
    
    					mmc4_pins_sdr12 {
    						pinctrl-single,pins = <0x3e8 0x60103 0x3ec 0x60103 0x3f0 0x60103 0x3f4 0x60103 0x3f8 0x60103 0x3fc 0x60103>;
    					};
    
    					mmc4_pins_sdr25 {
    						pinctrl-single,pins = <0x3e8 0x60103 0x3ec 0x60103 0x3f0 0x60103 0x3f4 0x60103 0x3f8 0x60103 0x3fc 0x60103>;
    					};
    				};
    
    				scm_conf@1c04 {
    					compatible = "syscon";
    					reg = <0x1c04 0x20>;
    					#syscon-cells = <0x2>;
    					phandle = <0x88>;
    				};
    
    				scm_conf@1c24 {
    					compatible = "syscon";
    					reg = <0x1c24 0x24>;
    					phandle = <0x85>;
    				};
    
    				dma-router@b78 {
    					compatible = "ti,dra7-dma-crossbar";
    					reg = <0xb78 0xfc>;
    					#dma-cells = <0x1>;
    					dma-requests = <0xcd>;
    					ti,dma-safe-map = <0x0>;
    					dma-masters = <0xe>;
    					phandle = <0x8d>;
    				};
    
    				dma-router@c78 {
    					compatible = "ti,dra7-dma-crossbar";
    					reg = <0xc78 0x7c>;
    					#dma-cells = <0x2>;
    					dma-requests = <0xcc>;
    					ti,dma-safe-map = <0x0>;
    					dma-masters = <0xf>;
    					phandle = <0xc3>;
    				};
    			};
    
    			cm_core_aon@5000 {
    				compatible = "ti,dra7-cm-core-aon", "simple-bus";
    				#address-cells = <0x1>;
    				#size-cells = <0x1>;
    				reg = <0x5000 0x2000>;
    				ranges = <0x0 0x5000 0x2000>;
    
    				clocks {
    					#address-cells = <0x1>;
    					#size-cells = <0x0>;
    
    					atl_clkin0_ck {
    						#clock-cells = <0x0>;
    						compatible = "ti,dra7-atl-clock";
    						clocks = <0x10 0x0 0x1a>;
    						phandle = <0xc4>;
    					};
    
    					atl_clkin1_ck {
    						#clock-cells = <0x0>;
    						compatible = "ti,dra7-atl-clock";
    						clocks = <0x10 0x0 0x1a>;
    						phandle = <0xc5>;
    					};
    
    					atl_clkin2_ck {
    						#clock-cells = <0x0>;
    						compatible = "ti,dra7-atl-clock";
    						clocks = <0x10 0x0 0x1a>;
    						phandle = <0xc6>;
    					};
    
    					atl_clkin3_ck {
    						#clock-cells = <0x0>;
    						compatible = "ti,dra7-atl-clock";
    						clocks = <0x10 0x0 0x1a>;
    						phandle = <0xc7>;
    					};
    
    					hdmi_clkin_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x0>;
    						phandle = <0x30>;
    					};
    
    					mlb_clkin_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x0>;
    						phandle = <0x81>;
    					};
    
    					mlbp_clkin_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x0>;
    						phandle = <0x82>;
    					};
    
    					pciesref_acs_clk_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x5f5e100>;
    						phandle = <0x40>;
    					};
    
    					ref_clkin0_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x0>;
    					};
    
    					ref_clkin1_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x0>;
    					};
    
    					ref_clkin2_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x0>;
    					};
    
    					ref_clkin3_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x0>;
    					};
    
    					rmii_clk_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x0>;
    					};
    
    					sdvenc_clkin_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x0>;
    					};
    
    					secure_32k_clk_src_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x8000>;
    						phandle = <0x6b>;
    					};
    
    					sys_clk32_crystal_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x8000>;
    						phandle = <0xc>;
    					};
    
    					sys_clk32_pseudo_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x11>;
    						clock-mult = <0x1>;
    						clock-div = <0x262>;
    						phandle = <0xd>;
    					};
    
    					virt_12000000_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0xb71b00>;
    						phandle = <0x59>;
    					};
    
    					virt_13000000_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0xc65d40>;
    					};
    
    					virt_16800000_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x1005900>;
    						phandle = <0x5b>;
    					};
    
    					virt_19200000_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x124f800>;
    						phandle = <0x5c>;
    					};
    
    					virt_20000000_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x1312d00>;
    						phandle = <0x5a>;
    					};
    
    					virt_26000000_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x18cba80>;
    						phandle = <0x5d>;
    					};
    
    					virt_27000000_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x19bfcc0>;
    						phandle = <0x5e>;
    					};
    
    					virt_38400000_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x249f000>;
    						phandle = <0x5f>;
    					};
    
    					sys_clkin2 {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x1588800>;
    						phandle = <0x60>;
    					};
    
    					usb_otg_clkin_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x0>;
    						phandle = <0x68>;
    					};
    
    					video1_clkin_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x0>;
    						phandle = <0x3a>;
    					};
    
    					video1_m2_clkin_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x0>;
    						phandle = <0x2f>;
    					};
    
    					video2_clkin_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x0>;
    						phandle = <0x3b>;
    					};
    
    					video2_m2_clkin_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x0>;
    						phandle = <0x2e>;
    					};
    
    					dpll_abe_ck@1e0 {
    						#clock-cells = <0x0>;
    						compatible = "ti,omap4-dpll-m4xen-clock";
    						clocks = <0x12 0x13>;
    						reg = <0x1e0 0x1e4 0x1ec 0x1e8>;
    						assigned-clocks = <0x14>;
    						assigned-clock-rates = <0x2faf080>;
    						phandle = <0x14>;
    					};
    
    					dpll_abe_x2_ck {
    						#clock-cells = <0x0>;
    						compatible = "ti,omap4-dpll-x2-clock";
    						clocks = <0x14>;
    						phandle = <0x15>;
    					};
    
    					dpll_abe_m2x2_ck@1f0 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x15>;
    						ti,max-div = <0x1f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x1f0>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0x16>;
    					};
    
    					abe_clk@108 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x16>;
    						ti,max-div = <0x4>;
    						reg = <0x108>;
    						ti,index-power-of-two;
    						phandle = <0x62>;
    					};
    
    					dpll_abe_m2_ck@1f0 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x14>;
    						ti,max-div = <0x1f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x1f0>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0x64>;
    					};
    
    					dpll_abe_m3x2_ck@1f4 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x15>;
    						ti,max-div = <0x1f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x1f4>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0x17>;
    					};
    
    					dpll_core_byp_mux@12c {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x11 0x17>;
    						ti,bit-shift = <0x17>;
    						reg = <0x12c>;
    						phandle = <0x18>;
    					};
    
    					dpll_core_ck@120 {
    						#clock-cells = <0x0>;
    						compatible = "ti,omap4-dpll-core-clock";
    						clocks = <0x11 0x18>;
    						reg = <0x120 0x124 0x12c 0x128>;
    						phandle = <0x19>;
    					};
    
    					dpll_core_x2_ck {
    						#clock-cells = <0x0>;
    						compatible = "ti,omap4-dpll-x2-clock";
    						clocks = <0x19>;
    						phandle = <0x1a>;
    					};
    
    					dpll_core_h12x2_ck@13c {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x1a>;
    						ti,max-div = <0x3f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x13c>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0x1b>;
    					};
    
    					mpu_dpll_hs_clk_div {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x1b>;
    						clock-mult = <0x1>;
    						clock-div = <0x1>;
    						phandle = <0x1c>;
    					};
    
    					dpll_mpu_ck@160 {
    						#clock-cells = <0x0>;
    						compatible = "ti,omap5-mpu-dpll-clock";
    						clocks = <0x11 0x1c>;
    						reg = <0x160 0x164 0x16c 0x168>;
    						phandle = <0x4>;
    					};
    
    					dpll_mpu_m2_ck@170 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x4>;
    						ti,max-div = <0x1f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x170>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0x1d>;
    					};
    
    					mpu_dclk_div {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x1d>;
    						clock-mult = <0x1>;
    						clock-div = <0x1>;
    						phandle = <0x6f>;
    					};
    
    					dsp_dpll_hs_clk_div {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x1b>;
    						clock-mult = <0x1>;
    						clock-div = <0x1>;
    						phandle = <0x1e>;
    					};
    
    					dpll_dsp_byp_mux@240 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x11 0x1e>;
    						ti,bit-shift = <0x17>;
    						reg = <0x240>;
    						phandle = <0x1f>;
    					};
    
    					dpll_dsp_ck@234 {
    						#clock-cells = <0x0>;
    						compatible = "ti,omap4-dpll-clock";
    						clocks = <0x11 0x1f>;
    						reg = <0x234 0x238 0x240 0x23c>;
    						assigned-clocks = <0x20>;
    						assigned-clock-rates = <0x23c34600>;
    						phandle = <0x20>;
    					};
    
    					dpll_dsp_m2_ck@244 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x20>;
    						ti,max-div = <0x1f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x244>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						assigned-clocks = <0x21>;
    						assigned-clock-rates = <0x23c34600>;
    						phandle = <0x21>;
    					};
    
    					iva_dpll_hs_clk_div {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x1b>;
    						clock-mult = <0x1>;
    						clock-div = <0x1>;
    						phandle = <0x22>;
    					};
    
    					dpll_iva_byp_mux@1ac {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x11 0x22>;
    						ti,bit-shift = <0x17>;
    						reg = <0x1ac>;
    						phandle = <0x23>;
    					};
    
    					dpll_iva_ck@1a0 {
    						#clock-cells = <0x0>;
    						compatible = "ti,omap4-dpll-clock";
    						clocks = <0x11 0x23>;
    						reg = <0x1a0 0x1a4 0x1ac 0x1a8>;
    						assigned-clocks = <0x24>;
    						assigned-clock-rates = <0x45707d40>;
    						phandle = <0x24>;
    					};
    
    					dpll_iva_m2_ck@1b0 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x24>;
    						ti,max-div = <0x1f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x1b0>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						assigned-clocks = <0x25>;
    						assigned-clock-rates = <0x17257f16>;
    						phandle = <0x25>;
    					};
    
    					iva_dclk {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x25>;
    						clock-mult = <0x1>;
    						clock-div = <0x1>;
    						phandle = <0x71>;
    					};
    
    					dpll_gpu_byp_mux@2e4 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x11 0x17>;
    						ti,bit-shift = <0x17>;
    						reg = <0x2e4>;
    						phandle = <0x26>;
    					};
    
    					dpll_gpu_ck@2d8 {
    						#clock-cells = <0x0>;
    						compatible = "ti,omap4-dpll-clock";
    						clocks = <0x11 0x26>;
    						reg = <0x2d8 0x2dc 0x2e4 0x2e0>;
    						assigned-clocks = <0x27>;
    						assigned-clock-rates = <0x4c1d7940>;
    						phandle = <0x27>;
    					};
    
    					dpll_gpu_m2_ck@2e8 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x27>;
    						ti,max-div = <0x1f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x2e8>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						assigned-clocks = <0x28>;
    						assigned-clock-rates = <0x195f286b>;
    						phandle = <0x28>;
    					};
    
    					dpll_core_m2_ck@130 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x19>;
    						ti,max-div = <0x1f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x130>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0x29>;
    					};
    
    					core_dpll_out_dclk_div {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x29>;
    						clock-mult = <0x1>;
    						clock-div = <0x1>;
    						phandle = <0x73>;
    					};
    
    					dpll_ddr_byp_mux@21c {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x11 0x17>;
    						ti,bit-shift = <0x17>;
    						reg = <0x21c>;
    						phandle = <0x2a>;
    					};
    
    					dpll_ddr_ck@210 {
    						#clock-cells = <0x0>;
    						compatible = "ti,omap4-dpll-clock";
    						clocks = <0x11 0x2a>;
    						reg = <0x210 0x214 0x21c 0x218>;
    						phandle = <0x2b>;
    					};
    
    					dpll_ddr_m2_ck@220 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x2b>;
    						ti,max-div = <0x1f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x220>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0x65>;
    					};
    
    					dpll_gmac_byp_mux@2b4 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x11 0x17>;
    						ti,bit-shift = <0x17>;
    						reg = <0x2b4>;
    						phandle = <0x2c>;
    					};
    
    					dpll_gmac_ck@2a8 {
    						#clock-cells = <0x0>;
    						compatible = "ti,omap4-dpll-clock";
    						clocks = <0x11 0x2c>;
    						reg = <0x2a8 0x2ac 0x2b4 0x2b0>;
    						phandle = <0x2d>;
    					};
    
    					dpll_gmac_m2_ck@2b8 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x2d>;
    						ti,max-div = <0x1f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x2b8>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0x66>;
    					};
    
    					video2_dclk_div {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x2e>;
    						clock-mult = <0x1>;
    						clock-div = <0x1>;
    						phandle = <0x75>;
    					};
    
    					video1_dclk_div {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x2f>;
    						clock-mult = <0x1>;
    						clock-div = <0x1>;
    						phandle = <0x76>;
    					};
    
    					hdmi_dclk_div {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x30>;
    						clock-mult = <0x1>;
    						clock-div = <0x1>;
    						phandle = <0x77>;
    					};
    
    					per_dpll_hs_clk_div {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x17>;
    						clock-mult = <0x1>;
    						clock-div = <0x2>;
    						phandle = <0x43>;
    					};
    
    					usb_dpll_hs_clk_div {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x17>;
    						clock-mult = <0x1>;
    						clock-div = <0x3>;
    						phandle = <0x47>;
    					};
    
    					eve_dpll_hs_clk_div {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x1b>;
    						clock-mult = <0x1>;
    						clock-div = <0x1>;
    						phandle = <0x31>;
    					};
    
    					dpll_eve_byp_mux@290 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x11 0x31>;
    						ti,bit-shift = <0x17>;
    						reg = <0x290>;
    						phandle = <0x32>;
    					};
    
    					dpll_eve_ck@284 {
    						#clock-cells = <0x0>;
    						compatible = "ti,omap4-dpll-clock";
    						clocks = <0x11 0x32>;
    						reg = <0x284 0x288 0x290 0x28c>;
    						phandle = <0x33>;
    					};
    
    					dpll_eve_m2_ck@294 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x33>;
    						ti,max-div = <0x1f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x294>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0x34>;
    					};
    
    					eve_dclk_div {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x34>;
    						clock-mult = <0x1>;
    						clock-div = <0x1>;
    						phandle = <0x80>;
    					};
    
    					dpll_core_h13x2_ck@140 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x1a>;
    						ti,max-div = <0x3f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x140>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    					};
    
    					dpll_core_h14x2_ck@144 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x1a>;
    						ti,max-div = <0x3f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x144>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0x51>;
    					};
    
    					dpll_core_h22x2_ck@154 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x1a>;
    						ti,max-div = <0x3f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x154>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0x3d>;
    					};
    
    					dpll_core_h23x2_ck@158 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x1a>;
    						ti,max-div = <0x3f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x158>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0x56>;
    					};
    
    					dpll_core_h24x2_ck@15c {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x1a>;
    						ti,max-div = <0x3f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x15c>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    					};
    
    					dpll_ddr_x2_ck {
    						#clock-cells = <0x0>;
    						compatible = "ti,omap4-dpll-x2-clock";
    						clocks = <0x2b>;
    						phandle = <0x35>;
    					};
    
    					dpll_ddr_h11x2_ck@228 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x35>;
    						ti,max-div = <0x3f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x228>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    					};
    
    					dpll_dsp_x2_ck {
    						#clock-cells = <0x0>;
    						compatible = "ti,omap4-dpll-x2-clock";
    						clocks = <0x20>;
    						phandle = <0x36>;
    					};
    
    					dpll_dsp_m3x2_ck@248 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x36>;
    						ti,max-div = <0x1f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x248>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						assigned-clocks = <0x37>;
    						assigned-clock-rates = <0x17d78400>;
    						phandle = <0x37>;
    					};
    
    					dpll_gmac_x2_ck {
    						#clock-cells = <0x0>;
    						compatible = "ti,omap4-dpll-x2-clock";
    						clocks = <0x2d>;
    						phandle = <0x38>;
    					};
    
    					dpll_gmac_h11x2_ck@2c0 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x38>;
    						ti,max-div = <0x3f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x2c0>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0x39>;
    					};
    
    					dpll_gmac_h12x2_ck@2c4 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x38>;
    						ti,max-div = <0x3f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x2c4>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    					};
    
    					dpll_gmac_h13x2_ck@2c8 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x38>;
    						ti,max-div = <0x3f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x2c8>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0xb5>;
    					};
    
    					dpll_gmac_m3x2_ck@2bc {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x38>;
    						ti,max-div = <0x1f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x2bc>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    					};
    
    					gmii_m_clk_div {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x39>;
    						clock-mult = <0x1>;
    						clock-div = <0x2>;
    					};
    
    					hdmi_clk2_div {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x30>;
    						clock-mult = <0x1>;
    						clock-div = <0x1>;
    					};
    
    					hdmi_div_clk {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x30>;
    						clock-mult = <0x1>;
    						clock-div = <0x1>;
    					};
    
    					l3_iclk_div@100 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						ti,max-div = <0x2>;
    						ti,bit-shift = <0x4>;
    						reg = <0x100>;
    						clocks = <0x1b>;
    						ti,index-power-of-two;
    						phandle = <0xa>;
    					};
    
    					l4_root_clk_div {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0xa>;
    						clock-mult = <0x1>;
    						clock-div = <0x2>;
    						phandle = <0xb>;
    					};
    
    					video1_clk2_div {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x3a>;
    						clock-mult = <0x1>;
    						clock-div = <0x1>;
    					};
    
    					video1_div_clk {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x3a>;
    						clock-mult = <0x1>;
    						clock-div = <0x1>;
    					};
    
    					video2_clk2_div {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x3b>;
    						clock-mult = <0x1>;
    						clock-div = <0x1>;
    					};
    
    					video2_div_clk {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x3b>;
    						clock-mult = <0x1>;
    						clock-div = <0x1>;
    					};
    
    					dummy_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x0>;
    					};
    				};
    
    				clockdomains {
    				};
    
    				mpu_cm@300 {
    					compatible = "ti,omap4-cm";
    					reg = <0x300 0x100>;
    					#address-cells = <0x1>;
    					#size-cells = <0x1>;
    					ranges = <0x0 0x300 0x100>;
    
    					clk@20 {
    						compatible = "ti,clkctrl";
    						reg = <0x20 0x4>;
    						#clock-cells = <0x2>;
    					};
    				};
    
    				dsp1_cm@400 {
    					compatible = "ti,omap4-cm";
    					reg = <0x400 0x100>;
    					#address-cells = <0x1>;
    					#size-cells = <0x1>;
    					ranges = <0x0 0x400 0x100>;
    
    					clk@20 {
    						compatible = "ti,clkctrl";
    						reg = <0x20 0x4>;
    						#clock-cells = <0x2>;
    					};
    				};
    
    				ipu1_cm@500 {
    					compatible = "ti,omap4-cm";
    					reg = <0x500 0x40>;
    					#address-cells = <0x1>;
    					#size-cells = <0x1>;
    					ranges = <0x0 0x500 0x100>;
    
    					clk@20 {
    						compatible = "ti,clkctrl";
    						reg = <0x20 0x20>;
    						#clock-cells = <0x2>;
    						assigned-clocks = <0x3c 0x0 0x18>;
    						assigned-clock-parents = <0x3d>;
    						phandle = <0x3c>;
    					};
    				};
    
    				ipu_cm@540 {
    					compatible = "ti,omap4-cm";
    					reg = <0x540 0xc0>;
    					#address-cells = <0x1>;
    					#size-cells = <0x1>;
    					ranges = <0x0 0x540 0xc0>;
    
    					clk@0 {
    						compatible = "ti,clkctrl";
    						reg = <0x0 0x44>;
    						#clock-cells = <0x2>;
    						phandle = <0x90>;
    					};
    				};
    
    				dsp2_cm@600 {
    					compatible = "ti,omap4-cm";
    					reg = <0x600 0x100>;
    					#address-cells = <0x1>;
    					#size-cells = <0x1>;
    					ranges = <0x0 0x600 0x100>;
    
    					clk@20 {
    						compatible = "ti,clkctrl";
    						reg = <0x20 0x4>;
    						#clock-cells = <0x2>;
    					};
    				};
    
    				rtc_cm@700 {
    					compatible = "ti,omap4-cm";
    					reg = <0x700 0x100>;
    					#address-cells = <0x1>;
    					#size-cells = <0x1>;
    					ranges = <0x0 0x700 0x100>;
    
    					clk@40 {
    						compatible = "ti,clkctrl";
    						reg = <0x40 0x8>;
    						#clock-cells = <0x2>;
    					};
    				};
    			};
    
    			cm_core@8000 {
    				compatible = "ti,dra7-cm-core", "simple-bus";
    				#address-cells = <0x1>;
    				#size-cells = <0x1>;
    				reg = <0x8000 0x3000>;
    				ranges = <0x0 0x8000 0x3000>;
    
    				clocks {
    					#address-cells = <0x1>;
    					#size-cells = <0x0>;
    
    					dpll_pcie_ref_ck@200 {
    						#clock-cells = <0x0>;
    						compatible = "ti,omap4-dpll-clock";
    						clocks = <0x11 0x11>;
    						reg = <0x200 0x204 0x20c 0x208>;
    						phandle = <0x3e>;
    					};
    
    					dpll_pcie_ref_m2ldo_ck@210 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x3e>;
    						ti,max-div = <0x1f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x210>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0x3f>;
    					};
    
    					apll_pcie_in_clk_mux@4ae06118 {
    						compatible = "ti,mux-clock";
    						clocks = <0x3f 0x40>;
    						#clock-cells = <0x0>;
    						reg = <0x21c 0x4>;
    						ti,bit-shift = <0x7>;
    						phandle = <0x41>;
    					};
    
    					apll_pcie_ck@21c {
    						#clock-cells = <0x0>;
    						compatible = "ti,dra7-apll-clock";
    						clocks = <0x41 0x3e>;
    						reg = <0x21c 0x220>;
    						phandle = <0x42>;
    					};
    
    					optfclk_pciephy_div@4a00821c {
    						compatible = "ti,divider-clock";
    						clocks = <0x42>;
    						#clock-cells = <0x0>;
    						reg = <0x21c>;
    						ti,dividers = <0x2 0x1>;
    						ti,bit-shift = <0x8>;
    						ti,max-div = <0x2>;
    						phandle = <0xb8>;
    					};
    
    					apll_pcie_clkvcoldo {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x42>;
    						clock-mult = <0x1>;
    						clock-div = <0x1>;
    					};
    
    					apll_pcie_clkvcoldo_div {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x42>;
    						clock-mult = <0x1>;
    						clock-div = <0x1>;
    					};
    
    					apll_pcie_m2_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x42>;
    						clock-mult = <0x1>;
    						clock-div = <0x1>;
    						phandle = <0x6a>;
    					};
    
    					dpll_per_byp_mux@14c {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x11 0x43>;
    						ti,bit-shift = <0x17>;
    						reg = <0x14c>;
    						phandle = <0x44>;
    					};
    
    					dpll_per_ck@140 {
    						#clock-cells = <0x0>;
    						compatible = "ti,omap4-dpll-clock";
    						clocks = <0x11 0x44>;
    						reg = <0x140 0x144 0x14c 0x148>;
    						phandle = <0x45>;
    					};
    
    					dpll_per_m2_ck@150 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x45>;
    						ti,max-div = <0x1f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x150>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0x46>;
    					};
    
    					func_96m_aon_dclk_div {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x46>;
    						clock-mult = <0x1>;
    						clock-div = <0x1>;
    						phandle = <0x78>;
    					};
    
    					dpll_usb_byp_mux@18c {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x11 0x47>;
    						ti,bit-shift = <0x17>;
    						reg = <0x18c>;
    						phandle = <0x48>;
    					};
    
    					dpll_usb_ck@180 {
    						#clock-cells = <0x0>;
    						compatible = "ti,omap4-dpll-j-type-clock";
    						clocks = <0x11 0x48>;
    						reg = <0x180 0x184 0x18c 0x188>;
    						phandle = <0x49>;
    					};
    
    					dpll_usb_m2_ck@190 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x49>;
    						ti,max-div = <0x7f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x190>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0x4d>;
    					};
    
    					dpll_pcie_ref_m2_ck@210 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x3e>;
    						ti,max-div = <0x7f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x210>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0x69>;
    					};
    
    					dpll_per_x2_ck {
    						#clock-cells = <0x0>;
    						compatible = "ti,omap4-dpll-x2-clock";
    						clocks = <0x45>;
    						phandle = <0x4a>;
    					};
    
    					dpll_per_h11x2_ck@158 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x4a>;
    						ti,max-div = <0x3f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x158>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0x4b>;
    					};
    
    					dpll_per_h12x2_ck@15c {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x4a>;
    						ti,max-div = <0x3f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x15c>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    					};
    
    					dpll_per_h13x2_ck@160 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x4a>;
    						ti,max-div = <0x3f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x160>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    					};
    
    					dpll_per_h14x2_ck@164 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x4a>;
    						ti,max-div = <0x3f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x164>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0x52>;
    					};
    
    					dpll_per_m2x2_ck@150 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x4a>;
    						ti,max-div = <0x1f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x150>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0x4c>;
    					};
    
    					dpll_usb_clkdcoldo {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x49>;
    						clock-mult = <0x1>;
    						clock-div = <0x1>;
    						phandle = <0x4f>;
    					};
    
    					func_128m_clk {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x4b>;
    						clock-mult = <0x1>;
    						clock-div = <0x2>;
    					};
    
    					func_12m_fclk {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x4c>;
    						clock-mult = <0x1>;
    						clock-div = <0x10>;
    					};
    
    					func_24m_clk {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x46>;
    						clock-mult = <0x1>;
    						clock-div = <0x4>;
    					};
    
    					func_48m_fclk {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x4c>;
    						clock-mult = <0x1>;
    						clock-div = <0x4>;
    					};
    
    					func_96m_fclk {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x4c>;
    						clock-mult = <0x1>;
    						clock-div = <0x2>;
    					};
    
    					l3init_60m_fclk@104 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x4d>;
    						reg = <0x104>;
    						ti,dividers = <0x1 0x8>;
    					};
    
    					clkout2_clk@6b0 {
    						#clock-cells = <0x0>;
    						compatible = "ti,gate-clock";
    						clocks = <0x4e>;
    						ti,bit-shift = <0x8>;
    						reg = <0x6b0>;
    						phandle = <0xea>;
    					};
    
    					l3init_960m_gfclk@6c0 {
    						#clock-cells = <0x0>;
    						compatible = "ti,gate-clock";
    						clocks = <0x4f>;
    						ti,bit-shift = <0x8>;
    						reg = <0x6c0>;
    					};
    
    					usb_phy1_always_on_clk32k@640 {
    						#clock-cells = <0x0>;
    						compatible = "ti,gate-clock";
    						clocks = <0x50>;
    						ti,bit-shift = <0x8>;
    						reg = <0x640>;
    						phandle = <0xba>;
    					};
    
    					usb_phy2_always_on_clk32k@688 {
    						#clock-cells = <0x0>;
    						compatible = "ti,gate-clock";
    						clocks = <0x50>;
    						ti,bit-shift = <0x8>;
    						reg = <0x688>;
    						phandle = <0xbc>;
    					};
    
    					usb_phy3_always_on_clk32k@698 {
    						#clock-cells = <0x0>;
    						compatible = "ti,gate-clock";
    						clocks = <0x50>;
    						ti,bit-shift = <0x8>;
    						reg = <0x698>;
    						phandle = <0xbd>;
    					};
    
    					gpu_core_gclk_mux@1220 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x51 0x52 0x28>;
    						ti,bit-shift = <0x18>;
    						reg = <0x1220>;
    						assigned-clocks = <0x53>;
    						assigned-clock-parents = <0x28>;
    						phandle = <0x53>;
    					};
    
    					gpu_hyd_gclk_mux@1220 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x51 0x52 0x28>;
    						ti,bit-shift = <0x1a>;
    						reg = <0x1220>;
    						assigned-clocks = <0x54>;
    						assigned-clock-parents = <0x28>;
    						phandle = <0x54>;
    					};
    
    					l3instr_ts_gclk_div@e50 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x55>;
    						ti,bit-shift = <0x18>;
    						reg = <0xe50>;
    						ti,dividers = <0x8 0x10 0x20>;
    					};
    
    					vip1_gclk_mux@1020 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0xa 0x56>;
    						ti,bit-shift = <0x18>;
    						reg = <0x1020>;
    					};
    
    					vip2_gclk_mux@1028 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0xa 0x56>;
    						ti,bit-shift = <0x18>;
    						reg = <0x1028>;
    					};
    
    					vip3_gclk_mux@1030 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0xa 0x56>;
    						ti,bit-shift = <0x18>;
    						reg = <0x1030>;
    					};
    				};
    
    				clockdomains {
    
    					coreaon_clkdm {
    						compatible = "ti,clockdomain";
    						clocks = <0x49>;
    					};
    				};
    
    				coreaon_cm@600 {
    					compatible = "ti,omap4-cm";
    					reg = <0x600 0x100>;
    					#address-cells = <0x1>;
    					#size-cells = <0x1>;
    					ranges = <0x0 0x600 0x100>;
    
    					clk@20 {
    						compatible = "ti,clkctrl";
    						reg = <0x20 0x1c>;
    						#clock-cells = <0x2>;
    						phandle = <0xbe>;
    					};
    				};
    
    				l3main1_cm@700 {
    					compatible = "ti,omap4-cm";
    					reg = <0x700 0x100>;
    					#address-cells = <0x1>;
    					#size-cells = <0x1>;
    					ranges = <0x0 0x700 0x100>;
    
    					clk@20 {
    						compatible = "ti,clkctrl";
    						reg = <0x20 0x74>;
    						#clock-cells = <0x2>;
    					};
    				};
    
    				ipu2_cm@900 {
    					compatible = "ti,omap4-cm";
    					reg = <0x900 0x100>;
    					#address-cells = <0x1>;
    					#size-cells = <0x1>;
    					ranges = <0x0 0x900 0x100>;
    
    					clk@20 {
    						compatible = "ti,clkctrl";
    						reg = <0x20 0x4>;
    						#clock-cells = <0x2>;
    					};
    				};
    
    				dma_cm@a00 {
    					compatible = "ti,omap4-cm";
    					reg = <0xa00 0x100>;
    					#address-cells = <0x1>;
    					#size-cells = <0x1>;
    					ranges = <0x0 0xa00 0x100>;
    
    					clk@20 {
    						compatible = "ti,clkctrl";
    						reg = <0x20 0x4>;
    						#clock-cells = <0x2>;
    					};
    				};
    
    				emif_cm@b00 {
    					compatible = "ti,omap4-cm";
    					reg = <0xb00 0x100>;
    					#address-cells = <0x1>;
    					#size-cells = <0x1>;
    					ranges = <0x0 0xb00 0x100>;
    
    					clk@20 {
    						compatible = "ti,clkctrl";
    						reg = <0x20 0x4>;
    						#clock-cells = <0x2>;
    					};
    				};
    
    				atl_cm@c00 {
    					compatible = "ti,omap4-cm";
    					reg = <0xc00 0x100>;
    					#address-cells = <0x1>;
    					#size-cells = <0x1>;
    					ranges = <0x0 0xc00 0x100>;
    
    					clk@0 {
    						compatible = "ti,clkctrl";
    						reg = <0x0 0x4>;
    						#clock-cells = <0x2>;
    						phandle = <0x10>;
    					};
    				};
    
    				l4cfg_cm@d00 {
    					compatible = "ti,omap4-cm";
    					reg = <0xd00 0x100>;
    					#address-cells = <0x1>;
    					#size-cells = <0x1>;
    					ranges = <0x0 0xd00 0x100>;
    
    					clk@20 {
    						compatible = "ti,clkctrl";
    						reg = <0x20 0x84>;
    						#clock-cells = <0x2>;
    					};
    				};
    
    				l3instr_cm@e00 {
    					compatible = "ti,omap4-cm";
    					reg = <0xe00 0x100>;
    					#address-cells = <0x1>;
    					#size-cells = <0x1>;
    					ranges = <0x0 0xe00 0x100>;
    
    					clk@20 {
    						compatible = "ti,clkctrl";
    						reg = <0x20 0xc>;
    						#clock-cells = <0x2>;
    					};
    				};
    
    				dss_cm@1100 {
    					compatible = "ti,omap4-cm";
    					reg = <0x1100 0x100>;
    					#address-cells = <0x1>;
    					#size-cells = <0x1>;
    					ranges = <0x0 0x1100 0x100>;
    
    					clk@20 {
    						compatible = "ti,clkctrl";
    						reg = <0x20 0x14>;
    						#clock-cells = <0x2>;
    						phandle = <0xcb>;
    					};
    				};
    
    				l3init_cm@1300 {
    					compatible = "ti,omap4-cm";
    					reg = <0x1300 0x100>;
    					#address-cells = <0x1>;
    					#size-cells = <0x1>;
    					ranges = <0x0 0x1300 0x100>;
    
    					clk@20 {
    						compatible = "ti,clkctrl";
    						reg = <0x20 0xd4>;
    						#clock-cells = <0x2>;
    						phandle = <0xb7>;
    					};
    				};
    
    				l4per_cm@1700 {
    					compatible = "ti,omap4-cm";
    					reg = <0x1700 0x300>;
    					#address-cells = <0x1>;
    					#size-cells = <0x1>;
    					ranges = <0x0 0x1700 0x300>;
    
    					clk@0 {
    						compatible = "ti,clkctrl";
    						reg = <0x0 0x20c>;
    						#clock-cells = <0x2>;
    						assigned-clocks = <0x57 0x168 0x18>;
    						assigned-clock-parents = <0x58>;
    						phandle = <0x57>;
    					};
    				};
    			};
    		};
    
    		l4@4ae00000 {
    			compatible = "ti,dra7-l4-wkup", "simple-bus";
    			#address-cells = <0x1>;
    			#size-cells = <0x1>;
    			ranges = <0x0 0x4ae00000 0x3f000>;
    
    			counter@4000 {
    				compatible = "ti,omap-counter32k";
    				reg = <0x4000 0x40>;
    				ti,hwmods = "counter_32k";
    			};
    
    			prm@6000 {
    				compatible = "ti,dra7-prm", "simple-bus";
    				reg = <0x6000 0x3000>;
    				interrupts = <0x0 0x6 0x4>;
    				#address-cells = <0x1>;
    				#size-cells = <0x1>;
    				ranges = <0x0 0x6000 0x3000>;
    
    				clocks {
    					#address-cells = <0x1>;
    					#size-cells = <0x0>;
    
    					sys_clkin1@110 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x59 0x5a 0x5b 0x5c 0x5d 0x5e 0x5f>;
    						reg = <0x110>;
    						ti,index-starts-at-one;
    						phandle = <0x11>;
    					};
    
    					abe_dpll_sys_clk_mux@118 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x11 0x60>;
    						reg = <0x118>;
    						phandle = <0x61>;
    					};
    
    					abe_dpll_bypass_clk_mux@114 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x61 0x50>;
    						reg = <0x114>;
    						phandle = <0x13>;
    					};
    
    					abe_dpll_clk_mux@10c {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x61 0x50>;
    						reg = <0x10c>;
    						phandle = <0x12>;
    					};
    
    					abe_24m_fclk@11c {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x16>;
    						reg = <0x11c>;
    						ti,dividers = <0x8 0x10>;
    						phandle = <0x58>;
    					};
    
    					aess_fclk@178 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x62>;
    						reg = <0x178>;
    						ti,max-div = <0x2>;
    						phandle = <0x63>;
    					};
    
    					abe_giclk_div@174 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x63>;
    						reg = <0x174>;
    						ti,max-div = <0x2>;
    						phandle = <0x91>;
    					};
    
    					abe_lp_clk_div@1d8 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x16>;
    						reg = <0x1d8>;
    						ti,dividers = <0x10 0x20>;
    						phandle = <0x83>;
    					};
    
    					abe_sys_clk_div@120 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x11>;
    						reg = <0x120>;
    						ti,max-div = <0x2>;
    					};
    
    					adc_gfclk_mux@1dc {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x11 0x60 0x50>;
    						reg = <0x1dc>;
    					};
    
    					sys_clk1_dclk_div@1c8 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x11>;
    						ti,max-div = <0x40>;
    						reg = <0x1c8>;
    						ti,index-power-of-two;
    						phandle = <0x6c>;
    					};
    
    					sys_clk2_dclk_div@1cc {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x60>;
    						ti,max-div = <0x40>;
    						reg = <0x1cc>;
    						ti,index-power-of-two;
    						phandle = <0x6d>;
    					};
    
    					per_abe_x1_dclk_div@1bc {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x64>;
    						ti,max-div = <0x40>;
    						reg = <0x1bc>;
    						ti,index-power-of-two;
    						phandle = <0x6e>;
    					};
    
    					dsp_gclk_div@18c {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x21>;
    						ti,max-div = <0x40>;
    						reg = <0x18c>;
    						ti,index-power-of-two;
    						phandle = <0x70>;
    					};
    
    					gpu_dclk@1a0 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x28>;
    						ti,max-div = <0x40>;
    						reg = <0x1a0>;
    						ti,index-power-of-two;
    						phandle = <0x72>;
    					};
    
    					emif_phy_dclk_div@190 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x65>;
    						ti,max-div = <0x40>;
    						reg = <0x190>;
    						ti,index-power-of-two;
    						phandle = <0x74>;
    					};
    
    					gmac_250m_dclk_div@19c {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x66>;
    						ti,max-div = <0x40>;
    						reg = <0x19c>;
    						ti,index-power-of-two;
    						phandle = <0x67>;
    					};
    
    					gmac_main_clk {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x67>;
    						clock-mult = <0x1>;
    						clock-div = <0x2>;
    						phandle = <0xc8>;
    					};
    
    					l3init_480m_dclk_div@1ac {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x4d>;
    						ti,max-div = <0x40>;
    						reg = <0x1ac>;
    						ti,index-power-of-two;
    						phandle = <0x79>;
    					};
    
    					usb_otg_dclk_div@184 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x68>;
    						ti,max-div = <0x40>;
    						reg = <0x184>;
    						ti,index-power-of-two;
    						phandle = <0x7a>;
    					};
    
    					sata_dclk_div@1c0 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x11>;
    						ti,max-div = <0x40>;
    						reg = <0x1c0>;
    						ti,index-power-of-two;
    						phandle = <0x7b>;
    					};
    
    					pcie2_dclk_div@1b8 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x69>;
    						ti,max-div = <0x40>;
    						reg = <0x1b8>;
    						ti,index-power-of-two;
    						phandle = <0x7c>;
    					};
    
    					pcie_dclk_div@1b4 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x6a>;
    						ti,max-div = <0x40>;
    						reg = <0x1b4>;
    						ti,index-power-of-two;
    						phandle = <0x7d>;
    					};
    
    					emu_dclk_div@194 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x11>;
    						ti,max-div = <0x40>;
    						reg = <0x194>;
    						ti,index-power-of-two;
    						phandle = <0x7e>;
    					};
    
    					secure_32k_dclk_div@1c4 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x6b>;
    						ti,max-div = <0x40>;
    						reg = <0x1c4>;
    						ti,index-power-of-two;
    						phandle = <0x7f>;
    					};
    
    					clkoutmux0_clk_mux@158 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x6c 0x6d 0x6e 0x6f 0x70 0x71 0x72 0x73 0x74 0x67 0x75 0x76 0x77 0x78 0x79 0x7a 0x7b 0x7c 0x7d 0x7e 0x7f 0x80>;
    						reg = <0x158>;
    					};
    
    					clkoutmux1_clk_mux@15c {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x6c 0x6d 0x6e 0x6f 0x70 0x71 0x72 0x73 0x74 0x67 0x75 0x76 0x77 0x78 0x79 0x7a 0x7b 0x7c 0x7d 0x7e 0x7f 0x80>;
    						reg = <0x15c>;
    					};
    
    					clkoutmux2_clk_mux@160 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x6c 0x6d 0x6e 0x6f 0x70 0x71 0x72 0x73 0x74 0x67 0x75 0x76 0x77 0x78 0x79 0x7a 0x7b 0x7c 0x7d 0x7e 0x7f 0x80>;
    						reg = <0x160>;
    						phandle = <0x4e>;
    					};
    
    					custefuse_sys_gfclk_div {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x11>;
    						clock-mult = <0x1>;
    						clock-div = <0x2>;
    					};
    
    					eve_clk@180 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x34 0x37>;
    						reg = <0x180>;
    					};
    
    					hdmi_dpll_clk_mux@164 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x11 0x60>;
    						reg = <0x164>;
    					};
    
    					mlb_clk@134 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x81>;
    						ti,max-div = <0x40>;
    						reg = <0x134>;
    						ti,index-power-of-two;
    					};
    
    					mlbp_clk@130 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x82>;
    						ti,max-div = <0x40>;
    						reg = <0x130>;
    						ti,index-power-of-two;
    					};
    
    					per_abe_x1_gfclk2_div@138 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x64>;
    						ti,max-div = <0x40>;
    						reg = <0x138>;
    						ti,index-power-of-two;
    					};
    
    					timer_sys_clk_div@144 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x11>;
    						reg = <0x144>;
    						ti,max-div = <0x2>;
    					};
    
    					video1_dpll_clk_mux@168 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x11 0x60>;
    						reg = <0x168>;
    					};
    
    					video2_dpll_clk_mux@16c {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x11 0x60>;
    						reg = <0x16c>;
    					};
    
    					wkupaon_iclk_mux@108 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x11 0x83>;
    						reg = <0x108>;
    						phandle = <0x55>;
    					};
    				};
    
    				clockdomains {
    				};
    
    				wkupaon_cm@1800 {
    					compatible = "ti,omap4-cm";
    					reg = <0x1800 0x100>;
    					#address-cells = <0x1>;
    					#size-cells = <0x1>;
    					ranges = <0x0 0x1800 0x100>;
    
    					clk@20 {
    						compatible = "ti,clkctrl";
    						reg = <0x20 0x6c>;
    						#clock-cells = <0x2>;
    						phandle = <0x8f>;
    					};
    				};
    			};
    
    			scm_conf@c000 {
    				compatible = "syscon";
    				reg = <0xc000 0x1000>;
    				phandle = <0x7>;
    			};
    		};
    
    		axi@0 {
    			compatible = "simple-bus";
    			#size-cells = <0x1>;
    			#address-cells = <0x1>;
    			ranges = <0x51000000 0x51000000 0x3000 0x0 0x20000000 0x10000000>;
    
    			pcie@51000000 {
    				reg = <0x51000000 0x2000 0x51002000 0x14c 0x1000 0x2000>;
    				reg-names = "rc_dbics", "ti_conf", "config";
    				interrupts = <0x0 0xe8 0x4 0x0 0xe9 0x4>;
    				#address-cells = <0x3>;
    				#size-cells = <0x2>;
    				device_type = "pci";
    				ranges = <0x81000000 0x0 0x0 0x3000 0x0 0x10000 0x82000000 0x0 0x20013000 0x13000 0x0 0xffed000>;
    				bus-range = <0x0 0xff>;
    				#interrupt-cells = <0x1>;
    				num-lanes = <0x1>;
    				linux,pci-domain = <0x0>;
    				ti,hwmods = "pcie1";
    				phys = <0x84>;
    				phy-names = "pcie-phy0";
    				ti,syscon-lane-sel = <0x85 0x18>;
    				interrupt-map-mask = <0x0 0x0 0x0 0x7>;
    				interrupt-map = <0x0 0x0 0x0 0x1 0x86 0x1 0x0 0x0 0x0 0x2 0x86 0x2 0x0 0x0 0x0 0x3 0x86 0x3 0x0 0x0 0x0 0x4 0x86 0x4>;
    				status = "ok";
    				compatible = "ti,dra746-pcie-rc", "ti,dra7-pcie";
    				gpios = <0x87 0x8 0x1>;
    
    				interrupt-controller {
    					interrupt-controller;
    					#address-cells = <0x0>;
    					#interrupt-cells = <0x1>;
    					phandle = <0x86>;
    				};
    			};
    
    			pcie_ep@51000000 {
    				reg = <0x51000000 0x28 0x51002000 0x14c 0x51001000 0x28 0x1000 0x10000000>;
    				reg-names = "ep_dbics", "ti_conf", "ep_dbics2", "addr_space";
    				interrupts = <0x0 0xe8 0x4>;
    				num-lanes = <0x1>;
    				num-ib-windows = <0x4>;
    				num-ob-windows = <0x10>;
    				ti,hwmods = "pcie1";
    				phys = <0x84>;
    				phy-names = "pcie-phy0";
    				ti,syscon-unaligned-access = <0x88 0x14 0x1>;
    				ti,syscon-lane-sel = <0x85 0x18>;
    				status = "disabled";
    				compatible = "ti,dra746-pcie-ep", "ti,dra7-pcie-ep";
    			};
    		};
    
    		axi@1 {
    			compatible = "simple-bus";
    			#size-cells = <0x1>;
    			#address-cells = <0x1>;
    			ranges = <0x51800000 0x51800000 0x3000 0x0 0x30000000 0x10000000>;
    			status = "disabled";
    
    			pcie@51800000 {
    				reg = <0x51800000 0x2000 0x51802000 0x14c 0x1000 0x2000>;
    				reg-names = "rc_dbics", "ti_conf", "config";
    				interrupts = <0x0 0x163 0x4 0x0 0x164 0x4>;
    				#address-cells = <0x3>;
    				#size-cells = <0x2>;
    				device_type = "pci";
    				ranges = <0x81000000 0x0 0x0 0x3000 0x0 0x10000 0x82000000 0x0 0x30013000 0x13000 0x0 0xffed000>;
    				bus-range = <0x0 0xff>;
    				#interrupt-cells = <0x1>;
    				num-lanes = <0x1>;
    				linux,pci-domain = <0x1>;
    				ti,hwmods = "pcie2";
    				phys = <0x89>;
    				phy-names = "pcie-phy0";
    				interrupt-map-mask = <0x0 0x0 0x0 0x7>;
    				interrupt-map = <0x0 0x0 0x0 0x1 0x8a 0x1 0x0 0x0 0x0 0x2 0x8a 0x2 0x0 0x0 0x0 0x3 0x8a 0x3 0x0 0x0 0x0 0x4 0x8a 0x4>;
    				compatible = "ti,dra746-pcie-rc", "ti,dra7-pcie";
    
    				interrupt-controller {
    					interrupt-controller;
    					#address-cells = <0x0>;
    					#interrupt-cells = <0x1>;
    					phandle = <0x8a>;
    				};
    			};
    		};
    
    		ocmcram@40300000 {
    			compatible = "mmio-sram";
    			reg = <0x40300000 0x80000>;
    			ranges = <0x0 0x40300000 0x80000>;
    			#address-cells = <0x1>;
    			#size-cells = <0x1>;
    
    			sram-hs@0 {
    				compatible = "ti,secure-ram";
    				reg = <0x0 0x0>;
    			};
    		};
    
    		ocmcram@40400000 {
    			status = "disabled";
    			compatible = "mmio-sram";
    			reg = <0x40400000 0x100000>;
    			ranges = <0x0 0x40400000 0x100000>;
    			#address-cells = <0x1>;
    			#size-cells = <0x1>;
    		};
    
    		ocmcram@40500000 {
    			status = "disabled";
    			compatible = "mmio-sram";
    			reg = <0x40500000 0x100000>;
    			ranges = <0x0 0x40500000 0x100000>;
    			#address-cells = <0x1>;
    			#size-cells = <0x1>;
    		};
    
    		bandgap@4a0021e0 {
    			reg = <0x4a0021e0 0xc 0x4a00232c 0xc 0x4a002380 0x2c 0x4a0023c0 0x3c 0x4a002564 0x8 0x4a002574 0x50>;
    			compatible = "ti,dra752-bandgap";
    			interrupts = <0x0 0x79 0x4>;
    			#thermal-sensor-cells = <0x1>;
    			phandle = <0xd9>;
    		};
    
    		dsp_system@40d00000 {
    			compatible = "syscon";
    			reg = <0x40d00000 0x100>;
    			phandle = <0xb3>;
    		};
    
    		padconf@4844a000 {
    			compatible = "ti,dra7-iodelay";
    			reg = <0x4844a000 0xd1c>;
    			#address-cells = <0x1>;
    			#size-cells = <0x0>;
    			#pinctrl-cells = <0x2>;
    
    			mmc1_iodelay_ddr_rev11_conf {
    				pinctrl-pin-array = <0x618 0x23c 0x21c 0x620 0x5f5 0x0 0x624 0x0 0x258 0x628 0x0 0x0 0x62c 0x37 0x0 0x630 0x193 0x78 0x634 0x0 0x0 0x638 0x0 0x0 0x63c 0x17 0x3c 0x640 0x0 0x0 0x644 0x0 0x0 0x648 0x19 0x3c 0x64c 0x0 0x0 0x650 0x0 0x0 0x654 0x0 0x0 0x658 0x0 0x0 0x65c 0x0 0x0>;
    			};
    
    			mmc1_iodelay_ddr50_rev20_conf {
    				pinctrl-pin-array = <0x618 0x434 0x14a 0x620 0x4f7 0x0 0x624 0x2d2 0x0 0x628 0x0 0x0 0x62c 0x0 0x0 0x630 0x2ef 0x0 0x634 0x0 0x0 0x638 0x14 0x0 0x63c 0x100 0x0 0x640 0x0 0x0 0x644 0x0 0x0 0x648 0x107 0x0 0x64c 0x0 0x0 0x650 0x0 0x0 0x654 0x0 0x0 0x658 0x0 0x0 0x65c 0x0 0x0>;
    			};
    
    			mmc1_iodelay_sdr104_rev11_conf {
    				pinctrl-pin-array = <0x620 0x427 0x11 0x628 0x0 0x0 0x62c 0x17 0x0 0x634 0x0 0x0 0x638 0x0 0x0 0x640 0x0 0x0 0x644 0x2 0x0 0x64c 0x0 0x0 0x650 0x0 0x0 0x658 0x0 0x0 0x65c 0x0 0x0>;
    			};
    
    			mmc1_iodelay_sdr104_rev20_conf {
    				pinctrl-pin-array = <0x620 0x258 0x190 0x628 0x0 0x0 0x62c 0x0 0x0 0x634 0x0 0x0 0x638 0x1e 0x0 0x640 0x0 0x0 0x644 0x0 0x0 0x64c 0x0 0x0 0x650 0x0 0x0 0x658 0x0 0x0 0x65c 0x0 0x0>;
    			};
    
    			mmc2_iodelay_hs200_rev11_conf {
    				pinctrl-pin-array = <0x190 0x26d 0x258 0x194 0x12c 0x0 0x1a8 0x2e3 0x258 0x1ac 0xf0 0x0 0x1b4 0x32c 0x258 0x1b8 0xf0 0x0 0x1c0 0x3ba 0x258 0x1c4 0x3c 0x0 0x1d0 0x53c 0x1a4 0x1d8 0x3a7 0x258 0x1dc 0x0 0x0 0x1e4 0x20d 0x258 0x1e8 0x78 0x0 0x1f0 0x2ff 0x258 0x1f4 0xe1 0x0 0x1fc 0x235 0x258 0x200 0x3c 0x0 0x364 0x3c9 0x258 0x368 0xb4 0x0>;
    			};
    
    			mmc2_iodelay_hs200_rev20_conf {
    				pinctrl-pin-array = <0x190 0x112 0x0 0x194 0xa2 0x0 0x1a8 0x191 0x0 0x1ac 0x49 0x0 0x1b4 0x1d1 0x0 0x1b8 0x73 0x0 0x1c0 0x279 0x0 0x1c4 0x2f 0x0 0x1d0 0x3a7 0x118 0x1d8 0x26d 0x0 0x1dc 0x0 0x0 0x1e4 0xb7 0x0 0x1e8 0x0 0x0 0x1f0 0x1d3 0x0 0x1f4 0x0 0x0 0x1fc 0x106 0x0 0x200 0x2e 0x0 0x364 0x2ac 0x0 0x368 0x4c 0x0>;
    			};
    
    			mmc2_iodelay_ddr_3_3v_rev11_conf {
    				pinctrl-pin-array = <0x18c 0x0 0x78 0x190 0x0 0x0 0x194 0xae 0x0 0x1a4 0x109 0x168 0x1a8 0x0 0x0 0x1ac 0xa8 0x0 0x1b0 0x0 0x78 0x1b4 0x0 0x0 0x1b8 0x88 0x0 0x1bc 0x0 0x78 0x1c0 0x0 0x0 0x1c4 0x0 0x0 0x1c8 0x11f 0x1a4 0x1d0 0x36f 0x0 0x1d4 0x90 0xf0 0x1d8 0x0 0x0 0x1dc 0x0 0x0 0x1e0 0x0 0x0 0x1e4 0x0 0x0 0x1e8 0x22 0x0 0x1ec 0x0 0x78 0x1f0 0x0 0x0 0x1f4 0x78 0x0 0x1f8 0x78 0xb4 0x1fc 0x0 0x0 0x200 0x0 0x0 0x360 0x0 0x0 0x364 0x0 0x0 0x368 0xb 0x0>;
    			};
    
    			mmc2_iodelay_ddr_1_8v_rev11_conf {
    				pinctrl-pin-array = <0x18c 0x0 0x0 0x190 0x0 0x0 0x194 0xae 0x0 0x1a4 0x112 0xf0 0x1a8 0x0 0x0 0x1ac 0xa8 0x0 0x1b0 0x0 0x3c 0x1b4 0x0 0x0 0x1b8 0x88 0x0 0x1bc 0x0 0x3c 0x1c0 0x0 0x0 0x1c4 0x0 0x0 0x1c8 0x202 0x168 0x1d0 0x36f 0x0 0x1d4 0xbb 0x78 0x1d8 0x0 0x0 0x1dc 0x0 0x0 0x1e0 0x0 0x0 0x1e4 0x0 0x0 0x1e8 0x22 0x0 0x1ec 0x0 0x3c 0x1f0 0x0 0x0 0x1f4 0x78 0x0 0x1f8 0x79 0x3c 0x1fc 0x0 0x0 0x200 0x0 0x0 0x360 0x0 0x0 0x364 0x0 0x0 0x368 0xb 0x0>;
    			};
    
    			mmc3_iodelay_manual1_conf {
    				pinctrl-pin-array = <0x678 0x196 0x0 0x680 0x293 0x0 0x684 0x0 0x0 0x688 0x0 0x0 0x68c 0x0 0x0 0x690 0x82 0x0 0x694 0x0 0x0 0x698 0x0 0x0 0x69c 0xa9 0x0 0x6a0 0x0 0x0 0x6a4 0x0 0x0 0x6a8 0x0 0x0 0x6ac 0x0 0x0 0x6b0 0x0 0x0 0x6b4 0x1c9 0x0 0x6b8 0x0 0x0 0x6bc 0x0 0x0>;
    			};
    
    			mmc4_iodelay_ds_rev11_conf {
    				pinctrl-pin-array = <0x840 0x0 0x0 0x848 0x0 0x0 0x84c 0x60 0x0 0x850 0x0 0x0 0x854 0x0 0x0 0x870 0x246 0x0 0x874 0x0 0x0 0x878 0x0 0x0 0x87c 0x187 0x0 0x880 0x0 0x0 0x884 0x0 0x0 0x888 0x231 0x0 0x88c 0x0 0x0 0x890 0x0 0x0 0x894 0x24c 0x0 0x898 0x0 0x0 0x89c 0x0 0x0>;
    			};
    
    			mmc4_iodelay_ds_rev20_conf {
    				pinctrl-pin-array = <0x840 0x0 0x0 0x848 0x0 0x0 0x84c 0x133 0x0 0x850 0x0 0x0 0x854 0x0 0x0 0x870 0x311 0x0 0x874 0x0 0x0 0x878 0x0 0x0 0x87c 0x265 0x0 0x880 0x0 0x0 0x884 0x0 0x0 0x888 0x2ab 0x0 0x88c 0x0 0x0 0x890 0x0 0x0 0x894 0x343 0x0 0x898 0x0 0x0 0x89c 0x0 0x0>;
    			};
    
    			mmc4_iodelay_sdr12_hs_sdr25_rev11_conf {
    				pinctrl-pin-array = <0x840 0x0 0x0 0x848 0xa5b 0x0 0x84c 0x624 0x0 0x850 0x0 0x0 0x854 0x0 0x0 0x870 0x779 0x0 0x874 0x0 0x0 0x878 0x0 0x0 0x87c 0x6b9 0x0 0x880 0x0 0x0 0x884 0x0 0x0 0x888 0x763 0x0 0x88c 0x0 0x0 0x890 0x0 0x0 0x894 0x77f 0x0 0x898 0x0 0x0 0x89c 0x0 0x0>;
    			};
    
    			mmc4_iodelay_sdr12_hs_sdr25_rev20_conf {
    				pinctrl-pin-array = <0x840 0x0 0x0 0x848 0x47b 0x0 0x84c 0x72a 0x0 0x850 0x0 0x0 0x854 0x0 0x0 0x870 0x875 0x0 0x874 0x0 0x0 0x878 0x0 0x0 0x87c 0x789 0x40 0x880 0x0 0x0 0x884 0x0 0x0 0x888 0x78f 0x80 0x88c 0x0 0x0 0x890 0x0 0x0 0x894 0x87c 0x2c 0x898 0x0 0x0 0x89c 0x0 0x0>;
    			};
    		};
    
    		dma-controller@4a056000 {
    			compatible = "ti,omap4430-sdma";
    			reg = <0x4a056000 0x1000>;
    			interrupts = <0x0 0x7 0x4 0x0 0x8 0x4 0x0 0x9 0x4 0x0 0xa 0x4>;
    			#dma-cells = <0x1>;
    			dma-channels = <0x20>;
    			dma-requests = <0x7f>;
    			ti,hwmods = "dma_system";
    			phandle = <0xe>;
    		};
    
    		edma@43300000 {
    			compatible = "ti,edma3-tpcc";
    			ti,hwmods = "tpcc";
    			reg = <0x43300000 0x100000>;
    			reg-names = "edma3_cc";
    			interrupts = <0x0 0x169 0x4 0x0 0x168 0x4 0x0 0x167 0x4>;
    			interrupt-names = "edma3_ccint", "edma3_mperr", "edma3_ccerrint";
    			dma-requests = <0x40>;
    			#dma-cells = <0x2>;
    			ti,tptcs = <0x8b 0x7 0x8c 0x0>;
    			phandle = <0xf>;
    		};
    
    		tptc@43400000 {
    			compatible = "ti,edma3-tptc";
    			ti,hwmods = "tptc0";
    			reg = <0x43400000 0x100000>;
    			interrupts = <0x0 0x172 0x4>;
    			interrupt-names = "edma3_tcerrint";
    			phandle = <0x8b>;
    		};
    
    		tptc@43500000 {
    			compatible = "ti,edma3-tptc";
    			ti,hwmods = "tptc1";
    			reg = <0x43500000 0x100000>;
    			interrupts = <0x0 0x173 0x4>;
    			interrupt-names = "edma3_tcerrint";
    			phandle = <0x8c>;
    		};
    
    		gpio@4ae10000 {
    			compatible = "ti,omap4-gpio";
    			reg = <0x4ae10000 0x200>;
    			interrupts = <0x0 0x18 0x4>;
    			ti,hwmods = "gpio1";
    			gpio-controller;
    			#gpio-cells = <0x2>;
    			interrupt-controller;
    			#interrupt-cells = <0x2>;
    			phandle = <0xa7>;
    		};
    
    		gpio@48055000 {
    			compatible = "ti,omap4-gpio";
    			reg = <0x48055000 0x200>;
    			interrupts = <0x0 0x19 0x4>;
    			ti,hwmods = "gpio2";
    			gpio-controller;
    			#gpio-cells = <0x2>;
    			interrupt-controller;
    			#interrupt-cells = <0x2>;
    			phandle = <0x87>;
    		};
    
    		gpio@48057000 {
    			compatible = "ti,omap4-gpio";
    			reg = <0x48057000 0x200>;
    			interrupts = <0x0 0x1a 0x4>;
    			ti,hwmods = "gpio3";
    			gpio-controller;
    			#gpio-cells = <0x2>;
    			interrupt-controller;
    			#interrupt-cells = <0x2>;
    		};
    
    		gpio@48059000 {
    			compatible = "ti,omap4-gpio";
    			reg = <0x48059000 0x200>;
    			interrupts = <0x0 0x1b 0x4>;
    			ti,hwmods = "gpio4";
    			gpio-controller;
    			#gpio-cells = <0x2>;
    			interrupt-controller;
    			#interrupt-cells = <0x2>;
    			phandle = <0xa9>;
    		};
    
    		gpio@4805b000 {
    			compatible = "ti,omap4-gpio";
    			reg = <0x4805b000 0x200>;
    			interrupts = <0x0 0x1c 0x4>;
    			ti,hwmods = "gpio5";
    			gpio-controller;
    			#gpio-cells = <0x2>;
    			interrupt-controller;
    			#interrupt-cells = <0x2>;
    		};
    
    		gpio@4805d000 {
    			compatible = "ti,omap4-gpio";
    			reg = <0x4805d000 0x200>;
    			interrupts = <0x0 0x1d 0x4>;
    			ti,hwmods = "gpio6";
    			gpio-controller;
    			#gpio-cells = <0x2>;
    			interrupt-controller;
    			#interrupt-cells = <0x2>;
    			phandle = <0xaf>;
    		};
    
    		gpio@48051000 {
    			compatible = "ti,omap4-gpio";
    			reg = <0x48051000 0x200>;
    			interrupts = <0x0 0x1e 0x4>;
    			ti,hwmods = "gpio7";
    			gpio-controller;
    			#gpio-cells = <0x2>;
    			interrupt-controller;
    			#interrupt-cells = <0x2>;
    			ti,no-reset-on-init;
    			ti,no-idle-on-init;
    			phandle = <0xaa>;
    		};
    
    		gpio@48053000 {
    			compatible = "ti,omap4-gpio";
    			reg = <0x48053000 0x200>;
    			interrupts = <0x0 0x74 0x4>;
    			ti,hwmods = "gpio8";
    			gpio-controller;
    			#gpio-cells = <0x2>;
    			interrupt-controller;
    			#interrupt-cells = <0x2>;
    		};
    
    		serial@4806a000 {
    			compatible = "ti,dra742-uart", "ti,omap4-uart";
    			reg = <0x4806a000 0x100>;
    			interrupts-extended = <0x1 0x0 0x43 0x4>;
    			ti,hwmods = "uart1";
    			clock-frequency = <0x2dc6c00>;
    			status = "disabled";
    			dmas = <0x8d 0x31 0x8d 0x32>;
    			dma-names = "tx", "rx";
    		};
    
    		serial@4806c000 {
    			compatible = "ti,dra742-uart", "ti,omap4-uart";
    			reg = <0x4806c000 0x100>;
    			interrupts = <0x0 0x44 0x4>;
    			ti,hwmods = "uart2";
    			clock-frequency = <0x2dc6c00>;
    			status = "disabled";
    			dmas = <0x8d 0x33 0x8d 0x34>;
    			dma-names = "tx", "rx";
    		};
    
    		serial@48020000 {
    			compatible = "ti,dra742-uart", "ti,omap4-uart";
    			reg = <0x48020000 0x100>;
    			interrupts = <0x0 0x45 0x4>;
    			ti,hwmods = "uart3";
    			clock-frequency = <0x2dc6c00>;
    			status = "okay";
    			dmas = <0x8d 0x35 0x8d 0x36>;
    			dma-names = "tx", "rx";
    			interrupts-extended = <0x1 0x0 0x45 0x4 0x8e 0x3f8>;
    		};
    
    		serial@4806e000 {
    			compatible = "ti,dra742-uart", "ti,omap4-uart";
    			reg = <0x4806e000 0x100>;
    			interrupts = <0x0 0x41 0x4>;
    			ti,hwmods = "uart4";
    			clock-frequency = <0x2dc6c00>;
    			status = "disabled";
    			dmas = <0x8d 0x37 0x8d 0x38>;
    			dma-names = "tx", "rx";
    		};
    
    		serial@48066000 {
    			compatible = "ti,dra742-uart", "ti,omap4-uart";
    			reg = <0x48066000 0x100>;
    			interrupts = <0x0 0x64 0x4>;
    			ti,hwmods = "uart5";
    			clock-frequency = <0x2dc6c00>;
    			status = "disabled";
    			dmas = <0x8d 0x3f 0x8d 0x40>;
    			dma-names = "tx", "rx";
    		};
    
    		serial@48068000 {
    			compatible = "ti,dra742-uart", "ti,omap4-uart";
    			reg = <0x48068000 0x100>;
    			interrupts = <0x0 0x65 0x4>;
    			ti,hwmods = "uart6";
    			clock-frequency = <0x2dc6c00>;
    			status = "disabled";
    			dmas = <0x8d 0x4f 0x8d 0x50>;
    			dma-names = "tx", "rx";
    		};
    
    		serial@48420000 {
    			compatible = "ti,dra742-uart", "ti,omap4-uart";
    			reg = <0x48420000 0x100>;
    			interrupts = <0x0 0xda 0x4>;
    			ti,hwmods = "uart7";
    			clock-frequency = <0x2dc6c00>;
    			status = "disabled";
    		};
    
    		serial@48422000 {
    			compatible = "ti,dra742-uart", "ti,omap4-uart";
    			reg = <0x48422000 0x100>;
    			interrupts = <0x0 0xdb 0x4>;
    			ti,hwmods = "uart8";
    			clock-frequency = <0x2dc6c00>;
    			status = "disabled";
    		};
    
    		serial@48424000 {
    			compatible = "ti,dra742-uart", "ti,omap4-uart";
    			reg = <0x48424000 0x100>;
    			interrupts = <0x0 0xdc 0x4>;
    			ti,hwmods = "uart9";
    			clock-frequency = <0x2dc6c00>;
    			status = "disabled";
    		};
    
    		serial@4ae2b000 {
    			compatible = "ti,dra742-uart", "ti,omap4-uart";
    			reg = <0x4ae2b000 0x100>;
    			interrupts = <0x0 0xdd 0x4>;
    			ti,hwmods = "uart10";
    			clock-frequency = <0x2dc6c00>;
    			status = "disabled";
    		};
    
    		mailbox@4a0f4000 {
    			compatible = "ti,omap4-mailbox";
    			reg = <0x4a0f4000 0x200>;
    			interrupts = <0x0 0x15 0x4 0x0 0x87 0x4 0x0 0x86 0x4>;
    			ti,hwmods = "mailbox1";
    			#mbox-cells = <0x1>;
    			ti,mbox-num-users = <0x3>;
    			ti,mbox-num-fifos = <0x8>;
    			status = "disabled";
    		};
    
    		mailbox@4883a000 {
    			compatible = "ti,omap4-mailbox";
    			reg = <0x4883a000 0x200>;
    			interrupts = <0x0 0xed 0x4 0x0 0xee 0x4 0x0 0xef 0x4 0x0 0xf0 0x4>;
    			ti,hwmods = "mailbox2";
    			#mbox-cells = <0x1>;
    			ti,mbox-num-users = <0x4>;
    			ti,mbox-num-fifos = <0xc>;
    			status = "disabled";
    		};
    
    		mailbox@4883c000 {
    			compatible = "ti,omap4-mailbox";
    			reg = <0x4883c000 0x200>;
    			interrupts = <0x0 0xf1 0x4 0x0 0xf2 0x4 0x0 0xf3 0x4 0x0 0xf4 0x4>;
    			ti,hwmods = "mailbox3";
    			#mbox-cells = <0x1>;
    			ti,mbox-num-users = <0x4>;
    			ti,mbox-num-fifos = <0xc>;
    			status = "disabled";
    		};
    
    		mailbox@4883e000 {
    			compatible = "ti,omap4-mailbox";
    			reg = <0x4883e000 0x200>;
    			interrupts = <0x0 0xf5 0x4 0x0 0xf6 0x4 0x0 0xf7 0x4 0x0 0xf8 0x4>;
    			ti,hwmods = "mailbox4";
    			#mbox-cells = <0x1>;
    			ti,mbox-num-users = <0x4>;
    			ti,mbox-num-fifos = <0xc>;
    			status = "disabled";
    		};
    
    		mailbox@48840000 {
    			compatible = "ti,omap4-mailbox";
    			reg = <0x48840000 0x200>;
    			interrupts = <0x0 0xf9 0x4 0x0 0xfa 0x4 0x0 0xfb 0x4 0x0 0xfc 0x4>;
    			ti,hwmods = "mailbox5";
    			#mbox-cells = <0x1>;
    			ti,mbox-num-users = <0x4>;
    			ti,mbox-num-fifos = <0xc>;
    			status = "okay";
    			phandle = <0x93>;
    
    			mbox_ipu1_ipc3x {
    				ti,mbox-tx = <0x6 0x2 0x2>;
    				ti,mbox-rx = <0x4 0x2 0x2>;
    				status = "okay";
    				phandle = <0x94>;
    			};
    
    			mbox_dsp1_ipc3x {
    				ti,mbox-tx = <0x5 0x2 0x2>;
    				ti,mbox-rx = <0x1 0x2 0x2>;
    				status = "okay";
    				phandle = <0xa3>;
    			};
    		};
    
    		mailbox@48842000 {
    			compatible = "ti,omap4-mailbox";
    			reg = <0x48842000 0x200>;
    			interrupts = <0x0 0xfd 0x4 0x0 0xfe 0x4 0x0 0xff 0x4 0x0 0x100 0x4>;
    			ti,hwmods = "mailbox6";
    			#mbox-cells = <0x1>;
    			ti,mbox-num-users = <0x4>;
    			ti,mbox-num-fifos = <0xc>;
    			status = "okay";
    			phandle = <0x9b>;
    
    			mbox_ipu2_ipc3x {
    				ti,mbox-tx = <0x6 0x2 0x2>;
    				ti,mbox-rx = <0x4 0x2 0x2>;
    				status = "okay";
    				phandle = <0x9c>;
    			};
    
    			mbox_dsp2_ipc3x {
    				ti,mbox-tx = <0x5 0x2 0x2>;
    				ti,mbox-rx = <0x1 0x2 0x2>;
    				status = "okay";
    				phandle = <0xd5>;
    			};
    		};
    
    		mailbox@48844000 {
    			compatible = "ti,omap4-mailbox";
    			reg = <0x48844000 0x200>;
    			interrupts = <0x0 0x101 0x4 0x0 0x102 0x4 0x0 0x103 0x4 0x0 0x104 0x4>;
    			ti,hwmods = "mailbox7";
    			#mbox-cells = <0x1>;
    			ti,mbox-num-users = <0x4>;
    			ti,mbox-num-fifos = <0xc>;
    			status = "disabled";
    		};
    
    		mailbox@48846000 {
    			compatible = "ti,omap4-mailbox";
    			reg = <0x48846000 0x200>;
    			interrupts = <0x0 0x105 0x4 0x0 0x106 0x4 0x0 0x107 0x4 0x0 0x108 0x4>;
    			ti,hwmods = "mailbox8";
    			#mbox-cells = <0x1>;
    			ti,mbox-num-users = <0x4>;
    			ti,mbox-num-fifos = <0xc>;
    			status = "disabled";
    		};
    
    		mailbox@4885e000 {
    			compatible = "ti,omap4-mailbox";
    			reg = <0x4885e000 0x200>;
    			interrupts = <0x0 0x109 0x4 0x0 0x10a 0x4 0x0 0x10b 0x4 0x0 0x10c 0x4>;
    			ti,hwmods = "mailbox9";
    			#mbox-cells = <0x1>;
    			ti,mbox-num-users = <0x4>;
    			ti,mbox-num-fifos = <0xc>;
    			status = "disabled";
    		};
    
    		mailbox@48860000 {
    			compatible = "ti,omap4-mailbox";
    			reg = <0x48860000 0x200>;
    			interrupts = <0x0 0x10d 0x4 0x0 0x10e 0x4 0x0 0x10f 0x4 0x0 0x110 0x4>;
    			ti,hwmods = "mailbox10";
    			#mbox-cells = <0x1>;
    			ti,mbox-num-users = <0x4>;
    			ti,mbox-num-fifos = <0xc>;
    			status = "disabled";
    		};
    
    		mailbox@48862000 {
    			compatible = "ti,omap4-mailbox";
    			reg = <0x48862000 0x200>;
    			interrupts = <0x0 0x111 0x4 0x0 0x112 0x4 0x0 0x113 0x4 0x0 0x114 0x4>;
    			ti,hwmods = "mailbox11";
    			#mbox-cells = <0x1>;
    			ti,mbox-num-users = <0x4>;
    			ti,mbox-num-fifos = <0xc>;
    			status = "disabled";
    		};
    
    		mailbox@48864000 {
    			compatible = "ti,omap4-mailbox";
    			reg = <0x48864000 0x200>;
    			interrupts = <0x0 0x115 0x4 0x0 0x116 0x4 0x0 0x117 0x4 0x0 0x118 0x4>;
    			ti,hwmods = "mailbox12";
    			#mbox-cells = <0x1>;
    			ti,mbox-num-users = <0x4>;
    			ti,mbox-num-fifos = <0xc>;
    			status = "disabled";
    		};
    
    		mailbox@48802000 {
    			compatible = "ti,omap4-mailbox";
    			reg = <0x48802000 0x200>;
    			interrupts = <0x0 0x17b 0x4 0x0 0x17c 0x4 0x0 0x17d 0x4 0x0 0x17e 0x4>;
    			ti,hwmods = "mailbox13";
    			#mbox-cells = <0x1>;
    			ti,mbox-num-users = <0x4>;
    			ti,mbox-num-fifos = <0xc>;
    			status = "disabled";
    		};
    
    		timer@4ae18000 {
    			compatible = "ti,omap5430-timer";
    			reg = <0x4ae18000 0x80>;
    			interrupts = <0x0 0x20 0x4>;
    			ti,hwmods = "timer1";
    			ti,timer-alwon;
    			clock-names = "fck";
    			clocks = <0x8f 0x20 0x18>;
    		};
    
    		timer@48032000 {
    			compatible = "ti,omap5430-timer";
    			reg = <0x48032000 0x80>;
    			interrupts = <0x0 0x21 0x4>;
    			ti,hwmods = "timer2";
    			clocks = <0x57 0x38 0x18>;
    			clock-names = "fck";
    		};
    
    		timer@48034000 {
    			compatible = "ti,omap5430-timer";
    			reg = <0x48034000 0x80>;
    			interrupts = <0x0 0x22 0x4>;
    			ti,hwmods = "timer3";
    			clocks = <0x57 0x40 0x18>;
    			clock-names = "fck";
    			phandle = <0x9d>;
    		};
    
    		timer@48036000 {
    			compatible = "ti,omap5430-timer";
    			reg = <0x48036000 0x80>;
    			interrupts = <0x0 0x23 0x4>;
    			ti,hwmods = "timer4";
    			clocks = <0x57 0x48 0x18>;
    			clock-names = "fck";
    			phandle = <0x9e>;
    		};
    
    		timer@48820000 {
    			compatible = "ti,omap5430-timer";
    			reg = <0x48820000 0x80>;
    			interrupts = <0x0 0x24 0x4>;
    			ti,hwmods = "timer5";
    			clocks = <0x90 0x18 0x18>;
    			clock-names = "fck";
    			phandle = <0xa4>;
    		};
    
    		timer@48822000 {
    			compatible = "ti,omap5430-timer";
    			reg = <0x48822000 0x80>;
    			interrupts = <0x0 0x25 0x4>;
    			ti,hwmods = "timer6";
    			clocks = <0x90 0x20 0x18>;
    			clock-names = "fck";
    			phandle = <0xd6>;
    		};
    
    		timer@48824000 {
    			compatible = "ti,omap5430-timer";
    			reg = <0x48824000 0x80>;
    			interrupts = <0x0 0x26 0x4>;
    			ti,hwmods = "timer7";
    			clocks = <0x90 0x28 0x18>;
    			clock-names = "fck";
    			phandle = <0x97>;
    		};
    
    		timer@48826000 {
    			compatible = "ti,omap5430-timer";
    			reg = <0x48826000 0x80>;
    			interrupts = <0x0 0x27 0x4>;
    			ti,hwmods = "timer8";
    			clocks = <0x90 0x30 0x18>;
    			clock-names = "fck";
    			phandle = <0x98>;
    		};
    
    		timer@4803e000 {
    			compatible = "ti,omap5430-timer";
    			reg = <0x4803e000 0x80>;
    			interrupts = <0x0 0x28 0x4>;
    			ti,hwmods = "timer9";
    			clocks = <0x57 0x50 0x18>;
    			clock-names = "fck";
    			phandle = <0x9f>;
    		};
    
    		timer@48086000 {
    			compatible = "ti,omap5430-timer";
    			reg = <0x48086000 0x80>;
    			interrupts = <0x0 0x29 0x4>;
    			ti,hwmods = "timer10";
    			clocks = <0x57 0x28 0x18>;
    			clock-names = "fck";
    			phandle = <0xa5>;
    		};
    
    		timer@48088000 {
    			compatible = "ti,omap5430-timer";
    			reg = <0x48088000 0x80>;
    			interrupts = <0x0 0x2a 0x4>;
    			ti,hwmods = "timer11";
    			clocks = <0x57 0x30 0x18>;
    			clock-names = "fck";
    			phandle = <0x95>;
    		};
    
    		timer@4ae20000 {
    			compatible = "ti,omap5430-timer";
    			reg = <0x4ae20000 0x80>;
    			interrupts = <0x0 0x5a 0x4>;
    			ti,hwmods = "timer12";
    			ti,timer-alwon;
    			ti,timer-secure;
    			clocks = <0x8f 0x28 0x18>;
    			clock-names = "fck";
    		};
    
    		timer@48828000 {
    			compatible = "ti,omap5430-timer";
    			reg = <0x48828000 0x80>;
    			interrupts = <0x0 0x153 0x4>;
    			ti,hwmods = "timer13";
    			clocks = <0x57 0xc8 0x18>;
    			clock-names = "fck";
    			phandle = <0xd7>;
    		};
    
    		timer@4882a000 {
    			compatible = "ti,omap5430-timer";
    			reg = <0x4882a000 0x80>;
    			interrupts = <0x0 0x154 0x4>;
    			ti,hwmods = "timer14";
    			clocks = <0x57 0xd0 0x18>;
    			clock-names = "fck";
    			phandle = <0x96>;
    		};
    
    		timer@4882c000 {
    			compatible = "ti,omap5430-timer";
    			reg = <0x4882c000 0x80>;
    			interrupts = <0x0 0x155 0x4>;
    			ti,hwmods = "timer15";
    			clocks = <0x57 0xd8 0x18>;
    			clock-names = "fck";
    		};
    
    		timer@4882e000 {
    			compatible = "ti,omap5430-timer";
    			reg = <0x4882e000 0x80>;
    			interrupts = <0x0 0x156 0x4>;
    			ti,hwmods = "timer16";
    			clocks = <0x57 0x130 0x18>;
    			clock-names = "fck";
    			assigned-clocks = <0x57 0x130 0x18>;
    			assigned-clock-parents = <0x91>;
    		};
    
    		wdt@4ae14000 {
    			compatible = "ti,omap3-wdt";
    			reg = <0x4ae14000 0x80>;
    			interrupts = <0x0 0x4b 0x4>;
    			ti,hwmods = "wd_timer2";
    		};
    
    		spinlock@4a0f6000 {
    			compatible = "ti,omap4-hwspinlock";
    			reg = <0x4a0f6000 0x1000>;
    			ti,hwmods = "spinlock";
    			#hwlock-cells = <0x1>;
    		};
    
    		dmm@4e000000 {
    			compatible = "ti,omap5-dmm";
    			reg = <0x4e000000 0x800>;
    			interrupts = <0x0 0x6c 0x4>;
    			ti,hwmods = "dmm";
    		};
    
    		ipu@58820000 {
    			compatible = "ti,dra7-ipu";
    			reg = <0x58820000 0x10000>;
    			reg-names = "l2ram";
    			ti,hwmods = "ipu1";
    			iommus = <0x92>;
    			ti,rproc-standby-info = <0x4a005520>;
    			status = "okay";
    			mboxes = <0x93 0x94>;
    			timers = <0x95 0x96>;
    			watchdog-timers = <0x97 0x98>;
    			memory-region = <0x99>;
    		};
    
    		ipu@55020000 {
    			compatible = "ti,dra7-ipu";
    			reg = <0x55020000 0x10000>;
    			reg-names = "l2ram";
    			ti,hwmods = "ipu2";
    			iommus = <0x9a>;
    			ti,rproc-standby-info = <0x4a008920>;
    			status = "okay";
    			mboxes = <0x9b 0x9c>;
    			timers = <0x9d>;
    			watchdog-timers = <0x9e 0x9f>;
    			memory-region = <0xa0>;
    		};
    
    		dsp@40800000 {
    			compatible = "ti,dra7-dsp";
    			reg = <0x40800000 0x48000 0x40e00000 0x8000 0x40f00000 0x8000>;
    			reg-names = "l2ram", "l1pram", "l1dram";
    			ti,hwmods = "dsp1";
    			syscon-bootreg = <0x9 0x55c>;
    			iommus = <0xa1 0xa2>;
    			ti,rproc-standby-info = <0x4a005420>;
    			status = "okay";
    			mboxes = <0x93 0xa3>;
    			timers = <0xa4>;
    			watchdog-timers = <0xa5>;
    			memory-region = <0xa6>;
    		};
    
    		i2c@48070000 {
    			compatible = "ti,omap4-i2c";
    			reg = <0x48070000 0x100>;
    			interrupts = <0x0 0x33 0x4>;
    			#address-cells = <0x1>;
    			#size-cells = <0x0>;
    			ti,hwmods = "i2c1";
    			status = "okay";
    			clock-frequency = <0x61a80>;
    
    			tps659038@58 {
    				compatible = "ti,tps659038";
    				reg = <0x58>;
    				interrupt-parent = <0xa7>;
    				interrupts = <0x0 0x8>;
    				#interrupt-cells = <0x2>;
    				interrupt-controller;
    				ti,system-power-controller;
    				ti,palmas-override-powerhold;
    				phandle = <0xa8>;
    
    				tps659038_pmic {
    					compatible = "ti,tps659038-pmic";
    
    					regulators {
    
    						smps12 {
    							regulator-name = "smps12";
    							regulator-min-microvolt = <0xcf850>;
    							regulator-max-microvolt = <0x1312d0>;
    							regulator-always-on;
    							regulator-boot-on;
    							phandle = <0x6>;
    						};
    
    						smps3 {
    							regulator-name = "smps3";
    							regulator-min-microvolt = <0x149970>;
    							regulator-max-microvolt = <0x149970>;
    							regulator-always-on;
    							regulator-boot-on;
    							phandle = <0xe2>;
    						};
    
    						smps45 {
    							regulator-name = "smps45";
    							regulator-min-microvolt = <0xcf850>;
    							regulator-max-microvolt = <0x1312d0>;
    							regulator-always-on;
    							regulator-boot-on;
    						};
    
    						smps6 {
    							regulator-name = "smps6";
    							regulator-min-microvolt = <0xcf850>;
    							regulator-max-microvolt = <0x118c30>;
    							regulator-always-on;
    							regulator-boot-on;
    						};
    
    						smps8 {
    							regulator-name = "smps8";
    							regulator-min-microvolt = <0x1b7740>;
    							regulator-max-microvolt = <0x1b7740>;
    							regulator-always-on;
    							regulator-boot-on;
    						};
    
    						ldo1 {
    							regulator-name = "ldo1";
    							regulator-min-microvolt = <0x1b7740>;
    							regulator-max-microvolt = <0x325aa0>;
    							regulator-boot-on;
    							regulator-always-on;
    							phandle = <0xb1>;
    						};
    
    						ldo2 {
    							regulator-name = "ldo2";
    							regulator-min-microvolt = <0x325aa0>;
    							regulator-max-microvolt = <0x325aa0>;
    							regulator-always-on;
    							regulator-boot-on;
    						};
    
    						ldo3 {
    							regulator-name = "ldo3";
    							regulator-min-microvolt = <0x1b7740>;
    							regulator-max-microvolt = <0x1b7740>;
    							regulator-always-on;
    							regulator-boot-on;
    						};
    
    						ldo4 {
    							regulator-name = "ldo4";
    							regulator-min-microvolt = <0x1b7740>;
    							regulator-max-microvolt = <0x1b7740>;
    							regulator-always-on;
    							regulator-boot-on;
    							phandle = <0xcd>;
    						};
    
    						ldo9 {
    							regulator-name = "ldo9";
    							regulator-min-microvolt = <0x100590>;
    							regulator-max-microvolt = <0x100590>;
    							regulator-always-on;
    							regulator-boot-on;
    						};
    
    						ldoln {
    							regulator-name = "ldoln";
    							regulator-min-microvolt = <0x1b7740>;
    							regulator-max-microvolt = <0x1b7740>;
    							regulator-always-on;
    							regulator-boot-on;
    							phandle = <0xcc>;
    						};
    
    						ldousb {
    							regulator-name = "ldousb";
    							regulator-min-microvolt = <0x325aa0>;
    							regulator-max-microvolt = <0x325aa0>;
    							regulator-boot-on;
    							phandle = <0xbb>;
    						};
    
    						regen1 {
    							regulator-name = "regen1";
    							regulator-boot-on;
    							regulator-always-on;
    							phandle = <0xe1>;
    						};
    					};
    				};
    
    				tps659038_rtc {
    					compatible = "ti,palmas-rtc";
    					interrupt-parent = <0xa8>;
    					interrupts = <0x8 0x2>;
    					wakeup-source;
    				};
    
    				tps659038_pwr_button {
    					compatible = "ti,palmas-pwrbutton";
    					interrupt-parent = <0xa8>;
    					interrupts = <0x1 0x2>;
    					wakeup-source;
    					ti,palmas-long-press-seconds = <0xc>;
    				};
    
    				tps659038_gpio {
    					compatible = "ti,palmas-gpio";
    					gpio-controller;
    					#gpio-cells = <0x2>;
    					phandle = <0xe3>;
    				};
    
    				tps659038_usb {
    					compatible = "ti,palmas-usb-vid";
    					ti,enable-vbus-detection;
    					vbus-gpio = <0xa9 0x15 0x0>;
    					phandle = <0xc1>;
    				};
    			};
    
    			tmp102@48 {
    				compatible = "ti,tmp102";
    				reg = <0x48>;
    				interrupt-parent = <0xaa>;
    				interrupts = <0x10 0x8>;
    				#thermal-sensor-cells = <0x1>;
    				phandle = <0xde>;
    			};
    
    			tlv320aic3104@18 {
    				#sound-dai-cells = <0x0>;
    				compatible = "ti,tlv320aic3104";
    				reg = <0x18>;
    				assigned-clocks = <0x4e>;
    				assigned-clock-parents = <0x6d>;
    				status = "okay";
    				adc-settle-ms = <0x28>;
    				AVDD-supply = <0xab>;
    				IOVDD-supply = <0xab>;
    				DRVDD-supply = <0xab>;
    				DVDD-supply = <0xac>;
    				phandle = <0xe9>;
    			};
    
    			eeprom@50 {
    				compatible = "atmel,24c32";
    				reg = <0x50>;
    			};
    		};
    
    		i2c@48072000 {
    			compatible = "ti,omap4-i2c";
    			reg = <0x48072000 0x100>;
    			interrupts = <0x0 0x34 0x4>;
    			#address-cells = <0x1>;
    			#size-cells = <0x0>;
    			ti,hwmods = "i2c2";
    			status = "disabled";
    		};
    
    		i2c@48060000 {
    			compatible = "ti,omap4-i2c";
    			reg = <0x48060000 0x100>;
    			interrupts = <0x0 0x38 0x4>;
    			#address-cells = <0x1>;
    			#size-cells = <0x0>;
    			ti,hwmods = "i2c3";
    			status = "okay";
    			clock-frequency = <0x61a80>;
    
    			rtc@6f {
    				compatible = "microchip,mcp7941x";
    				reg = <0x6f>;
    				interrupts-extended = <0x1 0x0 0x2 0x1 0x8e 0x424>;
    				interrupt-names = "irq", "wakeup";
    				vcc-supply = <0xab>;
    				wakeup-source;
    			};
    		};
    
    		i2c@4807a000 {
    			compatible = "ti,omap4-i2c";
    			reg = <0x4807a000 0x100>;
    			interrupts = <0x0 0x39 0x4>;
    			#address-cells = <0x1>;
    			#size-cells = <0x0>;
    			ti,hwmods = "i2c4";
    			status = "disabled";
    		};
    
    		i2c@4807c000 {
    			compatible = "ti,omap4-i2c";
    			reg = <0x4807c000 0x100>;
    			interrupts = <0x0 0x37 0x4>;
    			#address-cells = <0x1>;
    			#size-cells = <0x0>;
    			ti,hwmods = "i2c5";
    			status = "disabled";
    		};
    
    		mmc@4809c000 {
    			compatible = "ti,dra7-sdhci";
    			reg = <0x4809c000 0x400>;
    			interrupts = <0x0 0x4e 0x4>;
    			ti,hwmods = "mmc1";
    			status = "okay";
    			pbias-supply = <0xad>;
    			max-frequency = <0xb71b000>;
    			mmc-ddr-1_8v;
    			mmc-ddr-3_3v;
    			pinctrl-names = "default", "hs";
    			pinctrl-0 = <0xae>;
    			bus-width = <0x4>;
    			cd-gpios = <0xaf 0x1b 0x1>;
    			pinctrl-1 = <0xb0>;
    			vmmc-supply = <0xb1>;
    			no-1-8-v;
    		};
    
    		1w@480b2000 {
    			compatible = "ti,omap3-1w";
    			reg = <0x480b2000 0x1000>;
    			interrupts = <0x0 0x35 0x4>;
    			ti,hwmods = "hdq1w";
    		};
    
    		mmc@480b4000 {
    			compatible = "ti,dra7-sdhci";
    			reg = <0x480b4000 0x400>;
    			interrupts = <0x0 0x51 0x4>;
    			ti,hwmods = "mmc2";
    			status = "disabled";
    			max-frequency = <0xb71b000>;
    			sdhci-caps-mask = <0x7 0x0>;
    			mmc-hs200-1_8v;
    			mmc-ddr-1_8v;
    			mmc-ddr-3_3v;
    			pinctrl-names = "default";
    			pinctrl-0 = <0xb2>;
    			vmmc-supply = <0xab>;
    			vqmmc-supply = <0xab>;
    			bus-width = <0x8>;
    			non-removable;
    			no-1-8-v;
    		};
    
    		mmc@480ad000 {
    			compatible = "ti,dra7-sdhci";
    			reg = <0x480ad000 0x400>;
    			interrupts = <0x0 0x59 0x4>;
    			ti,hwmods = "mmc3";
    			status = "disabled";
    			max-frequency = <0x3d09000>;
    			sdhci-caps-mask = <0x0 0x400000>;
    		};
    
    		mmc@480d1000 {
    			compatible = "ti,dra7-sdhci";
    			reg = <0x480d1000 0x400>;
    			interrupts = <0x0 0x5b 0x4>;
    			ti,hwmods = "mmc4";
    			status = "disabled";
    			max-frequency = <0xb71b000>;
    			sdhci-caps-mask = <0x0 0x400000>;
    		};
    
    		mmu@40d01000 {
    			compatible = "ti,dra7-dsp-iommu";
    			reg = <0x40d01000 0x100>;
    			interrupts = <0x0 0x17 0x4>;
    			ti,hwmods = "mmu0_dsp1";
    			#iommu-cells = <0x0>;
    			ti,syscon-mmuconfig = <0xb3 0x0>;
    			phandle = <0xa1>;
    		};
    
    		mmu@40d02000 {
    			compatible = "ti,dra7-dsp-iommu";
    			reg = <0x40d02000 0x100>;
    			interrupts = <0x0 0x91 0x4>;
    			ti,hwmods = "mmu1_dsp1";
    			#iommu-cells = <0x0>;
    			ti,syscon-mmuconfig = <0xb3 0x1>;
    			phandle = <0xa2>;
    		};
    
    		mmu@58882000 {
    			compatible = "ti,dra7-iommu";
    			reg = <0x58882000 0x100>;
    			interrupts = <0x0 0x18b 0x4>;
    			ti,hwmods = "mmu_ipu1";
    			#iommu-cells = <0x0>;
    			ti,iommu-bus-err-back;
    			phandle = <0x92>;
    		};
    
    		mmu@55082000 {
    			compatible = "ti,dra7-iommu";
    			reg = <0x55082000 0x100>;
    			interrupts = <0x0 0x18c 0x4>;
    			ti,hwmods = "mmu_ipu2";
    			#iommu-cells = <0x0>;
    			ti,iommu-bus-err-back;
    			phandle = <0x9a>;
    		};
    
    		pruss-soc-bus@4b226004 {
    			compatible = "ti,am5728-pruss-soc-bus";
    			reg = <0x4b226004 0x4>;
    			ti,hwmods = "pruss1";
    			#address-cells = <0x1>;
    			#size-cells = <0x1>;
    			ranges;
    			status = "okay";
    
    			pruss@4b200000 {
    				compatible = "ti,am5728-pruss";
    				reg = <0x4b200000 0x80000>;
    				interrupts = <0x0 0xba 0x4 0x0 0xbb 0x4 0x0 0xbc 0x4 0x0 0xbd 0x4 0x0 0xbe 0x4 0x0 0xbf 0x4 0x0 0xc0 0x4 0x0 0xc1 0x4>;
    				interrupt-names = "host2", "host3", "host4", "host5", "host6", "host7", "host8", "host9";
    				#address-cells = <0x1>;
    				#size-cells = <0x1>;
    				ranges;
    				status = "okay";
    
    				memories@4b200000 {
    					reg = <0x4b200000 0x2000 0x4b202000 0x2000 0x4b210000 0x8000 0x4b22e000 0x31c 0x4b230000 0x60>;
    					reg-names = "dram0", "dram1", "shrdram2", "iep", "ecap";
    				};
    
    				cfg@4b226000 {
    					compatible = "syscon";
    					reg = <0x4b226000 0x2000>;
    				};
    
    				mii-rt@4b232000 {
    					compatible = "syscon";
    					reg = <0x4b232000 0x58>;
    				};
    
    				interrupt-controller@4b220000 {
    					compatible = "ti,am5728-pruss-intc";
    					reg = <0x4b220000 0x2000>;
    					interrupt-controller;
    					#interrupt-cells = <0x1>;
    					phandle = <0xb4>;
    				};
    
    				pru@4b234000 {
    					compatible = "ti,am5728-pru";
    					reg = <0x4b234000 0x3000 0x4b222000 0x400 0x4b222400 0x100>;
    					reg-names = "iram", "control", "debug";
    					firmware-name = "am57xx-pru1_0-fw";
    					interrupt-parent = <0xb4>;
    					interrupts = <0x10 0x11>;
    					interrupt-names = "vring", "kick";
    				};
    
    				pru@4b238000 {
    					compatible = "ti,am5728-pru";
    					reg = <0x4b238000 0x3000 0x4b224000 0x400 0x4b224400 0x100>;
    					reg-names = "iram", "control", "debug";
    					firmware-name = "am57xx-pru1_1-fw";
    					interrupt-parent = <0xb4>;
    					interrupts = <0x12 0x13>;
    					interrupt-names = "vring", "kick";
    				};
    
    				mdio@4b232400 {
    					compatible = "ti,davinci_mdio";
    					reg = <0x4b232400 0x90>;
    					#address-cells = <0x1>;
    					#size-cells = <0x0>;
    					clocks = <0xb5>;
    					clock-names = "fck";
    					bus_freq = <0xf4240>;
    					status = "disabled";
    				};
    			};
    		};
    
    		pruss-soc-bus@4b2a6004 {
    			compatible = "ti,am5728-pruss-soc-bus";
    			reg = <0x4b2a6004 0x4>;
    			ti,hwmods = "pruss2";
    			#address-cells = <0x1>;
    			#size-cells = <0x1>;
    			ranges;
    			status = "okay";
    
    			pruss@4b280000 {
    				compatible = "ti,am5728-pruss";
    				reg = <0x4b280000 0x80000>;
    				interrupts = <0x0 0xc4 0x4 0x0 0xc5 0x4 0x0 0xc6 0x4 0x0 0xc7 0x4 0x0 0xc8 0x4 0x0 0xc9 0x4 0x0 0xca 0x4 0x0 0xcb 0x4>;
    				interrupt-names = "host2", "host3", "host4", "host5", "host6", "host7", "host8", "host9";
    				#address-cells = <0x1>;
    				#size-cells = <0x1>;
    				ranges;
    				status = "okay";
    
    				memories@4b280000 {
    					reg = <0x4b280000 0x2000 0x4b282000 0x2000 0x4b290000 0x8000 0x4b2ae000 0x31c 0x4b2b0000 0x60>;
    					reg-names = "dram0", "dram1", "shrdram2", "iep", "ecap";
    				};
    
    				cfg@4b2a6000 {
    					compatible = "syscon";
    					reg = <0x4b2a6000 0x2000>;
    				};
    
    				mii-rt@4b2b2000 {
    					compatible = "syscon";
    					reg = <0x4b2b2000 0x58>;
    				};
    
    				interrupt-controller@4b2a0000 {
    					compatible = "ti,am5728-pruss-intc";
    					reg = <0x4b2a0000 0x2000>;
    					interrupt-controller;
    					#interrupt-cells = <0x1>;
    					phandle = <0xb6>;
    				};
    
    				pru@4b2b4000 {
    					compatible = "ti,am5728-pru";
    					reg = <0x4b2b4000 0x3000 0x4b2a2000 0x400 0x4b2a2400 0x100>;
    					reg-names = "iram", "control", "debug";
    					firmware-name = "am57xx-pru2_0-fw";
    					interrupt-parent = <0xb6>;
    					interrupts = <0x10 0x11>;
    					interrupt-names = "vring", "kick";
    				};
    
    				pru@4b2b8000 {
    					compatible = "ti,am5728-pru";
    					reg = <0x4b2b8000 0x3000 0x4b2a4000 0x400 0x4b2a4400 0x100>;
    					reg-names = "iram", "control", "debug";
    					firmware-name = "am57xx-pru2_1-fw";
    					interrupt-parent = <0xb6>;
    					interrupts = <0x12 0x13>;
    					interrupt-names = "vring", "kick";
    				};
    
    				mdio@4b2b2400 {
    					compatible = "ti,davinci_mdio";
    					reg = <0x4b2b2400 0x90>;
    					#address-cells = <0x1>;
    					#size-cells = <0x0>;
    					clocks = <0xb5>;
    					clock-names = "fck";
    					bus_freq = <0xf4240>;
    					status = "disabled";
    				};
    			};
    		};
    
    		regulator-abb-mpu {
    			compatible = "ti,abb-v3";
    			regulator-name = "abb_mpu";
    			#address-cells = <0x0>;
    			#size-cells = <0x0>;
    			clocks = <0x11>;
    			ti,settling-time = <0x32>;
    			ti,clock-cycles = <0x10>;
    			reg = <0x4ae07ddc 0x4 0x4ae07de0 0x4 0x4ae06014 0x4 0x4a003b20 0xc 0x4ae0c158 0x4>;
    			reg-names = "setup-address", "control-address", "int-address", "efuse-address", "ldo-address";
    			ti,tranxdone-status-mask = <0x80>;
    			ti,ldovbb-override-mask = <0x400>;
    			ti,ldovbb-vset-mask = <0x1f>;
    			ti,abb_info = <0x102ca0 0x0 0x0 0x0 0x2000000 0x1f00000 0x11b340 0x0 0x4 0x0 0x2000000 0x1f00000 0x127690 0x0 0x8 0x0 0x2000000 0x1f00000>;
    			phandle = <0x5>;
    		};
    
    		regulator-abb-ivahd {
    			compatible = "ti,abb-v3";
    			regulator-name = "abb_ivahd";
    			#address-cells = <0x0>;
    			#size-cells = <0x0>;
    			clocks = <0x11>;
    			ti,settling-time = <0x32>;
    			ti,clock-cycles = <0x10>;
    			reg = <0x4ae07e34 0x4 0x4ae07e24 0x4 0x4ae06010 0x4 0x4a0025cc 0xc 0x4a002470 0x4>;
    			reg-names = "setup-address", "control-address", "int-address", "efuse-address", "ldo-address";
    			ti,tranxdone-status-mask = <0x40000000>;
    			ti,ldovbb-override-mask = <0x400>;
    			ti,ldovbb-vset-mask = <0x1f>;
    			ti,abb_info = <0x101918 0x0 0x0 0x0 0x2000000 0x1f00000 0x118c30 0x0 0x4 0x0 0x2000000 0x1f00000 0x1312d0 0x0 0x8 0x0 0x2000000 0x1f00000>;
    		};
    
    		regulator-abb-dspeve {
    			compatible = "ti,abb-v3";
    			regulator-name = "abb_dspeve";
    			#address-cells = <0x0>;
    			#size-cells = <0x0>;
    			clocks = <0x11>;
    			ti,settling-time = <0x32>;
    			ti,clock-cycles = <0x10>;
    			reg = <0x4ae07e30 0x4 0x4ae07e20 0x4 0x4ae06010 0x4 0x4a0025e0 0xc 0x4a00246c 0x4>;
    			reg-names = "setup-address", "control-address", "int-address", "efuse-address", "ldo-address";
    			ti,tranxdone-status-mask = <0x20000000>;
    			ti,ldovbb-override-mask = <0x400>;
    			ti,ldovbb-vset-mask = <0x1f>;
    			ti,abb_info = <0x101918 0x0 0x0 0x0 0x2000000 0x1f00000 0x118c30 0x0 0x4 0x0 0x2000000 0x1f00000 0x1312d0 0x0 0x8 0x0 0x2000000 0x1f00000>;
    		};
    
    		regulator-abb-gpu {
    			compatible = "ti,abb-v3";
    			regulator-name = "abb_gpu";
    			#address-cells = <0x0>;
    			#size-cells = <0x0>;
    			clocks = <0x11>;
    			ti,settling-time = <0x32>;
    			ti,clock-cycles = <0x10>;
    			reg = <0x4ae07de4 0x4 0x4ae07de8 0x4 0x4ae06010 0x4 0x4a003b08 0xc 0x4ae0c154 0x4>;
    			reg-names = "setup-address", "control-address", "int-address", "efuse-address", "ldo-address";
    			ti,tranxdone-status-mask = <0x10000000>;
    			ti,ldovbb-override-mask = <0x400>;
    			ti,ldovbb-vset-mask = <0x1f>;
    			ti,abb_info = <0x10a1d0 0x0 0x0 0x0 0x2000000 0x1f00000 0x127690 0x0 0x4 0x0 0x2000000 0x1f00000 0x138800 0x0 0x8 0x0 0x2000000 0x1f00000>;
    		};
    
    		spi@48098000 {
    			compatible = "ti,omap4-mcspi";
    			reg = <0x48098000 0x200>;
    			interrupts = <0x0 0x3c 0x4>;
    			#address-cells = <0x1>;
    			#size-cells = <0x0>;
    			ti,hwmods = "mcspi1";
    			ti,spi-num-cs = <0x4>;
    			dmas = <0x8d 0x23 0x8d 0x24 0x8d 0x25 0x8d 0x26 0x8d 0x27 0x8d 0x28 0x8d 0x29 0x8d 0x2a>;
    			dma-names = "tx0", "rx0", "tx1", "rx1", "tx2", "rx2", "tx3", "rx3";
    			status = "disabled";
    		};
    
    		spi@4809a000 {
    			compatible = "ti,omap4-mcspi";
    			reg = <0x4809a000 0x200>;
    			interrupts = <0x0 0x3d 0x4>;
    			#address-cells = <0x1>;
    			#size-cells = <0x0>;
    			ti,hwmods = "mcspi2";
    			ti,spi-num-cs = <0x2>;
    			dmas = <0x8d 0x2b 0x8d 0x2c 0x8d 0x2d 0x8d 0x2e>;
    			dma-names = "tx0", "rx0", "tx1", "rx1";
    			status = "disabled";
    		};
    
    		spi@480b8000 {
    			compatible = "ti,omap4-mcspi";
    			reg = <0x480b8000 0x200>;
    			interrupts = <0x0 0x56 0x4>;
    			#address-cells = <0x1>;
    			#size-cells = <0x0>;
    			ti,hwmods = "mcspi3";
    			ti,spi-num-cs = <0x2>;
    			dmas = <0x8d 0xf 0x8d 0x10>;
    			dma-names = "tx0", "rx0";
    			status = "disabled";
    		};
    
    		spi@480ba000 {
    			compatible = "ti,omap4-mcspi";
    			reg = <0x480ba000 0x200>;
    			interrupts = <0x0 0x2b 0x4>;
    			#address-cells = <0x1>;
    			#size-cells = <0x0>;
    			ti,hwmods = "mcspi4";
    			ti,spi-num-cs = <0x1>;
    			dmas = <0x8d 0x46 0x8d 0x47>;
    			dma-names = "tx0", "rx0";
    			status = "disabled";
    		};
    
    		qspi@4b300000 {
    			compatible = "ti,dra7xxx-qspi";
    			reg = <0x4b300000 0x100 0x5c000000 0x4000000>;
    			reg-names = "qspi_base", "qspi_mmap";
    			syscon-chipselects = <0x9 0x558>;
    			#address-cells = <0x1>;
    			#size-cells = <0x0>;
    			ti,hwmods = "qspi";
    			clocks = <0x57 0x138 0x19>;
    			clock-names = "fck";
    			num-cs = <0x4>;
    			interrupts = <0x0 0x157 0x4>;
    			status = "disabled";
    		};
    
    		ocp2scp@4a090000 {
    			compatible = "ti,omap-ocp2scp";
    			#address-cells = <0x1>;
    			#size-cells = <0x1>;
    			ranges;
    			reg = <0x4a090000 0x20>;
    			ti,hwmods = "ocp2scp3";
    
    			phy@4a096000 {
    				compatible = "ti,phy-pipe3-sata";
    				reg = <0x4a096000 0x80 0x4a096400 0x64 0x4a096800 0x40>;
    				reg-names = "phy_rx", "phy_tx", "pll_ctrl";
    				syscon-phy-power = <0x9 0x374>;
    				clocks = <0x11 0xb7 0x68 0x8>;
    				clock-names = "sysclk", "refclk";
    				syscon-pllreset = <0x9 0x3fc>;
    				#phy-cells = <0x0>;
    				phandle = <0xb9>;
    			};
    
    			pciephy@4a094000 {
    				compatible = "ti,phy-pipe3-pcie";
    				reg = <0x4a094000 0x80 0x4a094400 0x64>;
    				reg-names = "phy_rx", "phy_tx";
    				syscon-phy-power = <0x85 0x1c>;
    				syscon-pcs = <0x85 0x10>;
    				clocks = <0x3e 0x3f 0xb7 0x90 0x8 0xb7 0x90 0x9 0xb7 0x90 0xa 0xb8 0x11>;
    				clock-names = "dpll_ref", "dpll_ref_m2", "wkupclk", "refclk", "div-clk", "phy-div", "sysclk";
    				#phy-cells = <0x0>;
    				phandle = <0x84>;
    			};
    
    			pciephy@4a095000 {
    				compatible = "ti,phy-pipe3-pcie";
    				reg = <0x4a095000 0x80 0x4a095400 0x64>;
    				reg-names = "phy_rx", "phy_tx";
    				syscon-phy-power = <0x85 0x20>;
    				syscon-pcs = <0x85 0x10>;
    				clocks = <0x3e 0x3f 0xb7 0x98 0x8 0xb7 0x98 0x9 0xb7 0x98 0xa 0xb8 0x11>;
    				clock-names = "dpll_ref", "dpll_ref_m2", "wkupclk", "refclk", "div-clk", "phy-div", "sysclk";
    				#phy-cells = <0x0>;
    				status = "disabled";
    				phandle = <0x89>;
    			};
    		};
    
    		sata@4a141100 {
    			compatible = "snps,dwc-ahci";
    			reg = <0x4a140000 0x1100 0x4a141100 0x7>;
    			interrupts = <0x0 0x31 0x4>;
    			phys = <0xb9>;
    			phy-names = "sata-phy";
    			clocks = <0xb7 0x68 0x8>;
    			ti,hwmods = "sata";
    			ports-implemented = <0x1>;
    			status = "okay";
    		};
    
    		rtc@48838000 {
    			compatible = "ti,am3352-rtc";
    			reg = <0x48838000 0x100>;
    			interrupts = <0x0 0xd9 0x4 0x0 0xd9 0x4>;
    			ti,hwmods = "rtcss";
    			clocks = <0x50>;
    		};
    
    		ocp2scp@4a080000 {
    			compatible = "ti,omap-ocp2scp";
    			#address-cells = <0x1>;
    			#size-cells = <0x1>;
    			ranges;
    			reg = <0x4a080000 0x20>;
    			ti,hwmods = "ocp2scp1";
    
    			phy@4a084000 {
    				compatible = "ti,dra7x-usb2", "ti,omap-usb2";
    				reg = <0x4a084000 0x400>;
    				syscon-phy-power = <0x9 0x300>;
    				clocks = <0xba 0xb7 0xd0 0x8>;
    				clock-names = "wkupclk", "refclk";
    				#phy-cells = <0x0>;
    				phy-supply = <0xbb>;
    				phandle = <0xbf>;
    			};
    
    			phy@4a085000 {
    				compatible = "ti,dra7x-usb2-phy2", "ti,omap-usb2";
    				reg = <0x4a085000 0x400>;
    				syscon-phy-power = <0x9 0xe74>;
    				clocks = <0xbc 0xb7 0x20 0x8>;
    				clock-names = "wkupclk", "refclk";
    				#phy-cells = <0x0>;
    				phy-supply = <0xbb>;
    				phandle = <0xc2>;
    			};
    
    			phy@4a084400 {
    				compatible = "ti,omap-usb3";
    				reg = <0x4a084400 0x80 0x4a084800 0x64 0x4a084c00 0x40>;
    				reg-names = "phy_rx", "phy_tx", "pll_ctrl";
    				syscon-phy-power = <0x9 0x370>;
    				clocks = <0xbd 0x11 0xb7 0xd0 0x8>;
    				clock-names = "wkupclk", "sysclk", "refclk";
    				#phy-cells = <0x0>;
    				phandle = <0xc0>;
    			};
    		};
    
    		target-module@4a0dd000 {
    			compatible = "ti,sysc-omap4-sr", "ti,sysc";
    			ti,hwmods = "smartreflex_core";
    			reg = <0x4a0dd038 0x4>;
    			reg-names = "sysc";
    			ti,sysc-mask = <0x4000000>;
    			ti,sysc-sidle = <0x0 0x1 0x2 0x3>;
    			clocks = <0xbe 0x18 0x0>;
    			clock-names = "fck";
    			#address-cells = <0x1>;
    			#size-cells = <0x1>;
    			ranges = <0x0 0x4a0dd000 0x1000>;
    		};
    
    		target-module@4a0d9000 {
    			compatible = "ti,sysc-omap4-sr", "ti,sysc";
    			ti,hwmods = "smartreflex_mpu";
    			reg = <0x4a0d9038 0x4>;
    			reg-names = "sysc";
    			ti,sysc-mask = <0x4000000>;
    			ti,sysc-sidle = <0x0 0x1 0x2 0x3>;
    			clocks = <0xbe 0x8 0x0>;
    			clock-names = "fck";
    			#address-cells = <0x1>;
    			#size-cells = <0x1>;
    			ranges = <0x0 0x4a0d9000 0x1000>;
    		};
    
    		omap_dwc3_1@48880000 {
    			compatible = "ti,dwc3";
    			ti,hwmods = "usb_otg_ss1";
    			reg = <0x48880000 0x10000>;
    			interrupts = <0x0 0x48 0x4>;
    			#address-cells = <0x1>;
    			#size-cells = <0x1>;
    			utmi-mode = <0x2>;
    			ranges;
    
    			usb@48890000 {
    				compatible = "snps,dwc3";
    				reg = <0x48890000 0x17000>;
    				interrupts = <0x0 0x47 0x4 0x0 0x47 0x4 0x0 0x48 0x4>;
    				interrupt-names = "peripheral", "host", "otg";
    				phys = <0xbf 0xc0>;
    				phy-names = "usb2-phy", "usb3-phy";
    				maximum-speed = "super-speed";
    				dr_mode = "host";
    				snps,dis_u3_susphy_quirk;
    				snps,dis_u2_susphy_quirk;
    			};
    		};
    
    		omap_dwc3_2@488c0000 {
    			compatible = "ti,dwc3";
    			ti,hwmods = "usb_otg_ss2";
    			reg = <0x488c0000 0x10000>;
    			interrupts = <0x0 0x57 0x4>;
    			#address-cells = <0x1>;
    			#size-cells = <0x1>;
    			utmi-mode = <0x2>;
    			ranges;
    			extcon = <0xc1>;
    
    			usb@488d0000 {
    				compatible = "snps,dwc3";
    				reg = <0x488d0000 0x17000>;
    				interrupts = <0x0 0x49 0x4 0x0 0x49 0x4 0x0 0x57 0x4>;
    				interrupt-names = "peripheral", "host", "otg";
    				phys = <0xc2>;
    				phy-names = "usb2-phy";
    				maximum-speed = "high-speed";
    				dr_mode = "peripheral";
    				snps,dis_u3_susphy_quirk;
    				snps,dis_u2_susphy_quirk;
    				snps,dis_metastability_quirk;
    			};
    		};
    
    		omap_dwc3_3@48900000 {
    			compatible = "ti,dwc3";
    			ti,hwmods = "usb_otg_ss3";
    			reg = <0x48900000 0x10000>;
    			interrupts = <0x0 0x158 0x4>;
    			#address-cells = <0x1>;
    			#size-cells = <0x1>;
    			utmi-mode = <0x2>;
    			ranges;
    			status = "disabled";
    
    			usb@48910000 {
    				compatible = "snps,dwc3";
    				reg = <0x48910000 0x17000>;
    				interrupts = <0x0 0x58 0x4 0x0 0x58 0x4 0x0 0x158 0x4>;
    				interrupt-names = "peripheral", "host", "otg";
    				maximum-speed = "high-speed";
    				dr_mode = "otg";
    				snps,dis_u3_susphy_quirk;
    				snps,dis_u2_susphy_quirk;
    			};
    		};
    
    		elm@48078000 {
    			compatible = "ti,am3352-elm";
    			reg = <0x48078000 0xfc0>;
    			interrupts = <0x0 0x1 0x4>;
    			ti,hwmods = "elm";
    			status = "disabled";
    		};
    
    		gpmc@50000000 {
    			compatible = "ti,am3352-gpmc";
    			ti,hwmods = "gpmc";
    			reg = <0x50000000 0x37c>;
    			interrupts = <0x0 0xf 0x4>;
    			dmas = <0xc3 0x4 0x0>;
    			dma-names = "rxtx";
    			gpmc,num-cs = <0x8>;
    			gpmc,num-waitpins = <0x2>;
    			#address-cells = <0x2>;
    			#size-cells = <0x1>;
    			interrupt-controller;
    			#interrupt-cells = <0x2>;
    			gpio-controller;
    			#gpio-cells = <0x2>;
    			status = "disabled";
    		};
    
    		atl@4843c000 {
    			compatible = "ti,dra7-atl";
    			reg = <0x4843c000 0x3ff>;
    			ti,hwmods = "atl";
    			ti,provided-clocks = <0xc4 0xc5 0xc6 0xc7>;
    			clocks = <0x10 0x0 0x1a>;
    			clock-names = "fck";
    			status = "disabled";
    		};
    
    		mcasp@48460000 {
    			compatible = "ti,dra7-mcasp-audio";
    			ti,hwmods = "mcasp1";
    			reg = <0x48460000 0x2000 0x45800000 0x1000>;
    			reg-names = "mpu", "dat";
    			interrupts = <0x0 0x68 0x4 0x0 0x67 0x4>;
    			interrupt-names = "tx", "rx";
    			dmas = <0xc3 0x81 0x1 0xc3 0x80 0x1>;
    			dma-names = "tx", "rx";
    			clocks = <0x90 0x10 0x16 0x90 0x10 0x18 0x90 0x10 0x1c>;
    			clock-names = "fck", "ahclkx", "ahclkr";
    			status = "disabled";
    		};
    
    		mcasp@48464000 {
    			compatible = "ti,dra7-mcasp-audio";
    			ti,hwmods = "mcasp2";
    			reg = <0x48464000 0x2000 0x45c00000 0x1000>;
    			reg-names = "mpu", "dat";
    			interrupts = <0x0 0x95 0x4 0x0 0x94 0x4>;
    			interrupt-names = "tx", "rx";
    			dmas = <0xc3 0x83 0x1 0xc3 0x82 0x1>;
    			dma-names = "tx", "rx";
    			clocks = <0x57 0x160 0x16 0x57 0x160 0x18 0x57 0x160 0x1c>;
    			clock-names = "fck", "ahclkx", "ahclkr";
    			status = "disabled";
    		};
    
    		mcasp@48468000 {
    			compatible = "ti,dra7-mcasp-audio";
    			ti,hwmods = "mcasp3";
    			reg = <0x48468000 0x2000 0x46000000 0x1000>;
    			reg-names = "mpu", "dat";
    			interrupts = <0x0 0x97 0x4 0x0 0x96 0x4>;
    			interrupt-names = "tx", "rx";
    			dmas = <0xc3 0x85 0x1 0xc3 0x84 0x1>;
    			dma-names = "tx", "rx";
    			clocks = <0x57 0x168 0x16 0x57 0x168 0x18>;
    			clock-names = "fck", "ahclkx";
    			status = "okay";
    			#sound-dai-cells = <0x0>;
    			assigned-clocks = <0x57 0x168 0x18>;
    			assigned-clock-parents = <0x60>;
    			op-mode = <0x0>;
    			tdm-slots = <0x2>;
    			serial-dir = <0x1 0x2 0x0 0x0>;
    			tx-num-evt = <0x20>;
    			rx-num-evt = <0x20>;
    			phandle = <0xe8>;
    		};
    
    		mcasp@4846c000 {
    			compatible = "ti,dra7-mcasp-audio";
    			ti,hwmods = "mcasp4";
    			reg = <0x4846c000 0x2000 0x48436000 0x1000>;
    			reg-names = "mpu", "dat";
    			interrupts = <0x0 0x99 0x4 0x0 0x98 0x4>;
    			interrupt-names = "tx", "rx";
    			dmas = <0xc3 0x87 0x1 0xc3 0x86 0x1>;
    			dma-names = "tx", "rx";
    			clocks = <0x57 0x198 0x16 0x57 0x198 0x18>;
    			clock-names = "fck", "ahclkx";
    			status = "disabled";
    		};
    
    		mcasp@48470000 {
    			compatible = "ti,dra7-mcasp-audio";
    			ti,hwmods = "mcasp5";
    			reg = <0x48470000 0x2000 0x4843a000 0x1000>;
    			reg-names = "mpu", "dat";
    			interrupts = <0x0 0x9b 0x4 0x0 0x9a 0x4>;
    			interrupt-names = "tx", "rx";
    			dmas = <0xc3 0x89 0x1 0xc3 0x88 0x1>;
    			dma-names = "tx", "rx";
    			clocks = <0x57 0x178 0x16 0x57 0x178 0x18>;
    			clock-names = "fck", "ahclkx";
    			status = "disabled";
    		};
    
    		mcasp@48474000 {
    			compatible = "ti,dra7-mcasp-audio";
    			ti,hwmods = "mcasp6";
    			reg = <0x48474000 0x2000 0x4844c000 0x1000>;
    			reg-names = "mpu", "dat";
    			interrupts = <0x0 0x9d 0x4 0x0 0x9c 0x4>;
    			interrupt-names = "tx", "rx";
    			dmas = <0xc3 0x8b 0x1 0xc3 0x8a 0x1>;
    			dma-names = "tx", "rx";
    			clocks = <0x57 0x204 0x16 0x57 0x204 0x18>;
    			clock-names = "fck", "ahclkx";
    			status = "disabled";
    		};
    
    		mcasp@48478000 {
    			compatible = "ti,dra7-mcasp-audio";
    			ti,hwmods = "mcasp7";
    			reg = <0x48478000 0x2000 0x48450000 0x1000>;
    			reg-names = "mpu", "dat";
    			interrupts = <0x0 0x9f 0x4 0x0 0x9e 0x4>;
    			interrupt-names = "tx", "rx";
    			dmas = <0xc3 0x8d 0x1 0xc3 0x8c 0x1>;
    			dma-names = "tx", "rx";
    			clocks = <0x57 0x208 0x16 0x57 0x208 0x18>;
    			clock-names = "fck", "ahclkx";
    			status = "disabled";
    		};
    
    		mcasp@4847c000 {
    			compatible = "ti,dra7-mcasp-audio";
    			ti,hwmods = "mcasp8";
    			reg = <0x4847c000 0x2000 0x48454000 0x1000>;
    			reg-names = "mpu", "dat";
    			interrupts = <0x0 0xa1 0x4 0x0 0xa0 0x4>;
    			interrupt-names = "tx", "rx";
    			dmas = <0xc3 0x8f 0x1 0xc3 0x8e 0x1>;
    			dma-names = "tx", "rx";
    			clocks = <0x57 0x190 0x16 0x57 0x190 0x18>;
    			clock-names = "fck", "ahclkx";
    			status = "disabled";
    		};
    
    		crossbar@4a002a48 {
    			compatible = "ti,irq-crossbar";
    			reg = <0x4a002a48 0x130>;
    			interrupt-controller;
    			interrupt-parent = <0x8>;
    			#interrupt-cells = <0x3>;
    			ti,max-irqs = <0xa0>;
    			ti,max-crossbar-sources = <0x190>;
    			ti,reg-size = <0x2>;
    			ti,irqs-reserved = <0x0 0x1 0x2 0x3 0x5 0x6 0x83 0x84>;
    			ti,irqs-skip = <0xa 0x85 0x8b 0x8c>;
    			ti,irqs-safe-map = <0x0>;
    			phandle = <0x1>;
    		};
    
    		ethernet@48484000 {
    			compatible = "ti,dra7-cpsw", "ti,cpsw";
    			ti,hwmods = "gmac";
    			clocks = <0xc8 0xb7 0xb0 0x19>;
    			clock-names = "fck", "cpts";
    			cpdma_channels = <0x8>;
    			ale_entries = <0x400>;
    			bd_ram_size = <0x2000>;
    			mac_control = <0x20>;
    			slaves = <0x2>;
    			active_slave = <0x0>;
    			cpts_clock_mult = <0x784cfe14>;
    			cpts_clock_shift = <0x1d>;
    			reg = <0x48484000 0x1000 0x48485200 0x2e00>;
    			#address-cells = <0x1>;
    			#size-cells = <0x1>;
    			ti,no-idle;
    			interrupts = <0x0 0x14e 0x4 0x0 0x14f 0x4 0x0 0x150 0x4 0x0 0x151 0x4>;
    			ranges;
    			syscon = <0x9>;
    			status = "okay";
    			dual_emac;
    
    			mdio@48485000 {
    				compatible = "ti,cpsw-mdio", "ti,davinci_mdio";
    				#address-cells = <0x1>;
    				#size-cells = <0x0>;
    				ti,hwmods = "davinci_mdio";
    				bus_freq = <0xf4240>;
    				reg = <0x48485000 0x100>;
    
    				ethernet-phy@1 {
    					reg = <0x1>;
    					phandle = <0xc9>;
    				};
    
    				ethernet-phy@2 {
    					reg = <0x2>;
    					status = "disabled";
    					max-speed = <0x64>;
    					phandle = <0xca>;
    				};
    			};
    
    			slave@48480200 {
    				mac-address = [00 00 00 00 00 00];
    				phy-handle = <0xc9>;
    				phy-mode = "rgmii";
    				dual_emac_res_vlan = <0x1>;
    			};
    
    			slave@48480300 {
    				mac-address = [00 00 00 00 00 00];
    				phy-handle = <0xca>;
    				phy-mode = "rgmii";
    				dual_emac_res_vlan = <0x2>;
    			};
    
    			cpsw-phy-sel@4a002554 {
    				compatible = "ti,dra7xx-cpsw-phy-sel";
    				reg = <0x4a002554 0x4>;
    				reg-names = "gmii-sel";
    			};
    		};
    
    		can@4ae3c000 {
    			compatible = "ti,dra7-d_can";
    			ti,hwmods = "dcan1";
    			reg = <0x4ae3c000 0x2000>;
    			syscon-raminit = <0x9 0x558 0x0>;
    			interrupts = <0x0 0xde 0x4>;
    			clocks = <0x8f 0x68 0x18>;
    			status = "disabled";
    		};
    
    		can@48480000 {
    			compatible = "ti,dra7-d_can";
    			ti,hwmods = "dcan2";
    			reg = <0x48480000 0x2000>;
    			syscon-raminit = <0x9 0x558 0x1>;
    			interrupts = <0x0 0xe1 0x4>;
    			clocks = <0x11>;
    			status = "disabled";
    		};
    
    		gpu@56000000 {
    			compatible = "ti,dra7-sgx544", "img,sgx544";
    			reg = <0x56000000 0x10000>;
    			reg-names = "gpu_ocp_base";
    			interrupts = <0x0 0x10 0x4>;
    			ti,hwmods = "gpu";
    			clocks = <0xa 0x53 0x54>;
    			clock-names = "iclk", "fclk1", "fclk2";
    			status = "disabled";
    		};
    
    		bb2d@59000000 {
    			compatible = "ti,dra7-bb2d";
    			reg = <0x59000000 0x700>;
    			interrupts = <0x0 0x78 0x4>;
    			ti,hwmods = "bb2d";
    			clocks = <0xcb 0x10 0x0>;
    			clock-names = "fck";
    			status = "okay";
    		};
    
    		dss@58000000 {
    			compatible = "ti,dra7-dss";
    			status = "ok";
    			ti,hwmods = "dss_core";
    			syscon-pll-ctrl = <0x9 0x538>;
    			#address-cells = <0x1>;
    			#size-cells = <0x1>;
    			ranges;
    			reg = <0x58000000 0x80 0x58004054 0x4 0x58004300 0x20 0x58009054 0x4 0x58009300 0x20>;
    			reg-names = "dss", "pll1_clkctrl", "pll1", "pll2_clkctrl", "pll2";
    			clocks = <0xcb 0x0 0x8 0xcb 0x0 0xc 0xcb 0x0 0xd>;
    			clock-names = "fck", "video1_clk", "video2_clk";
    			vdda_video-supply = <0xcc>;
    
    			dispc@58001000 {
    				compatible = "ti,dra7-dispc";
    				reg = <0x58001000 0x1000>;
    				interrupts = <0x0 0x14 0x4>;
    				ti,hwmods = "dss_dispc";
    				clocks = <0xcb 0x0 0x8>;
    				clock-names = "fck";
    				syscon-pol = <0x9 0x534>;
    			};
    
    			encoder@58060000 {
    				compatible = "ti,dra7-hdmi";
    				reg = <0x58040000 0x200 0x58040200 0x80 0x58040300 0x80 0x58060000 0x19000>;
    				reg-names = "wp", "pll", "phy", "core";
    				interrupts = <0x0 0x60 0x4>;
    				status = "ok";
    				ti,hwmods = "dss_hdmi";
    				clocks = <0xcb 0x0 0x9 0xcb 0x0 0xa>;
    				clock-names = "fck", "sys_clk";
    				dmas = <0x8d 0x4c>;
    				dma-names = "audio_tx";
    				vdda-supply = <0xcd>;
    
    				port {
    
    					endpoint {
    						remote-endpoint = <0xce>;
    						phandle = <0xe5>;
    					};
    				};
    			};
    		};
    
    		epwmss@4843e000 {
    			compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
    			reg = <0x4843e000 0x30>;
    			ti,hwmods = "epwmss0";
    			#address-cells = <0x1>;
    			#size-cells = <0x1>;
    			status = "disabled";
    			ranges;
    
    			pwm@4843e200 {
    				compatible = "ti,dra746-ehrpwm", "ti,am3352-ehrpwm";
    				#pwm-cells = <0x3>;
    				reg = <0x4843e200 0x80>;
    				clocks = <0xcf 0xb>;
    				clock-names = "tbclk", "fck";
    				status = "disabled";
    			};
    
    			ecap@4843e100 {
    				compatible = "ti,dra746-ecap", "ti,am3352-ecap";
    				#pwm-cells = <0x3>;
    				reg = <0x4843e100 0x80>;
    				clocks = <0xb>;
    				clock-names = "fck";
    				status = "disabled";
    			};
    		};
    
    		epwmss@48440000 {
    			compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
    			reg = <0x48440000 0x30>;
    			ti,hwmods = "epwmss1";
    			#address-cells = <0x1>;
    			#size-cells = <0x1>;
    			status = "disabled";
    			ranges;
    
    			pwm@48440200 {
    				compatible = "ti,dra746-ehrpwm", "ti,am3352-ehrpwm";
    				#pwm-cells = <0x3>;
    				reg = <0x48440200 0x80>;
    				clocks = <0xd0 0xb>;
    				clock-names = "tbclk", "fck";
    				status = "disabled";
    			};
    
    			ecap@48440100 {
    				compatible = "ti,dra746-ecap", "ti,am3352-ecap";
    				#pwm-cells = <0x3>;
    				reg = <0x48440100 0x80>;
    				clocks = <0xb>;
    				clock-names = "fck";
    				status = "disabled";
    			};
    		};
    
    		epwmss@48442000 {
    			compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
    			reg = <0x48442000 0x30>;
    			ti,hwmods = "epwmss2";
    			#address-cells = <0x1>;
    			#size-cells = <0x1>;
    			status = "disabled";
    			ranges;
    
    			pwm@48442200 {
    				compatible = "ti,dra746-ehrpwm", "ti,am3352-ehrpwm";
    				#pwm-cells = <0x3>;
    				reg = <0x48442200 0x80>;
    				clocks = <0xd1 0xb>;
    				clock-names = "tbclk", "fck";
    				status = "disabled";
    			};
    
    			ecap@48442100 {
    				compatible = "ti,dra746-ecap", "ti,am3352-ecap";
    				#pwm-cells = <0x3>;
    				reg = <0x48442100 0x80>;
    				clocks = <0xb>;
    				clock-names = "fck";
    				status = "disabled";
    			};
    		};
    
    		aes@4b500000 {
    			compatible = "ti,omap4-aes";
    			ti,hwmods = "aes1";
    			reg = <0x4b500000 0xa0>;
    			interrupts = <0x0 0x50 0x4>;
    			dmas = <0xc3 0x6f 0x0 0xc3 0x6e 0x0>;
    			dma-names = "tx", "rx";
    			clocks = <0xa>;
    			clock-names = "fck";
    		};
    
    		aes@4b700000 {
    			compatible = "ti,omap4-aes";
    			ti,hwmods = "aes2";
    			reg = <0x4b700000 0xa0>;
    			interrupts = <0x0 0x3b 0x4>;
    			dmas = <0xc3 0x72 0x0 0xc3 0x71 0x0>;
    			dma-names = "tx", "rx";
    			clocks = <0xa>;
    			clock-names = "fck";
    		};
    
    		des@480a5000 {
    			compatible = "ti,omap4-des";
    			ti,hwmods = "des";
    			reg = <0x480a5000 0xa0>;
    			interrupts = <0x0 0x4d 0x4>;
    			dmas = <0x8d 0x75 0x8d 0x74>;
    			dma-names = "tx", "rx";
    			clocks = <0xa>;
    			clock-names = "fck";
    		};
    
    		sham@53100000 {
    			compatible = "ti,omap5-sham";
    			ti,hwmods = "sham";
    			reg = <0x4b101000 0x300>;
    			interrupts = <0x0 0x2e 0x4>;
    			dmas = <0xc3 0x77 0x0>;
    			dma-names = "rx";
    			clocks = <0xa>;
    			clock-names = "fck";
    		};
    
    		rng@48090000 {
    			compatible = "ti,omap4-rng";
    			ti,hwmods = "rng";
    			reg = <0x48090000 0x2000>;
    			interrupts = <0x0 0x2f 0x4>;
    			clocks = <0xa>;
    			clock-names = "fck";
    		};
    
    		opp-supply@4a003b20 {
    			compatible = "ti,omap5-opp-supply";
    			reg = <0x4a003b20 0xc>;
    			ti,efuse-settings = <0x102ca0 0x0 0x11b340 0x4 0x127690 0x8>;
    			ti,absolute-max-voltage-uv = <0x16e360>;
    		};
    
    		vpe {
    			compatible = "ti,vpe";
    			ti,hwmods = "vpe";
    			clocks = <0x56>;
    			clock-names = "fck";
    			reg = <0x489d0000 0x120 0x489d0700 0x80 0x489d5700 0x18 0x489dd000 0x400>;
    			reg-names = "vpe_top", "sc", "csc", "vpdma";
    			interrupts = <0x0 0x162 0x4>;
    			#address-cells = <0x1>;
    			#size-cells = <0x0>;
    		};
    
    		vip@0x48970000 {
    			compatible = "ti,vip1";
    			reg = <0x48970000 0x114 0x48975500 0xd8 0x48975700 0x18 0x48975800 0x80 0x48975a00 0xd8 0x48975c00 0x18 0x48975d00 0x80 0x4897d000 0x400>;
    			reg-names = "vip", "parser0", "csc0", "sc0", "parser1", "csc1", "sc1", "vpdma";
    			ti,hwmods = "vip1";
    			interrupts = <0x0 0x15f 0x4 0x0 0x188 0x4>;
    			syscon-pol = <0x9 0x534>;
    			#address-cells = <0x1>;
    			#size-cells = <0x0>;
    			status = "disabled";
    
    			ports {
    				#address-cells = <0x1>;
    				#size-cells = <0x0>;
    
    				port@0 {
    					reg = <0x0>;
    				};
    
    				port@1 {
    					reg = <0x1>;
    				};
    
    				port@2 {
    					reg = <0x2>;
    				};
    
    				port@3 {
    					reg = <0x3>;
    				};
    			};
    		};
    
    		dsp_system@41500000 {
    			compatible = "syscon";
    			reg = <0x41500000 0x100>;
    			phandle = <0xd2>;
    		};
    
    		omap_dwc3_4@48940000 {
    			compatible = "ti,dwc3";
    			ti,hwmods = "usb_otg_ss4";
    			reg = <0x48940000 0x10000>;
    			interrupts = <0x0 0x15a 0x4>;
    			#address-cells = <0x1>;
    			#size-cells = <0x1>;
    			utmi-mode = <0x2>;
    			ranges;
    			status = "disabled";
    
    			usb@48950000 {
    				compatible = "snps,dwc3";
    				reg = <0x48950000 0x17000>;
    				interrupts = <0x0 0x159 0x4 0x0 0x159 0x4 0x0 0x15a 0x4>;
    				interrupt-names = "peripheral", "host", "otg";
    				maximum-speed = "high-speed";
    				dr_mode = "otg";
    			};
    		};
    
    		mmu@41501000 {
    			compatible = "ti,dra7-dsp-iommu";
    			reg = <0x41501000 0x100>;
    			interrupts = <0x0 0x92 0x4>;
    			ti,hwmods = "mmu0_dsp2";
    			#iommu-cells = <0x0>;
    			ti,syscon-mmuconfig = <0xd2 0x0>;
    			phandle = <0xd3>;
    		};
    
    		mmu@41502000 {
    			compatible = "ti,dra7-dsp-iommu";
    			reg = <0x41502000 0x100>;
    			interrupts = <0x0 0x93 0x4>;
    			ti,hwmods = "mmu1_dsp2";
    			#iommu-cells = <0x0>;
    			ti,syscon-mmuconfig = <0xd2 0x1>;
    			phandle = <0xd4>;
    		};
    
    		dsp@41000000 {
    			compatible = "ti,dra7-dsp";
    			reg = <0x41000000 0x48000 0x41600000 0x8000 0x41700000 0x8000>;
    			reg-names = "l2ram", "l1pram", "l1dram";
    			ti,hwmods = "dsp2";
    			syscon-bootreg = <0x9 0x560>;
    			iommus = <0xd3 0xd4>;
    			ti,rproc-standby-info = <0x4a005620>;
    			status = "okay";
    			mboxes = <0x9b 0xd5>;
    			timers = <0xd6>;
    			watchdog-timers = <0xd7>;
    			memory-region = <0xd8>;
    		};
    
    		vip@0x48990000 {
    			compatible = "ti,vip2";
    			reg = <0x48990000 0x114 0x48995500 0xd8 0x48995700 0x18 0x48995800 0x80 0x48995a00 0xd8 0x48995c00 0x18 0x48995d00 0x80 0x4899d000 0x400>;
    			reg-names = "vip", "parser0", "csc0", "sc0", "parser1", "csc1", "sc1", "vpdma";
    			ti,hwmods = "vip2";
    			interrupts = <0x0 0x160 0x4 0x0 0x189 0x4>;
    			syscon-pol = <0x9 0x534>;
    			#address-cells = <0x1>;
    			#size-cells = <0x0>;
    			status = "disabled";
    
    			ports {
    				#address-cells = <0x1>;
    				#size-cells = <0x0>;
    
    				port@0 {
    					reg = <0x0>;
    				};
    
    				port@1 {
    					reg = <0x1>;
    				};
    
    				port@2 {
    					reg = <0x2>;
    				};
    
    				port@3 {
    					reg = <0x3>;
    				};
    			};
    		};
    
    		vip@0x489b0000 {
    			compatible = "ti,vip3";
    			reg = <0x489b0000 0x114 0x489b5500 0xd8 0x489b5700 0x18 0x489b5800 0x80 0x489b5a00 0xd8 0x489b5c00 0x18 0x489b5d00 0x80 0x489bd000 0x400>;
    			reg-names = "vip", "parser0", "csc0", "sc0", "parser1", "csc1", "sc1", "vpdma";
    			ti,hwmods = "vip3";
    			interrupts = <0x0 0x161 0x4 0x0 0x18a 0x4>;
    			syscon-pol = <0x9 0x534>;
    			#address-cells = <0x1>;
    			#size-cells = <0x0>;
    			status = "disabled";
    
    			ports {
    				#address-cells = <0x1>;
    				#size-cells = <0x0>;
    
    				port@0 {
    					reg = <0x0>;
    				};
    
    				port@1 {
    					reg = <0x1>;
    				};
    			};
    		};
    	};
    
    	thermal-zones {
    
    		cpu_thermal {
    			polling-delay-passive = <0xfa>;
    			polling-delay = <0x1f4>;
    			thermal-sensors = <0xd9 0x0>;
    			coefficients = <0x0 0x7d0>;
    
    			trips {
    
    				cpu_alert {
    					temperature = <0x13880>;
    					hysteresis = <0x7d0>;
    					type = "passive";
    					phandle = <0xda>;
    				};
    
    				cpu_crit {
    					temperature = <0x15f90>;
    					hysteresis = <0x7d0>;
    					type = "critical";
    				};
    
    				cpu_alert1 {
    					temperature = <0xc350>;
    					hysteresis = <0x7d0>;
    					type = "active";
    					phandle = <0xdc>;
    				};
    			};
    
    			cooling-maps {
    
    				map0 {
    					trip = <0xda>;
    					cooling-device = <0xdb 0xffffffff 0xffffffff>;
    				};
    
    				map1 {
    					trip = <0xdc>;
    					cooling-device = <0xdd 0xffffffff 0xffffffff>;
    				};
    			};
    		};
    
    		gpu_thermal {
    			polling-delay-passive = <0xfa>;
    			polling-delay = <0x1f4>;
    			thermal-sensors = <0xd9 0x1>;
    			coefficients = <0x0 0x7d0>;
    
    			trips {
    
    				gpu_crit {
    					temperature = <0x15f90>;
    					hysteresis = <0x7d0>;
    					type = "critical";
    				};
    			};
    		};
    
    		core_thermal {
    			polling-delay-passive = <0xfa>;
    			polling-delay = <0x1f4>;
    			thermal-sensors = <0xd9 0x2>;
    			coefficients = <0x0 0x7d0>;
    
    			trips {
    
    				core_crit {
    					temperature = <0x15f90>;
    					hysteresis = <0x7d0>;
    					type = "critical";
    				};
    			};
    		};
    
    		dspeve_thermal {
    			polling-delay-passive = <0xfa>;
    			polling-delay = <0x1f4>;
    			thermal-sensors = <0xd9 0x3>;
    			coefficients = <0x0 0x7d0>;
    
    			trips {
    
    				dspeve_crit {
    					temperature = <0x15f90>;
    					hysteresis = <0x7d0>;
    					type = "critical";
    				};
    			};
    		};
    
    		iva_thermal {
    			polling-delay-passive = <0xfa>;
    			polling-delay = <0x1f4>;
    			thermal-sensors = <0xd9 0x4>;
    			coefficients = <0x0 0x7d0>;
    
    			trips {
    
    				iva_crit {
    					temperature = <0x15f90>;
    					hysteresis = <0x7d0>;
    					type = "critical";
    				};
    			};
    		};
    
    		board_thermal {
    			polling-delay-passive = <0x4e2>;
    			polling-delay = <0x5dc>;
    			thermal-sensors = <0xde 0x0>;
    
    			trips {
    
    				board_alert {
    					temperature = <0x9c40>;
    					hysteresis = <0x7d0>;
    					type = "active";
    					phandle = <0xdf>;
    				};
    
    				board_crit {
    					temperature = <0x19a28>;
    					hysteresis = <0x0>;
    					type = "critical";
    				};
    			};
    
    			cooling-maps {
    
    				map0 {
    					trip = <0xdf>;
    					cooling-device = <0xdd 0xffffffff 0xffffffff>;
    				};
    			};
    		};
    	};
    
    	pmu {
    		compatible = "arm,cortex-a15-pmu";
    		interrupt-parent = <0x8>;
    		interrupts = <0x0 0x83 0x4 0x0 0x84 0x4>;
    	};
    
    	memory@0 {
    		device_type = "memory";
    		reg = <0x0 0x80000000 0x0 0x80000000>;
    	};
    
    	reserved-memory {
    		#address-cells = <0x2>;
    		#size-cells = <0x2>;
    		ranges;
    
    		ipu2-memory@95800000 {
    			compatible = "shared-dma-pool";
    			reg = <0x0 0x95800000 0x0 0x3800000>;
    			reusable;
    			status = "okay";
    			phandle = <0xa0>;
    		};
    
    		dsp1-memory@99000000 {
    			compatible = "shared-dma-pool";
    			reg = <0x0 0x99000000 0x0 0x4000000>;
    			reusable;
    			status = "okay";
    			phandle = <0xa6>;
    		};
    
    		ipu1-memory@9d000000 {
    			compatible = "shared-dma-pool";
    			reg = <0x0 0x9d000000 0x0 0x2000000>;
    			reusable;
    			status = "okay";
    			phandle = <0x99>;
    		};
    
    		dsp2-memory@9f000000 {
    			compatible = "shared-dma-pool";
    			reg = <0x0 0x9f000000 0x0 0x800000>;
    			reusable;
    			status = "okay";
    			phandle = <0xd8>;
    		};
    
    		cmem_block_mem@a0000000 {
    			reg = <0x0 0xa0000000 0x0 0xc000000>;
    			no-map;
    			status = "okay";
    			phandle = <0xeb>;
    		};
    
    		cmem_block_mem@40500000 {
    			reg = <0x0 0x40500000 0x0 0x100000>;
    			no-map;
    			status = "okay";
    			phandle = <0xec>;
    		};
    	};
    
    	fixedregulator-main_12v0 {
    		compatible = "regulator-fixed";
    		regulator-name = "main_12v0";
    		regulator-min-microvolt = <0xb71b00>;
    		regulator-max-microvolt = <0xb71b00>;
    		regulator-always-on;
    		regulator-boot-on;
    		phandle = <0xe0>;
    	};
    
    	fixedregulator-evm_5v0 {
    		compatible = "regulator-fixed";
    		regulator-name = "evm_5v0";
    		regulator-min-microvolt = <0x4c4b40>;
    		regulator-max-microvolt = <0x4c4b40>;
    		vin-supply = <0xe0>;
    		regulator-always-on;
    		regulator-boot-on;
    	};
    
    	fixedregulator-vdd_3v3 {
    		compatible = "regulator-fixed";
    		regulator-name = "vdd_3v3";
    		vin-supply = <0xe1>;
    		regulator-min-microvolt = <0x325aa0>;
    		regulator-max-microvolt = <0x325aa0>;
    		phandle = <0xab>;
    	};
    
    	fixedregulator-aic_dvdd {
    		compatible = "regulator-fixed";
    		regulator-name = "aic_dvdd_fixed";
    		vin-supply = <0xab>;
    		regulator-min-microvolt = <0x1b7740>;
    		regulator-max-microvolt = <0x1b7740>;
    		phandle = <0xac>;
    	};
    
    	fixedregulator-vtt {
    		compatible = "regulator-fixed";
    		regulator-name = "vtt_fixed";
    		vin-supply = <0xe2>;
    		regulator-min-microvolt = <0x325aa0>;
    		regulator-max-microvolt = <0x325aa0>;
    		regulator-always-on;
    		regulator-boot-on;
    		enable-active-high;
    		gpio = <0xaa 0xb 0x0>;
    	};
    
    	leds {
    		compatible = "gpio-leds";
    
    		led0 {
    			label = "beagle-x15:usr0";
    			gpios = <0xaa 0x9 0x0>;
    			linux,default-trigger = "heartbeat";
    			default-state = "off";
    		};
    
    		led1 {
    			label = "beagle-x15:usr1";
    			gpios = <0xaa 0x8 0x0>;
    			linux,default-trigger = "cpu0";
    			default-state = "off";
    		};
    
    		led2 {
    			label = "beagle-x15:usr2";
    			gpios = <0xaa 0xe 0x0>;
    			linux,default-trigger = "mmc0";
    			default-state = "off";
    		};
    
    		led3 {
    			label = "beagle-x15:usr3";
    			gpios = <0xaa 0xf 0x0>;
    			linux,default-trigger = "disk-activity";
    			default-state = "off";
    		};
    	};
    
    	gpio_fan {
    		compatible = "gpio-fan";
    		gpios = <0xe3 0x2 0x0>;
    		gpio-fan,speed-map = <0x0 0x0 0x32c8 0x1>;
    		#cooling-cells = <0x2>;
    		phandle = <0xdd>;
    	};
    
    	connector {
    		compatible = "hdmi-connector";
    		label = "hdmi";
    		type = [61 00];
    
    		port {
    
    			endpoint {
    				remote-endpoint = <0xe4>;
    				phandle = <0xe6>;
    			};
    		};
    	};
    
    	encoder {
    		compatible = "ti,tpd12s015";
    		status = "disabled";
    
    		ports {
    			#address-cells = <0x1>;
    			#size-cells = <0x0>;
    
    			port@0 {
    				reg = <0x0>;
    
    				endpoint {
    					remote-endpoint = <0xe5>;
    					phandle = <0xce>;
    				};
    			};
    
    			port@1 {
    				reg = <0x1>;
    
    				endpoint {
    					remote-endpoint = <0xe6>;
    					phandle = <0xe4>;
    				};
    			};
    		};
    	};
    
    	sound0 {
    		compatible = "simple-audio-card";
    		simple-audio-card,name = "BeagleBoard-X15";
    		simple-audio-card,widgets = "Line", "Line Out", "Line", "Line In";
    		simple-audio-card,routing = "Line Out", "LLOUT", "Line Out", "RLOUT", "MIC2L", "Line In", "MIC2R", "Line In";
    		simple-audio-card,format = "dsp_b";
    		simple-audio-card,bitclock-master = <0xe7>;
    		simple-audio-card,frame-master = <0xe7>;
    		simple-audio-card,bitclock-inversion;
    
    		simple-audio-card,cpu {
    			sound-dai = <0xe8>;
    		};
    
    		simple-audio-card,codec {
    			sound-dai = <0xe9>;
    			clocks = <0xea>;
    			phandle = <0xe7>;
    		};
    	};
    
    	cmem {
    		compatible = "ti,cmem";
    		#address-cells = <0x1>;
    		#size-cells = <0x0>;
    		#pool-size-cells = <0x2>;
    		status = "okay";
    
    		cmem_block@0 {
    			reg = <0x0>;
    			memory-region = <0xeb>;
    			cmem-buf-pools = <0x1 0x0 0xc000000>;
    		};
    
    		cmem_block@1 {
    			reg = <0x1>;
    			memory-region = <0xec>;
    		};
    	};
    };

     

     

     

     

     

     

  • Please, see this thread.

  • Hello Kemal thank you for your post but,

    Can you give pls some instructions to solve the problem?

    I don´t understand why I should now look to your proposed thread. 

    What does the GPIO3 block have to do with my GPU not present in the AM5726?

    Best Regards

  • Can you remove the GPU node from dra7.dtsi and the SGX modules from the rootfs and retry?

  • Thank you Kemal,

    I have in my DTS deleted the node "gpu" with:

    / {

         ocp {
            ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
            //ti,hwmods = "";
            /delete-node/ gpu@56000000;
        };
    };

     

    In the back converted DTS from DTB there is now no entry of gpu@56000000

     

    I have found one thing with name like sgx on mmc.rootfs partition and I have renamed with mv ./opt/ltp/runtest/ddt/sgx ./opt/ltp/runtest/ddt/sgx~~~~~~


    I have copied the changed DTB to the boot boot partition and start it with:

    setenv bootargs console=ttyS2,115200 debug verbose panic=0 earlyprintk loglevel=3 mem=0x40000000 loglevel=7
    load mmc 0:1 0x88000000 sec4.dtb
    load mmc 0:1 0x82000000 zImage
    bootz 0x82000000 - 0x88000000

     

    The messages there are now:

    Loading Environment from FAT... *** Warning - bad CRC, using default environment

    Loading Environment from MMC... MMC Device 1 not found
    *** Warning - No MMC card found, using default environment

    invalid mmc device
    Net:   No ethernet found.
    Hit any key to stop autoboot:  0
    => setenv bootargs console=ttyS2,115200 debug verbose panic=0 earlyprintk loglevel=3 mem=0x40000000 loglevel=7
    => load mmc 0:1 0x88000000 sec4.dtb
    90228 bytes read in 6 ms (14.3 MiB/s)
    => load mmc 0:1 0x82000000 zImage
    4223488 bytes read in 188 ms (21.4 MiB/s)
    => bootz 0x82000000 - 0x88000000
    ## Flattened Device Tree blob at 88000000
       Booting using the fdt blob at 0x88000000
       Loading Device Tree to 8ffe6000, end 8ffff073 ... OK

    Starting kernel ...

    Uncompressing Linux... done, booting the kernel.
    [    0.000000] Booting Linux on physical CPU 0x0
    [    0.000000] Linux version 4.19.38-rt19 (rene@ubuntu) (gcc version 8.3.0 (GNU Toolchain for the A-profile Architecture 8.3-2019.03 (arm-rel-8.36))9
    [    0.000000] CPU: ARMv7 Processor [412fc0f2] revision 2 (ARMv7), cr=30c5387d
    [    0.000000] CPU: div instructions available: patching division code
    [    0.000000] CPU: PIPT / VIPT nonaliasing data cache, PIPT instruction cache
    [    0.000000] OF: fdt: Machine model: TI AM5728 BeagleBoard-X15
    [    0.000000] OF: fdt: Ignoring memory range 0x40000000 - 0x80000000
    [    0.000000] bootconsole [earlycon0] enabled
    [    0.000000] Memory policy: Data cache writealloc
    [    0.000000] efi: Getting EFI parameters from FDT:
    [    0.000000] efi: UEFI not found.
    [    0.000000] Reserved memory: created CMA memory pool at 0x0000000095800000, size 56 MiB
    [    0.000000] OF: reserved mem: initialized node ipu2-memory@95800000, compatible id shared-dma-pool
    [    0.000000] Reserved memory: created CMA memory pool at 0x0000000099000000, size 64 MiB
    [    0.000000] OF: reserved mem: initialized node dsp1-memory@99000000, compatible id shared-dma-pool
    [    0.000000] Reserved memory: created CMA memory pool at 0x000000009d000000, size 32 MiB
    [    0.000000] OF: reserved mem: initialized node ipu1-memory@9d000000, compatible id shared-dma-pool
    [    0.000000] Reserved memory: created CMA memory pool at 0x000000009f000000, size 8 MiB
    [    0.000000] OF: reserved mem: initialized node dsp2-memory@9f000000, compatible id shared-dma-pool
    [    0.000000] cma: Reserved 24 MiB at 0x00000000be400000
    [    0.000000] OMAP4: Map 0x00000000bfd00000 to (ptrval) for dram barrier
    [    0.000000] DRA752 ES2.0
    [    0.000000] random: get_random_bytes called from start_kernel+0xb0/0x480 with crng_init=0
    [    0.000000] percpu: Embedded 15 pages/cpu s32480 r8192 d20768 u61440
    [    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 210496
    [    0.000000] Kernel command line: console=ttyS2,115200 debug verbose panic=0 earlyprintk loglevel=3 mem=0x40000000 loglevel=7
    [    0.000000] Dentry cache hash table entries: 131072 (order: 8, 1048576 bytes)
    [    0.000000] Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
    [    0.000000] Memory: 635880K/848896K available (8192K kernel code, 356K rwdata, 2656K rodata, 2048K init, 275K bss, 24600K reserved, 188416K cma-r)
    [    0.000000] Virtual kernel memory layout:
    [    0.000000]     vector  : 0xffff0000 - 0xffff1000   (   4 kB)
    [    0.000000]     fixmap  : 0xffc00000 - 0xfff00000   (3072 kB)
    [    0.000000]     vmalloc : 0xf0800000 - 0xff800000   ( 240 MB)
    [    0.000000]     lowmem  : 0xc0000000 - 0xf0000000   ( 768 MB)
    [    0.000000]     pkmap   : 0xbfe00000 - 0xc0000000   (   2 MB)
    [    0.000000]     modules : 0xbf000000 - 0xbfe00000   (  14 MB)
    [    0.000000]       .text : 0x(ptrval) - 0x(ptrval)   (10208 kB)
    [    0.000000]       .init : 0x(ptrval) - 0x(ptrval)   (2048 kB)
    [    0.000000]       .data : 0x(ptrval) - 0x(ptrval)   ( 357 kB)
    [    0.000000]        .bss : 0x(ptrval) - 0x(ptrval)   ( 276 kB)
    [    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1
    [    0.000000] rcu: Preemptible hierarchical RCU implementation.
    [    0.000000] rcu:     RCU priority boosting: priority 1 delay 500 ms.
    [    0.000000]  No expedited grace period (rcu_normal_after_boot).
    [    0.000000]  Tasks RCU enabled.
    [    0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
    [    0.000000] GIC: Using split EOI/Deactivate mode
    [    0.000000] OMAP clockevent source: timer1 at 32786 Hz
    [    0.000000] arch_timer: cp15 timer(s) running at 6.14MHz (phys).
    [    0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x16af5adb9, max_idle_ns: 440795202250 ns
    [    0.000005] sched_clock: 56 bits at 6MHz, resolution 162ns, wraps every 4398046511023ns
    [    0.000012] Switching to timer-based delay loop, resolution 162ns
    [    0.000284] clocksource: 32k_counter: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 58327039986419 ns
    [    0.000287] OMAP clocksource: 32k_counter at 32768 Hz
    [    0.000721] Console: colour dummy device 80x30
    [    0.323355] Calibrating delay loop (skipped), value calculated using timer frequency.. 12.29 BogoMIPS (lpj=61475)
    [    0.323364] pid_max: default: 32768 minimum: 301
    [    0.323503] Mount-cache hash table entries: 2048 (order: 1, 8192 bytes)
    [    0.323513] Mountpoint-cache hash table entries: 2048 (order: 1, 8192 bytes)
    [    0.324243] CPU: Testing write buffer coherency: ok
    [    0.324273] CPU0: Spectre v2: using ICIALLU workaround
    [    0.324522] CPU0: update cpu_capacity 1024
    [    0.368214] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
    [    0.430227] Setting up static identity map for 0x80200000 - 0x80200060
    [    0.450201] rcu: Hierarchical SRCU implementation.
    [    0.510714] EFI services will not be available.
    [    0.540353] smp: Bringing up secondary CPUs ...
    [    0.660781] CPU1: update cpu_capacity 1024
    [    0.660786] CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
    [    0.660790] CPU1: Spectre v2: using ICIALLU workaround
    [    0.660925] smp: Brought up 1 node, 2 CPUs
    [    0.680372] SMP: Total of 2 processors activated (24.59 BogoMIPS).
    [    0.686716] CPU: All CPU(s) started in HYP mode.
    [    0.691485] CPU: Virtualization extensions available.
    [    0.697297] devtmpfs: initialized
    [    0.729488] VFP support v0.3: implementor 41 architecture 4 part 30 variant f rev 0
    [    0.737686] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
    [    0.747776] futex hash table entries: 512 (order: 3, 32768 bytes)
    [    0.757243] pinctrl core: initialized pinctrl subsystem
    [    0.763457] DMI not present or invalid.
    [    0.767857] NET: Registered protocol family 16
    [    0.775170] DMA: preallocated 256 KiB pool for atomic coherent allocations
    [    0.783146] omap_hwmod: l3_main_2 using broken dt data from ocp
    [    0.821446] omap_hwmod: gpu: no dt node
    [    0.825382] ------------[ cut here ]------------
    [    0.830126] WARNING: CPU: 0 PID: 1 at arch/arm/mach-omap2/omap_hwmod.c:2409 _init.constprop.22+0x1b0/0x4dc
    [    0.840029] omap_hwmod: gpu: doesn't have mpu register target base
    [    0.846365] Modules linked in:
    [    0.849506] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.19.38-rt19 #15
    [    0.849509] Hardware name: Generic DRA74X (Flattened Device Tree)
    [    0.849511] Backtrace:
    [    0.849525] [<c020c744>] (dump_backtrace) from [<c020ca7c>] (show_stack+0x18/0x1c)
    [    0.849532]  r7:c0bb73f4 r6:60000013 r5:00000000 r4:c1050a24
    [    0.849544] [<c020ca64>] (show_stack) from [<c09a5094>] (dump_stack+0x90/0xa4)
    [    0.849552] [<c09a5004>] (dump_stack) from [<c022d1b4>] (__warn+0xdc/0xf8)
    [    0.849556]  r7:c0bb73f4 r6:00000009 r5:00000000 r4:ef0a1ddc
    [    0.849568] [<c022d0d8>] (__warn) from [<c022cda4>] (warn_slowpath_fmt+0x50/0x6c)
    [    0.849574]  r9:c0e49824 r8:00000000 r7:c10142bc r6:00000000 r5:c0bb79dc r4:c1007488
    [    0.849583] [<c022cd58>] (warn_slowpath_fmt) from [<c0e0cae8>] (_init.constprop.22+0x1b0/0x4dc)
    [    0.849587]  r3:c0bb9afc r2:c0bb79dc
    [    0.849590]  r5:00000000 r4:c1014284
    [    0.849597] [<c0e0c938>] (_init.constprop.22) from [<c0e0cf44>] (__omap_hwmod_setup_all+0x48/0x134)
    [    0.849603]  r10:c0e5935c r9:c0e49824 r8:00000000 r7:c0e0cefc r6:ffffe000 r5:c100c768
    [    0.849606]  r4:c1014284
    [    0.849614] [<c0e0cefc>] (__omap_hwmod_setup_all) from [<c02023fc>] (do_one_initcall+0x84/0x1b0)
    [    0.849617]  r5:c1007488 r4:c10591c0
    [    0.849626] [<c0202378>] (do_one_initcall) from [<c0e0104c>] (kernel_init_freeable+0x218/0x2ac)
    [    0.849631]  r8:c0e49844 r7:c0e004f0 r6:c10591c0 r5:c10591c0 r4:00000003
    [    0.849641] [<c0e00e34>] (kernel_init_freeable) from [<c09b96d0>] (kernel_init+0x10/0x118)
    [    0.849646]  r10:00000000 r9:00000000 r8:00000000 r7:00000000 r6:00000000 r5:c09b96c0
    [    0.849649]  r4:00000000
    [    0.849656] [<c09b96c0>] (kernel_init) from [<c02010e0>] (ret_from_fork+0x14/0x34)
    [    0.849659] Exception stack(0xef0a1fb0 to 0xef0a1ff8)
    [    0.849664] 1fa0:                                     00000000 00000000 00000000 00000000
    [    0.849668] 1fc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
    [    0.849673] 1fe0: 00000000 00000000 00000000 00000000 00000013 00000000
    [    0.849676]  r5:c09b96c0 r4:00000000
    [    0.849679] ---[ end trace 0000000000000001 ]---
    [    1.203225] Unhandled fault: asynchronous external abort (0x1211) at 0x00000000
    [    1.203229] pgd = (ptrval)
    [    1.203232] [00000000] *pgd=80000080004003, *pmd=00000000
    [    1.203243] Internal error: : 1211 [#1] PREEMPT SMP ARM
    [    1.203246] Modules linked in:
    [    1.203253] CPU: 0 PID: 1 Comm: swapper/0 Tainted: G        W         4.19.38-rt19 #15
    [    1.203256] Hardware name: Generic DRA74X (Flattened Device Tree)
    [    1.203264] PC is at _enable_sysc+0x5c/0x25c
    [    1.203269] LR is at _enable_sysc+0x48/0x25c
    [    1.203273] pc : [<c021d8e8>]    lr : [<c021d8d4>]    psr: 40000013
    [    1.203276] sp : ef0a1e38  ip : ef0a1e38  fp : ef0a1e64
    [    1.203279] r10: c0e5935c  r9 : c0e49824  r8 : 00000000
    [    1.203282] r7 : c1012940  r6 : 00000000  r5 : c1007488  r4 : c1012428
    [    1.203285] r3 : c10124ac  r2 : c10124cc  r1 : 00000078  r0 : c1012428
    [    1.203290] Flags: nZcv  IRQs on  FIQs on  Mode SVC_32  ISA ARM  Segment user
    [    1.203294] Control: 30c5387d  Table: 80003000  DAC: fffffffd
    [    1.203297] Process swapper/0 (pid: 1, stack limit = 0x(ptrval))
    [    1.203301] Stack: (0xef0a1e38 to 0xef0a2000)
    [    1.203305] 1e20:                                                       c0224e70 c09be858
    [    1.203310] 1e40: ef0a1e64 8f3d4d61 c1012428 c1059810 00000000 c1012940 ef0a1e8c ef0a1e68
    [    1.203315] 1e60: c021dc40 c021d898 c1012428 c100ffb0 c1012428 c101244c c1007488 c1012460
    [    1.203320] 1e80: ef0a1ebc ef0a1e90 c021e164 c021daf4 ef0a1ebc ef0a1ea0 00000008 8f3d4d61
    [    1.203325] 1ea0: c1012428 c100c768 ffffe000 c0e0cefc ef0a1ed4 ef0a1ec0 c0e0d01c c021dfb0
    [    1.203330] 1ec0: c10591c0 c1007488 ef0a1f4c ef0a1ed8 c02023fc c0e0cf08 000004f0 c0bbc598
    [    1.203335] 1ee0: c0bbc578 c0bbc500 c0bc81a0 c1007488 00000000 c0bbc550 00000002 00000002
    [    1.203340] 1f00: 00000000 c0bb1e44 c0e004f0 c0c966e0 c1018b60 ef6646d1 ef6646da 8f3d4d61
    [    1.203345] 1f20: c02803c0 8f3d4d61 c10591c0 00000003 c10591c0 c10591c0 c0e004f0 c0e49844
    [    1.203350] 1f40: ef0a1f94 ef0a1f50 c0e0104c c0202384 00000002 00000002 00000000 c0e004f0
    [    1.203355] 1f60: c0c966e0 000000d2 c09be8ac 00000000 c09b96c0 00000000 00000000 00000000
    [    1.203359] 1f80: 00000000 00000000 ef0a1fac ef0a1f98 c09b96d0 c0e00e40 00000000 c09b96c0
    [    1.203364] 1fa0: 00000000 ef0a1fb0 c02010e0 c09b96cc 00000000 00000000 00000000 00000000
    [    1.203368] 1fc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
    [    1.203373] 1fe0: 00000000 00000000 00000000 00000000 00000013 00000000 00000000 00000000
    [    1.203374] Backtrace:
    [    1.203383] [<c021d88c>] (_enable_sysc) from [<c021dc40>] (_enable+0x158/0x284)
    [    1.203389]  r7:c1012940 r6:00000000 r5:c1059810 r4:c1012428
    [    1.203396] [<c021dae8>] (_enable) from [<c021e164>] (_setup.part.16+0x1c0/0x4e0)
    [    1.203400]  r7:c1012460 r6:c1007488 r5:c101244c r4:c1012428
    [    1.203408] [<c021dfa4>] (_setup.part.16) from [<c0e0d01c>] (__omap_hwmod_setup_all+0x120/0x134)
    [    1.203412]  r7:c0e0cefc r6:ffffe000 r5:c100c768 r4:c1012428
    [    1.203419] [<c0e0cefc>] (__omap_hwmod_setup_all) from [<c02023fc>] (do_one_initcall+0x84/0x1b0)
    [    1.203422]  r5:c1007488 r4:c10591c0
    [    1.203430] [<c0202378>] (do_one_initcall) from [<c0e0104c>] (kernel_init_freeable+0x218/0x2ac)
    [    1.203435]  r8:c0e49844 r7:c0e004f0 r6:c10591c0 r5:c10591c0 r4:00000003
    [    1.203444] [<c0e00e34>] (kernel_init_freeable) from [<c09b96d0>] (kernel_init+0x10/0x118)
    [    1.203449]  r10:00000000 r9:00000000 r8:00000000 r7:00000000 r6:00000000 r5:c09b96c0
    [    1.203452]  r4:00000000
    [    1.203459] [<c09b96c0>] (kernel_init) from [<c02010e0>] (ret_from_fork+0x14/0x34)
    [    1.203462] Exception stack(0xef0a1fb0 to 0xef0a1ff8)
    [    1.203466] 1fa0:                                     00000000 00000000 00000000 00000000
    [    1.203471] 1fc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
    [    1.203475] 1fe0: 00000000 00000000 00000000 00000000 00000013 00000000
    [    1.203478]  r5:c09b96c0 r4:00000000
    [    1.203485] Code: e3130080 1a000067 e5943004 e1a00004 (e5942044)
    [    1.568531] ---[ end trace 0000000000000002 ]---
    [    1.568535] Kernel panic - not syncing: Fatal exception
    [    1.568545] CPU1: stopping
    [    1.568551] CPU: 1 PID: 0 Comm: swapper/1 Tainted: G      D W         4.19.38-rt19 #15
    [    1.568553] Hardware name: Generic DRA74X (Flattened Device Tree)
    [    1.568555] Backtrace:
    [    1.568567] [<c020c744>] (dump_backtrace) from [<c020ca7c>] (show_stack+0x18/0x1c)
    [    1.568572]  r7:fa212000 r6:60000193 r5:00000000 r4:c1050a24
    [    1.568580] [<c020ca64>] (show_stack) from [<c09a5094>] (dump_stack+0x90/0xa4)
    [    1.568589] [<c09a5004>] (dump_stack) from [<c020f1b8>] (handle_IPI+0x1bc/0x22c)
    [    1.568594]  r7:fa212000 r6:00000001 r5:00000000 r4:c1059440
    [    1.568607] [<c020effc>] (handle_IPI) from [<c055407c>] (gic_handle_irq+0x94/0x98)
    [    1.568611]  r6:fa21200c r5:c10272bc r4:c10079bc
    [    1.568619] [<c0553fe8>] (gic_handle_irq) from [<c02019f8>] (__irq_svc+0x58/0xa0)
    [    1.568622] Exception stack(0xef0d9f28 to 0xef0d9f70)
    [    1.568627] 9f20:                   00000000 0000022c 00000000 c021a120 ffffe000 c10074bc
    [    1.568632] 9f40: c1007504 00000002 00000001 c1052656 c0bbce38 ef0d9f84 ef0d9f88 ef0d9f78
    [    1.568636] 9f60: c0208bf8 c0208bfc 60000013 ffffffff
    [    1.568641]  r9:ef0d8000 r8:00000001 r7:ef0d9f5c r6:ffffffff r5:60000013 r4:c0208bfc
    [    1.568652] [<c0208bbc>] (arch_cpu_idle) from [<c09be2c0>] (default_idle_call+0x34/0x40)
    [    1.568663] [<c09be28c>] (default_idle_call) from [<c025bcf0>] (do_idle+0x110/0x180)
    [    1.568671] [<c025bbe0>] (do_idle) from [<c025c04c>] (cpu_startup_entry+0x20/0x24)
    [    1.568676]  r10:00000000 r9:412fc0f2 r8:80007000 r7:c1059448 r6:00000001 r5:ef0d8000
    [    1.568679]  r4:00000086 r3:ef0d8000
    [    1.568687] [<c025c02c>] (cpu_startup_entry) from [<c020ed54>] (secondary_start_kernel+0x178/0x180)
    [    1.568693] [<c020ebdc>] (secondary_start_kernel) from [<8020210c>] (0x8020210c)
    [    1.568697]  r7:c1059448 r6:30c0387d r5:00000000 r4:af0771c0

  • Hello Kemal,

    Is it possible that the l3_main_2 clock is missing?

    Possibly the GPU messages are only conseqence errors.

    [ 0.714940] omap_hwmod: l3_main_2 using broken dt data from ocp
    [ 0.843866] omap_hwmod: gpu: _wait_target_ready failed: -16
    [ 0.849586] omap_hwmod: gpu: cannot be enabled for reset (3)

    One detail on my custom hardware is different to the reference designs. On the reference designs there are connected the second clock source with 22.5792MHz.

    It is possible that this clock is neccessary to start up linux correctly? I asked in this forum if the OPTIONAL second clock is really needed and why.

    The answer was no, the component would not be needed... here the thread: e2e.ti.com/.../743176

  • Hello,

    I believe the issue is not related to the GPU and I am wondering if you could please share the changes you have made in your DTS/DTSI files. If you could highlight the lines you have removed and please attach the changes as part of a text file. It is easier for us to parse the information from a text file.

    Regards,
    Krunal

  • Hello Kemal and Krunal, thank you for your help,


    I close this thread now but I have create a now one at https://e2e.ti.com/support/processors/f/791/t/850757