Hi,
When routing for DDR3L is there any guideline available for AM5718 's EMIF controller for bit swapping in byte lane , also any guidelines on Lane swapping.
I can observe in the AM5718 EVM schematics data lines D0-D8-D16-D24 are not considered for any bit swapping . Any specific reason for this.
We use the following DDR3L : : MT41K256M16TW-107 XIT:P TR
In micron DDR3L doc i could not find any suggestion
