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CCS/TMS320C6655: IBL Booting Fail

WSJ
Prodigy 190 points
Part Number: TMS320C6655

Tool/software: Code Composer Studio

[Condition]

1. BOOTMODE Configuration : DSP_GPIO[15:0] = 1000_1000_0010_1011

2. CORECLK P/N IN : 100MHz, DDRCLK P/N IN : 50MHz,  SRIOSGMIICLK P/N : 250MHz

[Status]

1. The power, reset, clock sequence for my custom board is shown below. (IO Before Core Power Sequencing).

The same CLK GEN as EVM was used, and the control timing of REFCLK2_PD# is as follows.

2.  Booting fail : IBL boot log is not displayed in the RS232 terminal.  (I2C Address : 0x51)

3.  BOOTCOMPLETE register : 0x00000001 (It was 0x00000001 when reading register value through CCS.)
4.  DEVSTAT register : 0x0000FFFF (It was 0x0000FFFF when reading register value through CCS.)

 

[Question]

1. If the board is normal, what about the BOOT waveform?

2. If the waveform I measured is abnormal, what is the cause of this waveform?

3. Is there a problem with the BOOTMODE [15: 0] value? (Using I2C EEPROM (IBL), Applications-> NAND)

4. If I use a 1 GHz core clock, are the following settings correct?

PLLM = 19, PLLD = 0, OUTPUT_DIVIDE = 1

5. How do I set up PLLM, PLLD and OUTPUT_DIVIDE when using the 667 MHz DDRCLKOUTP/N?

6. If there is no problem with the power, clock, and reset timing waveform I measured, why is the DEVSTAT register value set to 0x0000FFFF?

7. Based on the waveforms I measured, can I determine that my board's hardware is OK?

Thanks

  • 0
    TI__Guru**** 161600 points

    Hi,

    1. If normal, what about the BOOT waveform?

    2. If the waveform is abnormal, what is the cause of this waveform?

    From first glance it seems ok. Let me check against datasheet & available hw design guides.

    Best Regards,
    Yordan

  • 0 in reply to Yordan Kovachev
    Prodigy 190 points
    I modified the waveform I measured and added a question.
    Please check out.
    Best Regards
    WSJ
  • 0
    TI__Guru** 116170 points

    WSJ,

    Can you please connect to DSP core0 and read the value of Program counter and report it here. Program counter will indicate if the core is still in ROM or is branched to IBL source in MSMC.  DEVSTAT value of 0xFFF indicates that the BOOTMODE pins are not getting correctly latched into the device so the ROM doesn`t detect the boot mode so I expect the core to be hung in ROM memory.

    For IBL booting, we expect the DEVSTAT register to read I2C boot mode so that ROM fetches the image from the I2C EEPROM. this most likely appears to be an issue with power sequencing or weak pull up/pull down on the BOOTMODE pins.

    Given core clock is 100 Mhz, the setting to get to 1Ghz appears to be correct based on table provided in Section 6.29 in the data manual here:

    http://www.ti.com/lit/ds/symlink/tms320c6657.pdf

    I will let my HW colleague comment on the power and clock and reset timing questions but in the meantime, you can look at guidance provided in the HArdware design guide for Keystone Devices here:

    http://www.ti.com/lit/an/sprabi2d/sprabi2d.pdf

    Regards,

    Rahul

  • 0 in reply to Rahul Prabhu
    TI__Mastermind 46460 points

    WSJ,

    You are asking about IBL booting but then you have questions about basic operation.  You should use CCS and a GEL file to validate the operation of the DSP and the attached peripherals.  This will also allow you to validate PLL programming and DDR configuration..You can then build and load you code and then boot it while using CCS to verify that the your code runs and then you can write the IBL the I2C and verify the booting process.

    Tom