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First step in loading code over HPI on the C6416

Andy Chernock
Intellectual 740 points

I have a customer that has a question about booting a C6416

The design contains a 6416 connected via HPI and EMIF to an FPGA and has 8 Mbytes of off chip SRAM. 

The part boots over HPI, and basically the question is...to use the 8 Mbytes of off chip SRAM for code storage my customer believes that the first step in loading code over the HPI is to configure the EMIF, and then perform the normal process of code loading.   Is this correct? 

If it’s not what document should I forward to the customer for more guidance?

  • 0
    TI__Guru* 84110 points

    The first step would be to get the C6416 initialized in any way needed, such as PLLs and such. Then the peripherals need to be initialized, at least any that will be needed for the boot process, which of course would include the EMIF for this example.

    For documents, they will want the datasheet, HPI User's Guide, and EMIF User's Guide.

    Regards,
    RandyP

     

    If this answers your question, please click the  Verify Answer  button below. If not, please reply back with more information.

  • 0 in reply to RandyP
    Prodigy 10 points

    Thanks, that is what I'd thought, but I'm glad to have confirmation.  Is there a way to automate the process of putting this configuration data into a SREC file in the appropriate order?  I couldn't easily find a way to automate that process, and it appears that hex6x.exe just puts the data in address order.

    Regards,

    Joe

  • 0 in reply to Joseph French
    Intellectual 835 points

    I don't exactly understand the layout of your design but I assume there is another CPU for communication with 6416 via HPI. If there is, you can use the HPI boot mode and download all of your system load to DSP memory via HPI.

    Also you have to write a small piece of code in host CPU for downloading the DSP Load, hex6x.exe converts the .out file to an understandable text file. You should write the output of hex6x.exe to your HOST CPU's FLASH and your download code running on the HOST CPU should read and write the DSP Load from HOST CPU FLASH to DSP Memory, address by address via HPI access.

    I hope this information is not totally useless for you.

    Alphan

  • 0 in reply to Joseph French
    TI__Guru*** 125430 points

    Joseph French said:
    Is there a way to automate the process of putting this configuration data into a SREC file in the appropriate order?

    None of the TI tools will automate that step.  However, peripheral configuration generally involves things like read-modify-write which cannot be expressed in an srec anyway.  I think the previous post pretty much captures it.