Other Parts Discussed in Thread: BEAGLEBOARD-X15, AM5728, AM3356
Hello,
I had already opened a thread on this topic. The old thread will now be closed.
https://e2e.ti.com/support/processors/f/791/t/848623
I thought it would be better, for the sake of clarity, if I reset the u-boot and kernel-rt from the tisdk.
In the next steps I'll explain in which files I changed something and which commands I used to build the u-boot/kernel.
Currently I get a Kernel-Panic message because it has "broken dt data" on L3_Main_2:
U-Boot SPL 2019.01-g560ca90-dirty (Oct 24 2019 - 10:40:04 +0200) DRA752-GP ES2.0 Trying to boot from MMC1 no pinctrl state for default mode Loading Environment from FAT... *** Warning - bad CRC, using default environment Loading Environment from MMC... Card did not respond to voltage select! *** Warning - No block device, using default environment U-Boot 2019.01-g560ca90-dirty (Oct 24 2019 - 10:40:04 +0200) CPU : DRA752-GP ES2.0 Model: TI AM5728 BeagleBoard-X15 Board: custom DRAM: 1 GiB MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1 Loading Environment from FAT... *** Warning - bad CRC, using default environment Loading Environment from MMC... Card did not respond to voltage select! *** Warning - No block device, using default environment Card did not respond to voltage select! invalid mmc device Net: Could not get PHY for ethernet@48484000: addr 1 Warning: ethernet@48484000 using MAC address from ROM eth0: ethernet@48484000 Hit any key to stop autoboot: 0 => setenv bootargs console=ttyS2,115200 debug verbose panic=0 earlyprintk mem=0x40000000 loglevel=7 => load mmc 0:1 0x88000000 custom.dtb 90520 bytes read in 6 ms (14.4 MiB/s) => load mmc 0:1 0x82000000 zImage 4203008 bytes read in 187 ms (21.4 MiB/s) => bootz 0x82000000 - 0x88000000 ## Flattened Device Tree blob at 88000000 Booting using the fdt blob at 0x88000000 Loading Device Tree to 8ffe6000, end 8ffff197 ... OK Starting kernel ... [ 0.000000] Booting Linux on physical CPU 0x0 [ 0.000000] Linux version 4.19.38-rt19-g1224cd679e (rene@ubuntu) (gcc version 8.3.0 (GNU Toolchain for the A-profile Architecture 8.3-2019.03 (ar9 [ 0.000000] CPU: ARMv7 Processor [412fc0f2] revision 2 (ARMv7), cr=30c5387d [ 0.000000] CPU: div instructions available: patching division code [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, PIPT instruction cache [ 0.000000] OF: fdt: Machine model: TI AM5728 BeagleBoard-X15 [ 0.000000] bootconsole [earlycon0] enabled [ 0.000000] Memory policy: Data cache writealloc [ 0.000000] efi: Getting EFI parameters from FDT: [ 0.000000] efi: UEFI not found. [ 0.000000] Reserved memory: created CMA memory pool at 0x0000000095800000, size 56 MiB [ 0.000000] OF: reserved mem: initialized node ipu2-memory@95800000, compatible id shared-dma-pool [ 0.000000] Reserved memory: created CMA memory pool at 0x0000000099000000, size 64 MiB [ 0.000000] OF: reserved mem: initialized node dsp1-memory@99000000, compatible id shared-dma-pool [ 0.000000] Reserved memory: created CMA memory pool at 0x000000009d000000, size 32 MiB [ 0.000000] OF: reserved mem: initialized node ipu1-memory@9d000000, compatible id shared-dma-pool [ 0.000000] Reserved memory: created CMA memory pool at 0x000000009f000000, size 8 MiB [ 0.000000] OF: reserved mem: initialized node dsp2-memory@9f000000, compatible id shared-dma-pool [ 0.000000] cma: Reserved 24 MiB at 0x00000000be400000 [ 0.000000] OMAP4: Map 0x00000000bfd00000 to (ptrval) for dram barrier [ 0.000000] DRA752 ES2.0 [ 0.000000] random: get_random_bytes called from start_kernel+0xb0/0x480 with crng_init=0 [ 0.000000] percpu: Embedded 15 pages/cpu s32288 r8192 d20960 u61440 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 210496 [ 0.000000] Kernel command line: console=ttyS2,115200 debug verbose panic=0 earlyprintk mem=0x40000000 loglevel=7 [ 0.000000] Dentry cache hash table entries: 131072 (order: 8, 1048576 bytes) [ 0.000000] Inode-cache hash table entries: 65536 (order: 6, 262144 bytes) [ 0.000000] Memory: 635908K/848896K available (8192K kernel code, 329K rwdata, 2644K rodata, 2048K init, 275K bss, 24572K reserved, 188416K cma-r) [ 0.000000] Virtual kernel memory layout: [ 0.000000] vector : 0xffff0000 - 0xffff1000 ( 4 kB) [ 0.000000] fixmap : 0xffc00000 - 0xfff00000 (3072 kB) [ 0.000000] vmalloc : 0xf0800000 - 0xff800000 ( 240 MB) [ 0.000000] lowmem : 0xc0000000 - 0xf0000000 ( 768 MB) [ 0.000000] pkmap : 0xbfe00000 - 0xc0000000 ( 2 MB) [ 0.000000] modules : 0xbf000000 - 0xbfe00000 ( 14 MB) [ 0.000000] .text : 0x(ptrval) - 0x(ptrval) (10208 kB) [ 0.000000] .init : 0x(ptrval) - 0x(ptrval) (2048 kB) [ 0.000000] .data : 0x(ptrval) - 0x(ptrval) ( 330 kB) [ 0.000000] .bss : 0x(ptrval) - 0x(ptrval) ( 276 kB) [ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1 [ 0.000000] rcu: Preemptible hierarchical RCU implementation. [ 0.000000] rcu: RCU priority boosting: priority 1 delay 500 ms. [ 0.000000] No expedited grace period (rcu_normal_after_boot). [ 0.000000] Tasks RCU enabled. [ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16 [ 0.000000] GIC: Using split EOI/Deactivate mode [ 0.000000] OMAP clockevent source: timer1 at 32786 Hz [ 0.000000] arch_timer: cp15 timer(s) running at 6.14MHz (phys). [ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x16af5adb9, max_idle_ns: 440795202250 ns [ 0.000004] sched_clock: 56 bits at 6MHz, resolution 162ns, wraps every 4398046511023ns [ 0.000011] Switching to timer-based delay loop, resolution 162ns [ 0.000275] clocksource: 32k_counter: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 58327039986419 ns [ 0.000278] OMAP clocksource: 32k_counter at 32768 Hz [ 0.000706] Console: colour dummy device 80x30 [ 0.322331] Calibrating delay loop (skipped), value calculated using timer frequency.. 12.29 BogoMIPS (lpj=61475) [ 0.322339] pid_max: default: 32768 minimum: 301 [ 0.322473] Mount-cache hash table entries: 2048 (order: 1, 8192 bytes) [ 0.322482] Mountpoint-cache hash table entries: 2048 (order: 1, 8192 bytes) [ 0.323198] CPU: Testing write buffer coherency: ok [ 0.323228] CPU0: Spectre v2: using ICIALLU workaround [ 0.323470] /cpus/cpu@0 missing clock-frequency property [ 0.368406] /cpus/cpu@1 missing clock-frequency property [ 0.373857] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000 [ 0.430219] Setting up static identity map for 0x80200000 - 0x80200060 [ 0.450195] rcu: Hierarchical SRCU implementation. [ 0.510718] EFI services will not be available. [ 0.530332] smp: Bringing up secondary CPUs ... [ 0.650758] CPU1: thread -1, cpu 1, socket 0, mpidr 80000001 [ 0.650762] CPU1: Spectre v2: using ICIALLU workaround [ 0.650894] smp: Brought up 1 node, 2 CPUs [ 0.666168] SMP: Total of 2 processors activated (24.59 BogoMIPS). [ 0.672513] CPU: All CPU(s) started in HYP mode. [ 0.677246] CPU: Virtualization extensions available. [ 0.683070] devtmpfs: initialized [ 0.715248] VFP support v0.3: implementor 41 architecture 4 part 30 variant f rev 0 [ 0.723462] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns [ 0.733554] futex hash table entries: 512 (order: 3, 32768 bytes) [ 0.743088] pinctrl core: initialized pinctrl subsystem [ 0.749289] DMI not present or invalid. [ 0.753692] NET: Registered protocol family 16 [ 0.761024] DMA: preallocated 256 KiB pool for atomic coherent allocations [ 0.768980] omap_hwmod: l3_main_2 using broken dt data from ocp [ 0.902637] omap_hwmod: gpu: _wait_target_ready failed: -16 [ 0.908358] omap_hwmod: gpu: cannot be enabled for reset (3) [ 0.981149] Unhandled fault: asynchronous external abort (0x1211) at 0x00000000 [ 0.981153] pgd = (ptrval) [ 0.981156] [00000000] *pgd=80000080004003, *pmd=00000000 [ 0.981168] Internal error: : 1211 [#1] PREEMPT SMP ARM [ 0.981171] Modules linked in: [ 0.981180] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.19.38-rt19-g1224cd679e #1 [ 0.981182] Hardware name: Generic DRA74X (Flattened Device Tree) [ 0.981193] PC is at _enable_sysc+0x5c/0x25c [ 0.981198] LR is at _enable_sysc+0x48/0x25c [ 0.981202] pc : [<c021d908>] lr : [<c021d8f4>] psr: 40000013 [ 0.981205] sp : ef0a1e38 ip : ef0a1e38 fp : ef0a1e64 [ 0.981209] r10: c0e58320 r9 : c0e48824 r8 : 00000000 [ 0.981212] r7 : c1012900 r6 : 00000000 r5 : c1007488 r4 : c10123e8 [ 0.981215] r3 : c101246c r2 : c101248c r1 : 00000078 r0 : c10123e8 [ 0.981220] Flags: nZcv IRQs on FIQs on Mode SVC_32 ISA ARM Segment user [ 0.981225] Control: 30c5387d Table: 80003000 DAC: fffffffd [ 0.981228] Process swapper/0 (pid: 1, stack limit = 0x(ptrval)) [ 0.981233] Stack: (0xef0a1e38 to 0xef0a2000) [ 0.981237] 1e20: c0224e90 c09b9e08 [ 0.981243] 1e40: ef0a1e64 4300add3 c10123e8 c1052c10 00000000 c1012900 ef0a1e8c ef0a1e68 [ 0.981249] 1e60: c021dc60 c021d8b8 c10123e8 c100ff70 c10123e8 c101240c c1007488 c1012420 [ 0.981254] 1e80: ef0a1ebc ef0a1e90 c021e184 c021db14 ef0a1ebc ef0a1ea0 00000008 4300add3 [ 0.981259] 1ea0: c10123e8 c100c728 ffffe000 c0e0cee4 ef0a1ed4 ef0a1ec0 c0e0d004 c021dfd0 [ 0.981265] 1ec0: c10525c0 c1007488 ef0a1f4c ef0a1ed8 c02023fc c0e0cef0 00000000 c0bbb46c [ 0.981270] 1ee0: c0bbb44c c0bbb400 c0bc6a68 c1007488 00000000 c0bbb424 00000002 00000002 [ 0.981275] 1f00: 00000000 c0bb11e8 c0e004f0 c0c933f0 c1018960 ef664486 ef66448f 4300add3 [ 0.981280] 1f20: c027ff88 4300add3 c10525c0 00000003 c10525c0 c10525c0 c0e004f0 c0e48844 [ 0.981285] 1f40: ef0a1f94 ef0a1f50 c0e01048 c0202384 00000002 00000002 00000000 c0e004f0 [ 0.981291] 1f60: c0c933f0 000000d1 c09b9e5c 00000000 c09b4c88 00000000 00000000 00000000 [ 0.981296] 1f80: 00000000 00000000 ef0a1fac ef0a1f98 c09b4c98 c0e00e40 00000000 c09b4c88 [ 0.981301] 1fa0: 00000000 ef0a1fb0 c02010e0 c09b4c94 00000000 00000000 00000000 00000000 [ 0.981306] 1fc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 [ 0.981311] 1fe0: 00000000 00000000 00000000 00000000 00000013 00000000 00000000 00000000 [ 0.981312] Backtrace: [ 0.981322] [<c021d8ac>] (_enable_sysc) from [<c021dc60>] (_enable+0x158/0x284) [ 0.981328] r7:c1012900 r6:00000000 r5:c1052c10 r4:c10123e8 [ 0.981336] [<c021db08>] (_enable) from [<c021e184>] (_setup.part.16+0x1c0/0x4e0) [ 0.981341] r7:c1012420 r6:c1007488 r5:c101240c r4:c10123e8 [ 0.981352] [<c021dfc4>] (_setup.part.16) from [<c0e0d004>] (__omap_hwmod_setup_all+0x120/0x134) [ 0.981357] r7:c0e0cee4 r6:ffffe000 r5:c100c728 r4:c10123e8 [ 0.981366] [<c0e0cee4>] (__omap_hwmod_setup_all) from [<c02023fc>] (do_one_initcall+0x84/0x1b0) [ 0.981369] r5:c1007488 r4:c10525c0 [ 0.981377] [<c0202378>] (do_one_initcall) from [<c0e01048>] (kernel_init_freeable+0x214/0x2a8) [ 0.981381] r8:c0e48844 r7:c0e004f0 r6:c10525c0 r5:c10525c0 r4:00000003 [ 0.981391] [<c0e00e34>] (kernel_init_freeable) from [<c09b4c98>] (kernel_init+0x10/0x118) [ 0.981396] r10:00000000 r9:00000000 r8:00000000 r7:00000000 r6:00000000 r5:c09b4c88 [ 0.981398] r4:00000000 [ 0.981406] [<c09b4c88>] (kernel_init) from [<c02010e0>] (ret_from_fork+0x14/0x34) [ 0.981409] Exception stack(0xef0a1fb0 to 0xef0a1ff8) [ 0.981413] 1fa0: 00000000 00000000 00000000 00000000 [ 0.981418] 1fc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 [ 0.981422] 1fe0: 00000000 00000000 00000000 00000000 00000013 00000000 [ 0.981426] r5:c09b4c88 r4:00000000 [ 0.981432] Code: e3130080 1a000067 e5943004 e1a00004 (e5942044) [ 1.346028] ---[ end trace 0000000000000001 ]--- [ 1.346098] Kernel panic - not syncing: Attempted to kill init! exitcode=0x0000000b [ 1.346098] [ 1.346108] CPU1: stopping [ 1.346115] CPU: 1 PID: 0 Comm: swapper/1 Tainted: G D 4.19.38-rt19-g1224cd679e #1 [ 1.346117] Hardware name: Generic DRA74X (Flattened Device Tree) [ 1.346119] Backtrace: [ 1.346132] [<c020c748>] (dump_backtrace) from [<c020ca80>] (show_stack+0x18/0x1c) [ 1.346137] r7:fa212000 r6:60000193 r5:00000000 r4:c10505a4 [ 1.346146] [<c020ca68>] (show_stack) from [<c09a0684>] (dump_stack+0x90/0xa4) [ 1.346154] [<c09a05f4>] (dump_stack) from [<c020f1b8>] (handle_IPI+0x1bc/0x22c) [ 1.346160] r7:fa212000 r6:00000001 r5:00000000 r4:c1052840 [ 1.346170] [<c020effc>] (handle_IPI) from [<c05522a0>] (gic_handle_irq+0x94/0x98) [ 1.346174] r6:fa21200c r5:c102707c r4:c100796c [ 1.346181] [<c055220c>] (gic_handle_irq) from [<c02019f8>] (__irq_svc+0x58/0xa0) [ 1.346184] Exception stack(0xef0cff28 to 0xef0cff70) [ 1.346189] ff20: 00000000 0000018c 00000000 c021a140 ffffe000 c10074bc [ 1.346195] ff40: c1007504 00000002 00000001 c10521d6 c0bbbc90 ef0cff84 ef0cff88 ef0cff78 [ 1.346198] ff60: c0208bf8 c0208bfc 60000013 ffffffff [ 1.346204] r9:ef0ce000 r8:00000001 r7:ef0cff5c r6:ffffffff r5:60000013 r4:c0208bfc [ 1.346214] [<c0208bbc>] (arch_cpu_idle) from [<c09b9870>] (default_idle_call+0x34/0x40) [ 1.346222] [<c09b983c>] (default_idle_call) from [<c025b928>] (do_idle+0x110/0x180) [ 1.346229] [<c025b818>] (do_idle) from [<c025bc84>] (cpu_startup_entry+0x20/0x24) [ 1.346235] r10:00000000 r9:412fc0f2 r8:80007000 r7:c1052848 r6:00000001 r5:ef0ce000 [ 1.346238] r4:00000086 r3:ef0ce000 [ 1.346245] [<c025bc64>] (cpu_startup_entry) from [<c020ed54>] (secondary_start_kernel+0x178/0x180) [ 1.346252] [<c020ebdc>] (secondary_start_kernel) from [<8020210c>] (0x8020210c) [ 1.346256] r7:c1052848 r6:30c0387d r5:00000000 r4:af0771c0
Make u-boot
make clean
make distclean
make tisdk_am57xx-evm-am57xx_evm_defconfig
make menuconfig
-> DEBUG_LL [=y]
-> DEBUG_LL_UART_8250 [=y]
-> DEBUG_UART_PHYS [=0x48020000]
-> DEBUG_UART_8250_SHIFT [=2]
I have changed 2 files:
board-support/u-boot/board/ti/am57xx/board.c
board-support/u-boot/board/ti/am57xx/mux_data.h
make j8
copy MLO to bootpartition as MLO
copy u-boot.bin to bootpartition as u-boot.bin
copy u-boot.img to bootpartition as u-boot.img
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
*
* Author: Felipe Balbi <balbi@ti.com>
*
* Based on board/ti/dra7xx/evm.c
*/
#include <common.h>
#include <palmas.h>
#include <sata.h>
#include <usb.h>
#include <asm/omap_common.h>
#include <asm/omap_sec_common.h>
#include <asm/emif.h>
#include <asm/gpio.h>
#include <asm/arch/gpio.h>
#include <asm/arch/clock.h>
#include <asm/arch/dra7xx_iodelay.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/sata.h>
#include <asm/arch/gpio.h>
#include <asm/arch/omap.h>
#include <environment.h>
#include <usb.h>
#include <linux/usb/gadget.h>
#include <dwc3-uboot.h>
#include <dwc3-omap-uboot.h>
#include <ti-usb-phy-uboot.h>
#include <mmc.h>
#include "../common/board_detect.h"
#include "mux_data.h"
#define STR_BOARD_NAME "**Custom**"
#define board_is_x15() board_ti_is("BBRDX15_")
#define board_is_x15_revb1() (board_ti_is("BBRDX15_") && \
!strncmp("B.10", board_ti_get_rev(), 3))
#define board_is_x15_revc() (board_ti_is("BBRDX15_") && \
!strncmp("C.00", board_ti_get_rev(), 3))
#define board_is_am572x_evm() board_ti_is("AM572PM_")
#define board_is_am572x_evm_reva3() \
(board_ti_is("AM572PM_") && \
!strncmp("A.30", board_ti_get_rev(), 3))
#define board_is_am574x_idk() board_ti_is("AM574IDK")
#define board_is_am572x_idk() board_ti_is("AM572IDK")
#define board_is_am571x_idk() board_ti_is("AM571IDK")
#ifdef CONFIG_DRIVER_TI_CPSW
#include <cpsw.h>
#endif
DECLARE_GLOBAL_DATA_PTR;
#define GPIO_ETH_LCD GPIO_TO_PIN(2, 22)
/* GPIO 7_11 */
#define GPIO_DDR_VTT_EN 203
/* Touch screen controller to identify the LCD */
#define OSD_TS_FT_BUS_ADDRESS 0
#define OSD_TS_FT_CHIP_ADDRESS 0x38
#define OSD_TS_FT_REG_ID 0xA3
/*
* Touchscreen IDs for various OSD panels
* Ref: http://www.osddisplays.com/TI/OSD101T2587-53TS_A.1.pdf
*/
/* Used on newer osd101t2587 Panels */
#define OSD_TS_FT_ID_5x46 0x54
/* Used on older osd101t2045 Panels */
#define OSD_TS_FT_ID_5606 0x08
#define SYSINFO_BOARD_NAME_MAX_LEN 45
#define TPS65903X_PRIMARY_SECONDARY_PAD2 0xFB
#define TPS65903X_PAD2_POWERHOLD_MASK 0x20
const struct omap_sysinfo sysinfo = {
"Board: custom\n"
};
static const struct dmm_lisa_map_regs AM57xx_533MHZ_dmm_regs = {
.dmm_lisa_map_0 = 0x00000000,
.dmm_lisa_map_1 = 0x00000000,
.dmm_lisa_map_2 = 0x80640300,
.dmm_lisa_map_3 = 0xFF020100,
.is_ma_present = 0x1
};
void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
{
*dmm_lisa_regs = &AM57xx_533MHZ_dmm_regs;
}
static const struct emif_regs AM57xx_533MHZ_emif_regs = {
.sdram_config_init = 0x61851AB2,
.sdram_config = 0x61851AB2,
.sdram_config2 = 0x00000000,
.ref_ctrl = 0x00004111,
.ref_ctrl_final = 0x0000081E,
.sdram_tim1 = 0xCEEF2663,
.sdram_tim2 = 0x305A7FDA,
.sdram_tim3 = 0x407F8558,
.read_idle_ctrl = 0x00050000,
.zq_config = 0x5007190B,
.temp_alert_config = 0x00000000,
.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
.emif_ddr_phy_ctlr_1_init = 0x0024400B,
.emif_ddr_phy_ctlr_1 = 0x0E24400B,
.emif_rd_wr_exec_thresh = 0x00000305
};
/* Ext phy ctrl regs 1-35 */
static const u32 am57xx_533MHZ_emif1_ddr3_ext_phy_ctrl_const_regs[] = {
0x04040100, // EMIF1_EXT_PHY_CTRL_1
0x006B0083, // EMIF1_EXT_PHY_CTRL_2
0x006B0075, // EMIF1_EXT_PHY_CTRL_3
0x006B0088, // EMIF1_EXT_PHY_CTRL_4
0x006B0072, // EMIF1_EXT_PHY_CTRL_5
0x006B006B, // EMIF1_EXT_PHY_CTRL_6
0x00320032, // EMIF1_EXT_PHY_CTRL_7
0x00320032, // EMIF1_EXT_PHY_CTRL_8
0x00320032, // EMIF1_EXT_PHY_CTRL_9
0x00320032, // EMIF1_EXT_PHY_CTRL_10
0x00320032, // EMIF1_EXT_PHY_CTRL_11
0x00600065, // EMIF1_EXT_PHY_CTRL_12
0x00600056, // EMIF1_EXT_PHY_CTRL_13
0x0060006A, // EMIF1_EXT_PHY_CTRL_14
0x00600059, // EMIF1_EXT_PHY_CTRL_15
0x00600060, // EMIF1_EXT_PHY_CTRL_16
0x00400045, // EMIF1_EXT_PHY_CTRL_17
0x00400036, // EMIF1_EXT_PHY_CTRL_18
0x0040004A, // EMIF1_EXT_PHY_CTRL_19
0x00400039, // EMIF1_EXT_PHY_CTRL_20
0x00400040, // EMIF1_EXT_PHY_CTRL_21
0x00800080, // EMIF1_EXT_PHY_CTRL_22
0x00800080, // EMIF1_EXT_PHY_CTRL_23
0x40010080, // EMIF1_EXT_PHY_CTRL_24
0x08102040, // EMIF1_EXT_PHY_CTRL_25
0x00000073, // EMIF1_EXT_PHY_CTRL_26
0x00000065, // EMIF1_EXT_PHY_CTRL_27
0x00000078, // EMIF1_EXT_PHY_CTRL_28
0x00000062, // EMIF1_EXT_PHY_CTRL_29
0x00000000, // EMIF1_EXT_PHY_CTRL_30
0x00000035, // EMIF1_EXT_PHY_CTRL_31
0x00000026, // EMIF1_EXT_PHY_CTRL_32
0x0000003A, // EMIF1_EXT_PHY_CTRL_33
0x00000029, // EMIF1_EXT_PHY_CTRL_34
0x00000000, // EMIF1_EXT_PHY_CTRL_35
0x00000077 // EMIF1_EXT_PHY_CTRL_36
};
static const u32 am57xx_533MHZ_emif2_ddr3_ext_phy_ctrl_const_regs[] = {
0x04040100, // EMIF2_EXT_PHY_CTRL_1
0x006B0083, // EMIF2_EXT_PHY_CTRL_2
0x006B0077, // EMIF2_EXT_PHY_CTRL_3
0x006B0088, // EMIF2_EXT_PHY_CTRL_4
0x006B0075, // EMIF2_EXT_PHY_CTRL_5
0x006B006B, // EMIF2_EXT_PHY_CTRL_6
0x00320032, // EMIF2_EXT_PHY_CTRL_7
0x00320032, // EMIF2_EXT_PHY_CTRL_8
0x00320032, // EMIF2_EXT_PHY_CTRL_9
0x00320032, // EMIF2_EXT_PHY_CTRL_10
0x00320032, // EMIF2_EXT_PHY_CTRL_11
0x00600062, // EMIF2_EXT_PHY_CTRL_12
0x00600054, // EMIF2_EXT_PHY_CTRL_13
0x00600068, // EMIF2_EXT_PHY_CTRL_14
0x00600056, // EMIF2_EXT_PHY_CTRL_15
0x00600060, // EMIF2_EXT_PHY_CTRL_16
0x00400042, // EMIF2_EXT_PHY_CTRL_17
0x00400034, // EMIF2_EXT_PHY_CTRL_18
0x00400048, // EMIF2_EXT_PHY_CTRL_19
0x00400036, // EMIF2_EXT_PHY_CTRL_20
0x00400040, // EMIF2_EXT_PHY_CTRL_21
0x00800080, // EMIF2_EXT_PHY_CTRL_22
0x00800080, // EMIF2_EXT_PHY_CTRL_23
0x40010080, // EMIF2_EXT_PHY_CTRL_24
0x08102040, // EMIF2_EXT_PHY_CTRL_25
0x00000073, // EMIF2_EXT_PHY_CTRL_26
0x00000067, // EMIF2_EXT_PHY_CTRL_27
0x00000078, // EMIF2_EXT_PHY_CTRL_28
0x00000065, // EMIF2_EXT_PHY_CTRL_29
0x00000000, // EMIF2_EXT_PHY_CTRL_30
0x00000032, // EMIF2_EXT_PHY_CTRL_31
0x00000024, // EMIF2_EXT_PHY_CTRL_32
0x00000038, // EMIF2_EXT_PHY_CTRL_33
0x00000026, // EMIF2_EXT_PHY_CTRL_34
0x00000000, // EMIF2_EXT_PHY_CTRL_35
0x00000077 // EMIF2_EXT_PHY_CTRL_36
};
void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
{
switch (emif_nr) {
case 1:
*regs = &AM57xx_533MHZ_emif_regs;
break;
case 2:
*regs = &AM57xx_533MHZ_emif_regs;
break;
}
}
void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size)
{
switch (emif_nr) {
case 1:
*regs = am57xx_533MHZ_emif1_ddr3_ext_phy_ctrl_const_regs;
*size = ARRAY_SIZE(am57xx_533MHZ_emif1_ddr3_ext_phy_ctrl_const_regs);
break;
case 2:
*regs = am57xx_533MHZ_emif2_ddr3_ext_phy_ctrl_const_regs;
*size = ARRAY_SIZE(am57xx_533MHZ_emif2_ddr3_ext_phy_ctrl_const_regs);
break;
}
}
struct vcores_data beagle_x15_volts = {
.mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
.mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
.mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.mpu.addr = TPS659038_REG_ADDR_SMPS12,
.mpu.pmic = &tps659038,
.mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
.eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
.eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
.eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
.eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
.eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
.eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
.eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.eve.addr = TPS659038_REG_ADDR_SMPS45,
.eve.pmic = &tps659038,
.eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
.gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
.gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
.gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
.gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
.gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
.gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
.gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.gpu.addr = TPS659038_REG_ADDR_SMPS45,
.gpu.pmic = &tps659038,
.gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
.core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
.core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
.core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.core.addr = TPS659038_REG_ADDR_SMPS6,
.core.pmic = &tps659038,
.iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
.iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
.iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
.iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
.iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
.iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
.iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.iva.addr = TPS659038_REG_ADDR_SMPS45,
.iva.pmic = &tps659038,
.iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
};
int get_voltrail_opp(int rail_offset)
{
int opp;
switch (rail_offset) {
case VOLT_MPU:
opp = DRA7_MPU_OPP;
break;
case VOLT_CORE:
opp = DRA7_CORE_OPP;
break;
case VOLT_GPU:
opp = DRA7_GPU_OPP;
break;
case VOLT_EVE:
opp = DRA7_DSPEVE_OPP;
break;
case VOLT_IVA:
opp = DRA7_IVA_OPP;
break;
default:
opp = OPP_NOM;
}
return opp;
}
#ifdef CONFIG_SPL_BUILD
/* No env to setup for SPL */
static inline void setup_board_eeprom_env(void) { }
/* Override function to read eeprom information */
void do_board_detect(void) { }
#else /* CONFIG_SPL_BUILD */
/* Override function to read eeprom information: actual i2c read done by SPL*/
void do_board_detect(void) { }
static void setup_board_eeprom_env(void)
{
set_board_info_env(STR_BOARD_NAME);
}
#endif /* CONFIG_SPL_BUILD */
void vcores_init(void)
{
*omap_vcores = &beagle_x15_volts;
}
void hw_data_init(void)
{
*prcm = &dra7xx_prcm;
if (is_dra72x())
*dplls_data = &dra72x_dplls;
else if (is_dra76x())
*dplls_data = &dra76x_dplls;
else
*dplls_data = &dra7xx_dplls;
*ctrl = &dra7xx_ctrl;
}
int board_init(void)
{
gpmc_init();
gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);
return 0;
}
#if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
static int device_okay(const char *path)
{
int node;
node = fdt_path_offset(gd->fdt_blob, path);
if (node < 0)
return 0;
return fdtdec_get_is_enabled(gd->fdt_blob, node);
}
#endif
int board_late_init(void)
{
setup_board_eeprom_env();
u8 val;
/*
* DEV_CTRL.DEV_ON = 1 please - else palmas switches off in 8 seconds
* This is the POWERHOLD-in-Low behavior.
*/
palmas_i2c_write_u8(TPS65903X_CHIP_P1, 0xA0, 0x1);
/*
* Default FIT boot on HS devices. Non FIT images are not allowed
* on HS devices.
*/
if (get_device_type() == HS_DEVICE)
env_set("boot_fit", "1");
/*
* Set the GPIO7 Pad to POWERHOLD. This has higher priority
* over DEV_CTRL.DEV_ON bit. This can be reset in case of
* PMIC Power off. So to be on the safer side set it back
* to POWERHOLD mode irrespective of the current state.
*/
palmas_i2c_read_u8(TPS65903X_CHIP_P1, TPS65903X_PRIMARY_SECONDARY_PAD2,
&val);
val = val | TPS65903X_PAD2_POWERHOLD_MASK;
palmas_i2c_write_u8(TPS65903X_CHIP_P1, TPS65903X_PRIMARY_SECONDARY_PAD2,
val);
omap_die_id_serial();
omap_set_fastboot_vars();
#if !defined(CONFIG_SPL_BUILD)
board_ti_set_ethaddr(2);
#endif
#if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
if (device_okay("/ocp/omap_dwc3_1@48880000"))
enable_usb_clocks(0);
if (device_okay("/ocp/omap_dwc3_2@488c0000"))
enable_usb_clocks(1);
#endif
return 0;
}
void set_muxconf_regs(void)
{
do_set_mux32((*ctrl)->control_padconf_core_base,
early_padconf, ARRAY_SIZE(early_padconf));
}
#ifdef CONFIG_IODELAY_RECALIBRATION
void recalibrate_iodelay(void)
{
const struct pad_conf_entry *pconf;
const struct iodelay_cfg_entry *iod, *delta_iod;
int pconf_sz, iod_sz, delta_iod_sz = 0;
int ret;
pconf = core_padconf_array_essential_custom;
pconf_sz = ARRAY_SIZE(core_padconf_array_essential_custom);
if (omap_revision() == DRA752_ES1_1) {
iod = iodelay_cfg_array_custom_sr1_1;
iod_sz = ARRAY_SIZE(iodelay_cfg_array_custom_sr1_1);
} else {
/* Since full production should switch to SR2.0 */
iod = iodelay_cfg_array_custom_sr2_0;
iod_sz = ARRAY_SIZE(iodelay_cfg_array_custom_sr2_0);
}
/* Setup I/O isolation */
ret = __recalibrate_iodelay_start();
if (ret)
goto err;
/* Do the muxing here */
do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
/* Setup IOdelay configuration */
ret = do_set_iodelay((*ctrl)->iodelay_config_base, iod, iod_sz);
if (delta_iod_sz)
ret = do_set_iodelay((*ctrl)->iodelay_config_base, delta_iod,
delta_iod_sz);
err:
/* Closeup.. remove isolation */
__recalibrate_iodelay_end(ret);
}
#endif
#if defined(CONFIG_MMC)
int board_mmc_init(bd_t *bis)
{
omap_mmc_init(0, 0, 0, -1, -1);
omap_mmc_init(1, 0, 0, -1, -1);
return 0;
}
static const struct mmc_platform_fixups am57x_es1_1_mmc1_fixups = {
.hw_rev = "rev11",
.unsupported_caps = MMC_CAP(MMC_HS_200) |
MMC_CAP(UHS_SDR104),
.max_freq = 96000000,
};
static const struct mmc_platform_fixups am57x_es1_1_mmc23_fixups = {
.hw_rev = "rev11",
.unsupported_caps = MMC_CAP(MMC_HS_200) |
MMC_CAP(UHS_SDR104) |
MMC_CAP(UHS_SDR50),
.max_freq = 48000000,
};
const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr)
{
switch (omap_revision()) {
case DRA752_ES1_0:
case DRA752_ES1_1:
if (addr == OMAP_HSMMC1_BASE)
return &am57x_es1_1_mmc1_fixups;
else
return &am57x_es1_1_mmc23_fixups;
default:
return NULL;
}
}
#endif
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
int spl_start_uboot(void)
{
/* break into full u-boot on 'c' */
if (serial_tstc() && serial_getc() == 'c')
return 1;
#ifdef CONFIG_SPL_ENV_SUPPORT
env_init();
env_load();
if (env_get_yesno("boot_os") != 1)
return 1;
#endif
return 0;
}
#endif
#ifdef CONFIG_DRIVER_TI_CPSW
/* Delay value to add to calibrated value */
#define RGMII0_TXCTL_DLY_VAL ((0x3 << 5) + 0x8)
#define RGMII0_TXD0_DLY_VAL ((0x3 << 5) + 0x8)
#define RGMII0_TXD1_DLY_VAL ((0x3 << 5) + 0x2)
#define RGMII0_TXD2_DLY_VAL ((0x4 << 5) + 0x0)
#define RGMII0_TXD3_DLY_VAL ((0x4 << 5) + 0x0)
#define VIN2A_D13_DLY_VAL ((0x3 << 5) + 0x8)
#define VIN2A_D17_DLY_VAL ((0x3 << 5) + 0x8)
#define VIN2A_D16_DLY_VAL ((0x3 << 5) + 0x2)
#define VIN2A_D15_DLY_VAL ((0x4 << 5) + 0x0)
#define VIN2A_D14_DLY_VAL ((0x4 << 5) + 0x0)
static void cpsw_control(int enabled)
{
/* VTP can be added here */
}
static struct cpsw_slave_data cpsw_slaves[] = {
{
.slave_reg_ofs = 0x208,
.sliver_reg_ofs = 0xd80,
.phy_addr = 1,
},
{
.slave_reg_ofs = 0x308,
.sliver_reg_ofs = 0xdc0,
.phy_addr = 2,
},
};
static struct cpsw_platform_data cpsw_data = {
.mdio_base = CPSW_MDIO_BASE,
.cpsw_base = CPSW_BASE,
.mdio_div = 0xff,
.channels = 8,
.cpdma_reg_ofs = 0x800,
.slaves = 1,
.slave_data = cpsw_slaves,
.ale_reg_ofs = 0xd00,
.ale_entries = 1024,
.host_port_reg_ofs = 0x108,
.hw_stats_reg_ofs = 0x900,
.bd_ram_ofs = 0x2000,
.mac_control = (1 << 5),
.control = cpsw_control,
.host_port_num = 0,
.version = CPSW_CTRL_VERSION_2,
};
static u64 mac_to_u64(u8 mac[6])
{
int i;
u64 addr = 0;
for (i = 0; i < 6; i++) {
addr <<= 8;
addr |= mac[i];
}
return addr;
}
static void u64_to_mac(u64 addr, u8 mac[6])
{
mac[5] = addr;
mac[4] = addr >> 8;
mac[3] = addr >> 16;
mac[2] = addr >> 24;
mac[1] = addr >> 32;
mac[0] = addr >> 40;
}
int board_eth_init(bd_t *bis)
{
return -1;
int ret;
uint8_t mac_addr[6];
uint32_t mac_hi, mac_lo;
uint32_t ctrl_val;
int i;
u64 mac1, mac2;
u8 mac_addr1[6], mac_addr2[6];
int num_macs;
/* try reading mac address from efuse */
mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
mac_addr[1] = (mac_hi & 0xFF00) >> 8;
mac_addr[2] = mac_hi & 0xFF;
mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
mac_addr[4] = (mac_lo & 0xFF00) >> 8;
mac_addr[5] = mac_lo & 0xFF;
if (!env_get("ethaddr")) {
printf("<ethaddr> not set. Validating first E-fuse MAC\n");
if (is_valid_ethaddr(mac_addr))
eth_env_set_enetaddr("ethaddr", mac_addr);
}
mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
mac_addr[1] = (mac_hi & 0xFF00) >> 8;
mac_addr[2] = mac_hi & 0xFF;
mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
mac_addr[4] = (mac_lo & 0xFF00) >> 8;
mac_addr[5] = mac_lo & 0xFF;
if (!env_get("eth1addr")) {
if (is_valid_ethaddr(mac_addr))
eth_env_set_enetaddr("eth1addr", mac_addr);
}
ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
ctrl_val |= 0x22;
writel(ctrl_val, (*ctrl)->control_core_control_io1);
/* The phy address for the AM57xx IDK are different than x15 */
if (board_is_am572x_idk() || board_is_am571x_idk() ||
board_is_am574x_idk()) {
cpsw_data.slave_data[0].phy_addr = 0;
cpsw_data.slave_data[1].phy_addr = 1;
}
ret = cpsw_register(&cpsw_data);
if (ret < 0)
printf("Error %d registering CPSW switch\n", ret);
/*
* Export any Ethernet MAC addresses from EEPROM.
* On AM57xx the 2 MAC addresses define the address range
*/
board_ti_get_eth_mac_addr(0, mac_addr1);
board_ti_get_eth_mac_addr(1, mac_addr2);
if (is_valid_ethaddr(mac_addr1) && is_valid_ethaddr(mac_addr2)) {
mac1 = mac_to_u64(mac_addr1);
mac2 = mac_to_u64(mac_addr2);
/* must contain an address range */
num_macs = mac2 - mac1 + 1;
/* <= 50 to protect against user programming error */
if (num_macs > 0 && num_macs <= 50) {
for (i = 0; i < num_macs; i++) {
u64_to_mac(mac1 + i, mac_addr);
if (is_valid_ethaddr(mac_addr)) {
eth_env_set_enetaddr_by_index("eth",
i + 2,
mac_addr);
}
}
}
}
return ret;
}
#endif
#ifdef CONFIG_BOARD_EARLY_INIT_F
int board_early_init_f(void)
{
return 0;
}
#endif
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
return 0;
}
#endif
#ifdef CONFIG_SPL_LOAD_FIT
int board_fit_config_name_match(const char *name)
{
if (!strcmp(name, STR_BOARD_NAME))
return 0;
return -1;
}
#endif
#ifdef CONFIG_TI_SECURE_DEVICE
void board_fit_image_post_process(void **p_image, size_t *p_size)
{
secure_boot_verify_image(p_image, p_size);
}
void board_tee_image_process(ulong tee_image, size_t tee_size)
{
secure_tee_install((u32)tee_image);
}
#if CONFIG_IS_ENABLED(FASTBOOT) && !CONFIG_IS_ENABLED(ENV_IS_NOWHERE)
int fastboot_set_reboot_flag(void)
{
printf("Setting reboot to fastboot flag ...\n");
env_set("dofastboot", "1");
env_save();
return 0;
}
#endif
U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process);
#endif
diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c
index dcddd4f..a473b89 100644
--- a/board/ti/am57xx/board.c
+++ b/board/ti/am57xx/board.c
@@ -34,6 +34,7 @@
#include "../common/board_detect.h"
#include "mux_data.h"
+#define STR_BOARD_NAME "**Custom**"
#define board_is_x15() board_ti_is("BBRDX15_")
#define board_is_x15_revb1() (board_ti_is("BBRDX15_") && \
!strncmp("B.10", board_ti_get_rev(), 3))
@@ -76,231 +77,128 @@ DECLARE_GLOBAL_DATA_PTR;
#define TPS65903X_PAD2_POWERHOLD_MASK 0x20
const struct omap_sysinfo sysinfo = {
- "Board: UNKNOWN(BeagleBoard X15?) REV UNKNOWN\n"
+ "Board: custom\n"
};
-static const struct dmm_lisa_map_regs beagle_x15_lisa_regs = {
- .dmm_lisa_map_3 = 0x80740300,
- .is_ma_present = 0x1
-};
-
-static const struct dmm_lisa_map_regs am571x_idk_lisa_regs = {
- .dmm_lisa_map_3 = 0x80640100,
- .is_ma_present = 0x1
-};
-
-static const struct dmm_lisa_map_regs am574x_idk_lisa_regs = {
- .dmm_lisa_map_2 = 0xc0600200,
- .dmm_lisa_map_3 = 0x80600100,
- .is_ma_present = 0x1
+static const struct dmm_lisa_map_regs AM57xx_533MHZ_dmm_regs = {
+ .dmm_lisa_map_0 = 0x00000000,
+ .dmm_lisa_map_1 = 0x00000000,
+ .dmm_lisa_map_2 = 0x80640300,
+ .dmm_lisa_map_3 = 0xFF020100,
+ .is_ma_present = 0x1
};
void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
{
- if (board_is_am571x_idk())
- *dmm_lisa_regs = &am571x_idk_lisa_regs;
- else if (board_is_am574x_idk())
- *dmm_lisa_regs = &am574x_idk_lisa_regs;
- else
- *dmm_lisa_regs = &beagle_x15_lisa_regs;
+ *dmm_lisa_regs = &AM57xx_533MHZ_dmm_regs;
}
-static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = {
- .sdram_config_init = 0x61851b32,
- .sdram_config = 0x61851b32,
- .sdram_config2 = 0x08000000,
- .ref_ctrl = 0x000040F1,
- .ref_ctrl_final = 0x00001035,
- .sdram_tim1 = 0xcccf36ab,
- .sdram_tim2 = 0x308f7fda,
- .sdram_tim3 = 0x409f88a8,
- .read_idle_ctrl = 0x00050000,
- .zq_config = 0x5007190b,
- .temp_alert_config = 0x00000000,
- .emif_ddr_phy_ctlr_1_init = 0x0024400b,
- .emif_ddr_phy_ctlr_1 = 0x0e24400b,
- .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
- .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
- .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
- .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
- .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
- .emif_rd_wr_lvl_rmp_win = 0x00000000,
- .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
- .emif_rd_wr_lvl_ctl = 0x00000000,
- .emif_rd_wr_exec_thresh = 0x00000305
+static const struct emif_regs AM57xx_533MHZ_emif_regs = {
+ .sdram_config_init = 0x61851AB2,
+ .sdram_config = 0x61851AB2,
+ .sdram_config2 = 0x00000000,
+ .ref_ctrl = 0x00004111,
+ .ref_ctrl_final = 0x0000081E,
+ .sdram_tim1 = 0xCEEF2663,
+ .sdram_tim2 = 0x305A7FDA,
+ .sdram_tim3 = 0x407F8558,
+ .read_idle_ctrl = 0x00050000,
+ .zq_config = 0x5007190B,
+ .temp_alert_config = 0x00000000,
+ .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
+ .emif_rd_wr_lvl_ctl = 0x00000000,
+ .emif_ddr_phy_ctlr_1_init = 0x0024400B,
+ .emif_ddr_phy_ctlr_1 = 0x0E24400B,
+ .emif_rd_wr_exec_thresh = 0x00000305
};
/* Ext phy ctrl regs 1-35 */
-static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = {
- 0x10040100,
- 0x00910091,
- 0x00950095,
- 0x009B009B,
- 0x009E009E,
- 0x00980098,
- 0x00340034,
- 0x00350035,
- 0x00340034,
- 0x00310031,
- 0x00340034,
- 0x007F007F,
- 0x007F007F,
- 0x007F007F,
- 0x007F007F,
- 0x007F007F,
- 0x00480048,
- 0x004A004A,
- 0x00520052,
- 0x00550055,
- 0x00500050,
- 0x00000000,
- 0x00600020,
- 0x40011080,
- 0x08102040,
- 0x0,
- 0x0,
- 0x0,
- 0x0,
- 0x0,
- 0x0,
- 0x0,
- 0x0,
- 0x0,
- 0x0
-};
-
-static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = {
- .sdram_config_init = 0x61851b32,
- .sdram_config = 0x61851b32,
- .sdram_config2 = 0x08000000,
- .ref_ctrl = 0x000040F1,
- .ref_ctrl_final = 0x00001035,
- .sdram_tim1 = 0xcccf36b3,
- .sdram_tim2 = 0x308f7fda,
- .sdram_tim3 = 0x407f88a8,
- .read_idle_ctrl = 0x00050000,
- .zq_config = 0x5007190b,
- .temp_alert_config = 0x00000000,
- .emif_ddr_phy_ctlr_1_init = 0x0024400b,
- .emif_ddr_phy_ctlr_1 = 0x0e24400b,
- .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
- .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
- .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
- .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
- .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
- .emif_rd_wr_lvl_rmp_win = 0x00000000,
- .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
- .emif_rd_wr_lvl_ctl = 0x00000000,
- .emif_rd_wr_exec_thresh = 0x00000305
-};
-
-static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = {
- 0x10040100,
- 0x00910091,
- 0x00950095,
- 0x009B009B,
- 0x009E009E,
- 0x00980098,
- 0x00340034,
- 0x00350035,
- 0x00340034,
- 0x00310031,
- 0x00340034,
- 0x007F007F,
- 0x007F007F,
- 0x007F007F,
- 0x007F007F,
- 0x007F007F,
- 0x00480048,
- 0x004A004A,
- 0x00520052,
- 0x00550055,
- 0x00500050,
- 0x00000000,
- 0x00600020,
- 0x40011080,
- 0x08102040,
- 0x0,
- 0x0,
- 0x0,
- 0x0,
- 0x0,
- 0x0,
- 0x0,
- 0x0,
- 0x0,
- 0x0
-};
-
-static const struct emif_regs am571x_emif1_ddr3_666mhz_emif_regs = {
- .sdram_config_init = 0x61863332,
- .sdram_config = 0x61863332,
- .sdram_config2 = 0x08000000,
- .ref_ctrl = 0x0000514d,
- .ref_ctrl_final = 0x0000144a,
- .sdram_tim1 = 0xd333887c,
- .sdram_tim2 = 0x30b37fe3,
- .sdram_tim3 = 0x409f8ad8,
- .read_idle_ctrl = 0x00050000,
- .zq_config = 0x5007190b,
- .temp_alert_config = 0x00000000,
- .emif_ddr_phy_ctlr_1_init = 0x0024400f,
- .emif_ddr_phy_ctlr_1 = 0x0e24400f,
- .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
- .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
- .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
- .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
- .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
- .emif_rd_wr_lvl_rmp_win = 0x00000000,
- .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
- .emif_rd_wr_lvl_ctl = 0x00000000,
- .emif_rd_wr_exec_thresh = 0x00000305
+static const u32 am57xx_533MHZ_emif1_ddr3_ext_phy_ctrl_const_regs[] = {
+ 0x04040100, // EMIF1_EXT_PHY_CTRL_1
+ 0x006B0083, // EMIF1_EXT_PHY_CTRL_2
+ 0x006B0075, // EMIF1_EXT_PHY_CTRL_3
+ 0x006B0088, // EMIF1_EXT_PHY_CTRL_4
+ 0x006B0072, // EMIF1_EXT_PHY_CTRL_5
+ 0x006B006B, // EMIF1_EXT_PHY_CTRL_6
+ 0x00320032, // EMIF1_EXT_PHY_CTRL_7
+ 0x00320032, // EMIF1_EXT_PHY_CTRL_8
+ 0x00320032, // EMIF1_EXT_PHY_CTRL_9
+ 0x00320032, // EMIF1_EXT_PHY_CTRL_10
+ 0x00320032, // EMIF1_EXT_PHY_CTRL_11
+ 0x00600065, // EMIF1_EXT_PHY_CTRL_12
+ 0x00600056, // EMIF1_EXT_PHY_CTRL_13
+ 0x0060006A, // EMIF1_EXT_PHY_CTRL_14
+ 0x00600059, // EMIF1_EXT_PHY_CTRL_15
+ 0x00600060, // EMIF1_EXT_PHY_CTRL_16
+ 0x00400045, // EMIF1_EXT_PHY_CTRL_17
+ 0x00400036, // EMIF1_EXT_PHY_CTRL_18
+ 0x0040004A, // EMIF1_EXT_PHY_CTRL_19
+ 0x00400039, // EMIF1_EXT_PHY_CTRL_20
+ 0x00400040, // EMIF1_EXT_PHY_CTRL_21
+ 0x00800080, // EMIF1_EXT_PHY_CTRL_22
+ 0x00800080, // EMIF1_EXT_PHY_CTRL_23
+ 0x40010080, // EMIF1_EXT_PHY_CTRL_24
+ 0x08102040, // EMIF1_EXT_PHY_CTRL_25
+ 0x00000073, // EMIF1_EXT_PHY_CTRL_26
+ 0x00000065, // EMIF1_EXT_PHY_CTRL_27
+ 0x00000078, // EMIF1_EXT_PHY_CTRL_28
+ 0x00000062, // EMIF1_EXT_PHY_CTRL_29
+ 0x00000000, // EMIF1_EXT_PHY_CTRL_30
+ 0x00000035, // EMIF1_EXT_PHY_CTRL_31
+ 0x00000026, // EMIF1_EXT_PHY_CTRL_32
+ 0x0000003A, // EMIF1_EXT_PHY_CTRL_33
+ 0x00000029, // EMIF1_EXT_PHY_CTRL_34
+ 0x00000000, // EMIF1_EXT_PHY_CTRL_35
+ 0x00000077 // EMIF1_EXT_PHY_CTRL_36
};
-static const struct emif_regs am574x_emif1_ddr3_666mhz_emif_ecc_regs = {
- .sdram_config_init = 0x61863332,
- .sdram_config = 0x61863332,
- .sdram_config2 = 0x08000000,
- .ref_ctrl = 0x0000514d,
- .ref_ctrl_final = 0x0000144a,
- .sdram_tim1 = 0xd333887c,
- .sdram_tim2 = 0x30b37fe3,
- .sdram_tim3 = 0x409f8ad8,
- .read_idle_ctrl = 0x00050000,
- .zq_config = 0x5007190b,
- .temp_alert_config = 0x00000000,
- .emif_ddr_phy_ctlr_1_init = 0x0024400f,
- .emif_ddr_phy_ctlr_1 = 0x0e24400f,
- .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
- .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
- .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
- .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
- .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
- .emif_rd_wr_lvl_rmp_win = 0x00000000,
- .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
- .emif_rd_wr_lvl_ctl = 0x00000000,
- .emif_rd_wr_exec_thresh = 0x00000305,
- .emif_ecc_ctrl_reg = 0xD0000001,
- .emif_ecc_address_range_1 = 0x3FFF0000,
- .emif_ecc_address_range_2 = 0x00000000
+static const u32 am57xx_533MHZ_emif2_ddr3_ext_phy_ctrl_const_regs[] = {
+ 0x04040100, // EMIF2_EXT_PHY_CTRL_1
+ 0x006B0083, // EMIF2_EXT_PHY_CTRL_2
+ 0x006B0077, // EMIF2_EXT_PHY_CTRL_3
+ 0x006B0088, // EMIF2_EXT_PHY_CTRL_4
+ 0x006B0075, // EMIF2_EXT_PHY_CTRL_5
+ 0x006B006B, // EMIF2_EXT_PHY_CTRL_6
+ 0x00320032, // EMIF2_EXT_PHY_CTRL_7
+ 0x00320032, // EMIF2_EXT_PHY_CTRL_8
+ 0x00320032, // EMIF2_EXT_PHY_CTRL_9
+ 0x00320032, // EMIF2_EXT_PHY_CTRL_10
+ 0x00320032, // EMIF2_EXT_PHY_CTRL_11
+ 0x00600062, // EMIF2_EXT_PHY_CTRL_12
+ 0x00600054, // EMIF2_EXT_PHY_CTRL_13
+ 0x00600068, // EMIF2_EXT_PHY_CTRL_14
+ 0x00600056, // EMIF2_EXT_PHY_CTRL_15
+ 0x00600060, // EMIF2_EXT_PHY_CTRL_16
+ 0x00400042, // EMIF2_EXT_PHY_CTRL_17
+ 0x00400034, // EMIF2_EXT_PHY_CTRL_18
+ 0x00400048, // EMIF2_EXT_PHY_CTRL_19
+ 0x00400036, // EMIF2_EXT_PHY_CTRL_20
+ 0x00400040, // EMIF2_EXT_PHY_CTRL_21
+ 0x00800080, // EMIF2_EXT_PHY_CTRL_22
+ 0x00800080, // EMIF2_EXT_PHY_CTRL_23
+ 0x40010080, // EMIF2_EXT_PHY_CTRL_24
+ 0x08102040, // EMIF2_EXT_PHY_CTRL_25
+ 0x00000073, // EMIF2_EXT_PHY_CTRL_26
+ 0x00000067, // EMIF2_EXT_PHY_CTRL_27
+ 0x00000078, // EMIF2_EXT_PHY_CTRL_28
+ 0x00000065, // EMIF2_EXT_PHY_CTRL_29
+ 0x00000000, // EMIF2_EXT_PHY_CTRL_30
+ 0x00000032, // EMIF2_EXT_PHY_CTRL_31
+ 0x00000024, // EMIF2_EXT_PHY_CTRL_32
+ 0x00000038, // EMIF2_EXT_PHY_CTRL_33
+ 0x00000026, // EMIF2_EXT_PHY_CTRL_34
+ 0x00000000, // EMIF2_EXT_PHY_CTRL_35
+ 0x00000077 // EMIF2_EXT_PHY_CTRL_36
};
void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
{
switch (emif_nr) {
case 1:
- if (board_is_am571x_idk())
- *regs = &am571x_emif1_ddr3_666mhz_emif_regs;
- else if (board_is_am574x_idk())
- *regs = &am574x_emif1_ddr3_666mhz_emif_ecc_regs;
- else
- *regs = &beagle_x15_emif1_ddr3_532mhz_emif_regs;
+ *regs = &AM57xx_533MHZ_emif_regs;
break;
case 2:
- if (board_is_am574x_idk())
- *regs = &am571x_emif1_ddr3_666mhz_emif_regs;
- else
- *regs = &beagle_x15_emif2_ddr3_532mhz_emif_regs;
+ *regs = &AM57xx_533MHZ_emif_regs;
break;
}
}
@@ -309,12 +207,12 @@ void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size)
{
switch (emif_nr) {
case 1:
- *regs = beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs;
- *size = ARRAY_SIZE(beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs);
+ *regs = am57xx_533MHZ_emif1_ddr3_ext_phy_ctrl_const_regs;
+ *size = ARRAY_SIZE(am57xx_533MHZ_emif1_ddr3_ext_phy_ctrl_const_regs);
break;
case 2:
- *regs = beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs;
- *size = ARRAY_SIZE(beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs);
+ *regs = am57xx_533MHZ_emif2_ddr3_ext_phy_ctrl_const_regs;
+ *size = ARRAY_SIZE(am57xx_533MHZ_emif2_ddr3_ext_phy_ctrl_const_regs);
break;
}
}
@@ -367,102 +265,6 @@ struct vcores_data beagle_x15_volts = {
.iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
};
-struct vcores_data am572x_idk_volts = {
- .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
- .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
- .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
- .mpu.addr = TPS659038_REG_ADDR_SMPS12,
- .mpu.pmic = &tps659038,
- .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
-
- .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
- .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
- .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
- .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
- .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
- .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
- .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
- .eve.addr = TPS659038_REG_ADDR_SMPS45,
- .eve.pmic = &tps659038,
- .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
-
- .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
- .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
- .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
- .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
- .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
- .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
- .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
- .gpu.addr = TPS659038_REG_ADDR_SMPS6,
- .gpu.pmic = &tps659038,
- .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
-
- .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
- .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
- .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
- .core.addr = TPS659038_REG_ADDR_SMPS7,
- .core.pmic = &tps659038,
-
- .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
- .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
- .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
- .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
- .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
- .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
- .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
- .iva.addr = TPS659038_REG_ADDR_SMPS8,
- .iva.pmic = &tps659038,
- .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
-};
-
-struct vcores_data am571x_idk_volts = {
- .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
- .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
- .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
- .mpu.addr = TPS659038_REG_ADDR_SMPS12,
- .mpu.pmic = &tps659038,
- .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
-
- .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
- .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
- .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
- .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
- .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
- .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
- .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
- .eve.addr = TPS659038_REG_ADDR_SMPS45,
- .eve.pmic = &tps659038,
- .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
-
- .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
- .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
- .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
- .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
- .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
- .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
- .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
- .gpu.addr = TPS659038_REG_ADDR_SMPS6,
- .gpu.pmic = &tps659038,
- .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
-
- .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
- .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
- .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
- .core.addr = TPS659038_REG_ADDR_SMPS7,
- .core.pmic = &tps659038,
-
- .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
- .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
- .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
- .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
- .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
- .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
- .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
- .iva.addr = TPS659038_REG_ADDR_SMPS45,
- .iva.pmic = &tps659038,
- .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
-};
-
int get_voltrail_opp(int rail_offset)
{
int opp;
@@ -496,92 +298,23 @@ int get_voltrail_opp(int rail_offset)
static inline void setup_board_eeprom_env(void) { }
/* Override function to read eeprom information */
-void do_board_detect(void)
-{
- int rc;
-
- rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
- CONFIG_EEPROM_CHIP_ADDRESS);
- if (rc)
- printf("ti_i2c_eeprom_init failed %d\n", rc);
-}
+void do_board_detect(void) { }
#else /* CONFIG_SPL_BUILD */
/* Override function to read eeprom information: actual i2c read done by SPL*/
-void do_board_detect(void)
-{
- char *bname = NULL;
- int rc;
-
- rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
- CONFIG_EEPROM_CHIP_ADDRESS);
- if (rc)
- printf("ti_i2c_eeprom_init failed %d\n", rc);
-
- if (board_is_x15())
- bname = "BeagleBoard X15";
- else if (board_is_am572x_evm())
- bname = "AM572x EVM";
- else if (board_is_am574x_idk())
- bname = "AM574x IDK";
- else if (board_is_am572x_idk())
- bname = "AM572x IDK";
- else if (board_is_am571x_idk())
- bname = "AM571x IDK";
-
- if (bname)
- snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN,
- "Board: %s REV %s\n", bname, board_ti_get_rev());
-}
+void do_board_detect(void) { }
static void setup_board_eeprom_env(void)
{
- char *name = "beagle_x15";
- int rc;
-
- rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
- CONFIG_EEPROM_CHIP_ADDRESS);
- if (rc)
- goto invalid_eeprom;
-
- if (board_is_x15()) {
- if (board_is_x15_revb1())
- name = "beagle_x15_revb1";
- else if (board_is_x15_revc())
- name = "beagle_x15_revc";
- else
- name = "beagle_x15";
- } else if (board_is_am572x_evm()) {
- if (board_is_am572x_evm_reva3())
- name = "am57xx_evm_reva3";
- else
- name = "am57xx_evm";
- } else if (board_is_am574x_idk()) {
- name = "am574x_idk";
- } else if (board_is_am572x_idk()) {
- name = "am572x_idk";
- } else if (board_is_am571x_idk()) {
- name = "am571x_idk";
- } else {
- printf("Unidentified board claims %s in eeprom header\n",
- board_ti_get_name());
- }
-
-invalid_eeprom:
- set_board_info_env(name);
+ set_board_info_env(STR_BOARD_NAME);
}
#endif /* CONFIG_SPL_BUILD */
void vcores_init(void)
{
- if (board_is_am572x_idk() || board_is_am574x_idk())
- *omap_vcores = &am572x_idk_volts;
- else if (board_is_am571x_idk())
- *omap_vcores = &am571x_idk_volts;
- else
- *omap_vcores = &beagle_x15_volts;
+ *omap_vcores = &beagle_x15_volts;
}
void hw_data_init(void)
@@ -596,21 +329,6 @@ void hw_data_init(void)
*ctrl = &dra7xx_ctrl;
}
-bool am571x_idk_needs_lcd(void)
-{
- bool needs_lcd;
-
- gpio_request(GPIO_ETH_LCD, "nLCD_Detect");
- if (gpio_get_value(GPIO_ETH_LCD))
- needs_lcd = false;
- else
- needs_lcd = true;
-
- gpio_free(GPIO_ETH_LCD);
-
- return needs_lcd;
-}
-
int board_init(void)
{
gpmc_init();
@@ -619,71 +337,6 @@ int board_init(void)
return 0;
}
-void am57x_idk_lcd_detect(void)
-{
- int r = -ENODEV;
- char *idk_lcd = "no";
- struct udevice *dev;
-
- /* Only valid for IDKs */
- if (board_is_x15() || board_is_am572x_evm())
- return;
-
- /* Only AM571x IDK has gpio control detect.. so check that */
- if (board_is_am571x_idk() && !am571x_idk_needs_lcd())
- goto out;
-
- r = i2c_get_chip_for_busnum(OSD_TS_FT_BUS_ADDRESS,
- OSD_TS_FT_CHIP_ADDRESS, 1, &dev);
- if (r) {
- printf("%s: Failed to get I2C device %d/%d (ret %d)\n",
- __func__, OSD_TS_FT_BUS_ADDRESS, OSD_TS_FT_CHIP_ADDRESS,
- r);
- /* AM572x IDK has no explicit settings for optional LCD kit */
- if (board_is_am571x_idk())
- printf("%s: Touch screen detect failed: %d!\n",
- __func__, r);
- goto out;
- }
-
- /* Read FT ID */
- r = dm_i2c_reg_read(dev, OSD_TS_FT_REG_ID);
- if (r < 0) {
- printf("%s: Touch screen ID read %d:0x%02x[0x%02x] failed:%d\n",
- __func__, OSD_TS_FT_BUS_ADDRESS, OSD_TS_FT_CHIP_ADDRESS,
- OSD_TS_FT_REG_ID, r);
- goto out;
- }
-
- switch (r) {
- case OSD_TS_FT_ID_5606:
- idk_lcd = "osd101t2045";
- break;
- case OSD_TS_FT_ID_5x46:
- idk_lcd = "osd101t2587";
- break;
- default:
- printf("%s: Unidentifed Touch screen ID 0x%02x\n",
- __func__, r);
- /* we will let default be "no lcd" */
- }
-out:
- env_set("idk_lcd", idk_lcd);
-
- /*
- * On AM571x_IDK, no Display with J51 set to LCD is considered as an
- * invalid configuration and we prevent boot to get user attention.
- */
- if (board_is_am571x_idk() && am571x_idk_needs_lcd() &&
- !strncmp(idk_lcd, "no", 2)) {
- printf("%s: Invalid HW configuration: display not detected/supported but J51 is set. Remove J51 to boot without display.\n",
- __func__);
- hang();
- }
-
- return;
-}
-
#if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
static int device_okay(const char *path)
{
@@ -730,7 +383,6 @@ int board_late_init(void)
omap_die_id_serial();
omap_set_fastboot_vars();
- am57x_idk_lcd_detect();
#if !defined(CONFIG_SPL_BUILD)
board_ti_set_ethaddr(2);
@@ -759,34 +411,16 @@ void recalibrate_iodelay(void)
int pconf_sz, iod_sz, delta_iod_sz = 0;
int ret;
- if (board_is_am572x_idk()) {
- pconf = core_padconf_array_essential_am572x_idk;
- pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am572x_idk);
- iod = iodelay_cfg_array_am572x_idk;
- iod_sz = ARRAY_SIZE(iodelay_cfg_array_am572x_idk);
- } else if (board_is_am574x_idk()) {
- pconf = core_padconf_array_essential_am574x_idk;
- pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am574x_idk);
- iod = iodelay_cfg_array_am574x_idk;
- iod_sz = ARRAY_SIZE(iodelay_cfg_array_am574x_idk);
- } else if (board_is_am571x_idk()) {
- pconf = core_padconf_array_essential_am571x_idk;
- pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am571x_idk);
- iod = iodelay_cfg_array_am571x_idk;
- iod_sz = ARRAY_SIZE(iodelay_cfg_array_am571x_idk);
+ pconf = core_padconf_array_essential_custom;
+ pconf_sz = ARRAY_SIZE(core_padconf_array_essential_custom);
+
+ if (omap_revision() == DRA752_ES1_1) {
+ iod = iodelay_cfg_array_custom_sr1_1;
+ iod_sz = ARRAY_SIZE(iodelay_cfg_array_custom_sr1_1);
} else {
- /* Common for X15/GPEVM */
- pconf = core_padconf_array_essential_x15;
- pconf_sz = ARRAY_SIZE(core_padconf_array_essential_x15);
- /* There never was an SR1.0 X15.. So.. */
- if (omap_revision() == DRA752_ES1_1) {
- iod = iodelay_cfg_array_x15_sr1_1;
- iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15_sr1_1);
- } else {
- /* Since full production should switch to SR2.0 */
- iod = iodelay_cfg_array_x15_sr2_0;
- iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15_sr2_0);
- }
+ /* Since full production should switch to SR2.0 */
+ iod = iodelay_cfg_array_custom_sr2_0;
+ iod_sz = ARRAY_SIZE(iodelay_cfg_array_custom_sr2_0);
}
/* Setup I/O isolation */
@@ -797,33 +431,6 @@ void recalibrate_iodelay(void)
/* Do the muxing here */
do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
- /* Now do the weird minor deltas that should be safe */
- if (board_is_x15() || board_is_am572x_evm()) {
- if (board_is_x15_revb1() || board_is_am572x_evm_reva3() ||
- board_is_x15_revc()) {
- pconf = core_padconf_array_delta_x15_sr2_0;
- pconf_sz = ARRAY_SIZE(core_padconf_array_delta_x15_sr2_0);
- } else {
- pconf = core_padconf_array_delta_x15_sr1_1;
- pconf_sz = ARRAY_SIZE(core_padconf_array_delta_x15_sr1_1);
- }
- do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
- }
-
- if (board_is_am571x_idk()) {
- if (am571x_idk_needs_lcd()) {
- pconf = core_padconf_array_vout_am571x_idk;
- pconf_sz = ARRAY_SIZE(core_padconf_array_vout_am571x_idk);
- delta_iod = iodelay_cfg_array_am571x_idk_4port;
- delta_iod_sz = ARRAY_SIZE(iodelay_cfg_array_am571x_idk_4port);
-
- } else {
- pconf = core_padconf_array_icss1eth_am571x_idk;
- pconf_sz = ARRAY_SIZE(core_padconf_array_icss1eth_am571x_idk);
- }
- do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
- }
-
/* Setup IOdelay configuration */
ret = do_set_iodelay((*ctrl)->iodelay_config_base, iod, iod_sz);
if (delta_iod_sz)
@@ -968,6 +575,7 @@ static void u64_to_mac(u64 addr, u8 mac[6])
int board_eth_init(bd_t *bis)
{
+ return -1;
int ret;
uint8_t mac_addr[6];
uint32_t mac_hi, mac_lo;
@@ -1054,19 +662,8 @@ int board_eth_init(bd_t *bis)
#endif
#ifdef CONFIG_BOARD_EARLY_INIT_F
-/* VTT regulator enable */
-static inline void vtt_regulator_enable(void)
-{
- if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
- return;
-
- gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
- gpio_direction_output(GPIO_DDR_VTT_EN, 1);
-}
-
int board_early_init_f(void)
{
- vtt_regulator_enable();
return 0;
}
#endif
@@ -1083,26 +680,8 @@ int ft_board_setup(void *blob, bd_t *bd)
#ifdef CONFIG_SPL_LOAD_FIT
int board_fit_config_name_match(const char *name)
{
- if (board_is_x15()) {
- if (board_is_x15_revb1()) {
- if (!strcmp(name, "am57xx-beagle-x15-revb1"))
- return 0;
- } else if (board_is_x15_revc()) {
- if (!strcmp(name, "am57xx-beagle-x15-revc"))
- return 0;
- } else if (!strcmp(name, "am57xx-beagle-x15")) {
- return 0;
- }
- } else if (board_is_am572x_evm() &&
- !strcmp(name, "am57xx-beagle-x15")) {
+ if (!strcmp(name, STR_BOARD_NAME))
return 0;
- } else if (board_is_am572x_idk() && !strcmp(name, "am572x-idk")) {
- return 0;
- } else if (board_is_am574x_idk() && !strcmp(name, "am574x-idk")) {
- return 0;
- } else if (board_is_am571x_idk() && !strcmp(name, "am571x-idk")) {
- return 0;
- }
return -1;
}
#
# Automatically generated file; DO NOT EDIT.
# U-Boot 2019.01 Configuration
#
CONFIG_CREATE_ARCH_SYMLINK=y
# CONFIG_ARC is not set
CONFIG_ARM=y
# CONFIG_M68K is not set
# CONFIG_MICROBLAZE is not set
# CONFIG_MIPS is not set
# CONFIG_NDS32 is not set
# CONFIG_NIOS2 is not set
# CONFIG_PPC is not set
# CONFIG_RISCV is not set
# CONFIG_SANDBOX is not set
# CONFIG_SH is not set
# CONFIG_X86 is not set
# CONFIG_XTENSA is not set
CONFIG_SYS_ARCH="arm"
CONFIG_SYS_CPU="armv7"
CONFIG_SYS_SOC="omap5"
CONFIG_SYS_VENDOR="ti"
CONFIG_SYS_BOARD="am57xx"
CONFIG_SYS_CONFIG_NAME="am57xx_evm"
#
# ARM architecture
#
CONFIG_HAS_VBAR=y
CONFIG_HAS_THUMB2=y
CONFIG_ARM_ASM_UNIFIED=y
CONFIG_SYS_ARM_CACHE_CP15=y
CONFIG_SYS_ARM_MMU=y
# CONFIG_SYS_ARM_MPU is not set
CONFIG_ARM_ERRATA_798870=y
CONFIG_ARM_CORTEX_A15_CVE_2017_5715=y
CONFIG_CPU_V7A=y
CONFIG_SYS_ARM_ARCH=7
CONFIG_SYS_CACHE_SHIFT_6=y
CONFIG_SYS_CACHELINE_SIZE=64
# CONFIG_SYS_ARCH_TIMER is not set
# CONFIG_ARM_SMCCC is not set
# CONFIG_SEMIHOSTING is not set
CONFIG_SYS_THUMB_BUILD=y
CONFIG_SPL_SYS_THUMB_BUILD=y
# CONFIG_SYS_L2CACHE_OFF is not set
# CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK is not set
CONFIG_USE_ARCH_MEMCPY=y
CONFIG_SPL_USE_ARCH_MEMCPY=y
CONFIG_USE_ARCH_MEMSET=y
CONFIG_SPL_USE_ARCH_MEMSET=y
# CONFIG_ARM64_SUPPORT_AARCH32 is not set
# CONFIG_ARCH_AT91 is not set
# CONFIG_TARGET_EDB93XX is not set
# CONFIG_TARGET_ASPENITE is not set
# CONFIG_TARGET_GPLUGD is not set
# CONFIG_ARCH_DAVINCI is not set
# CONFIG_KIRKWOOD is not set
# CONFIG_ARCH_MVEBU is not set
# CONFIG_TARGET_APF27 is not set
# CONFIG_ORION5X is not set
# CONFIG_TARGET_SPEAR300 is not set
# CONFIG_TARGET_SPEAR310 is not set
# CONFIG_TARGET_SPEAR320 is not set
# CONFIG_TARGET_SPEAR600 is not set
# CONFIG_TARGET_STV0991 is not set
# CONFIG_TARGET_X600 is not set
# CONFIG_TARGET_WOODBURN is not set
# CONFIG_TARGET_WOODBURN_SD is not set
# CONFIG_TARGET_FLEA3 is not set
# CONFIG_TARGET_MX35PDK is not set
# CONFIG_ARCH_BCM283X is not set
# CONFIG_ARCH_BCM6858 is not set
# CONFIG_TARGET_VEXPRESS_CA15_TC2 is not set
# CONFIG_ARCH_BCMSTB is not set
# CONFIG_TARGET_VEXPRESS_CA5X2 is not set
# CONFIG_TARGET_VEXPRESS_CA9X4 is not set
# CONFIG_TARGET_BCM23550_W1D is not set
# CONFIG_TARGET_BCM28155_AP is not set
# CONFIG_TARGET_BCMCYGNUS is not set
# CONFIG_TARGET_BCMNSP is not set
# CONFIG_TARGET_BCMNS2 is not set
# CONFIG_ARCH_EXYNOS is not set
# CONFIG_ARCH_S5PC1XX is not set
# CONFIG_ARCH_HIGHBANK is not set
# CONFIG_ARCH_INTEGRATOR is not set
# CONFIG_ARCH_KEYSTONE is not set
# CONFIG_ARCH_K3 is not set
CONFIG_ARCH_OMAP2PLUS=y
# CONFIG_ARCH_MESON is not set
# CONFIG_ARCH_MEDIATEK is not set
# CONFIG_ARCH_LPC32XX is not set
# CONFIG_ARCH_IMX8 is not set
# CONFIG_ARCH_IMX8M is not set
# CONFIG_ARCH_MX23 is not set
# CONFIG_ARCH_MX25 is not set
# CONFIG_ARCH_MX28 is not set
# CONFIG_ARCH_MX31 is not set
# CONFIG_ARCH_MX7ULP is not set
# CONFIG_ARCH_MX7 is not set
# CONFIG_ARCH_MX6 is not set
CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
# CONFIG_ARCH_MX5 is not set
# CONFIG_ARCH_OWL is not set
# CONFIG_ARCH_QEMU is not set
# CONFIG_ARCH_RMOBILE is not set
# CONFIG_TARGET_S32V234EVB is not set
# CONFIG_ARCH_SNAPDRAGON is not set
# CONFIG_ARCH_SOCFPGA is not set
# CONFIG_ARCH_SUNXI is not set
# CONFIG_ARCH_VERSAL is not set
# CONFIG_ARCH_VF610 is not set
# CONFIG_ARCH_ZYNQ is not set
# CONFIG_ARCH_ZYNQMP_R5 is not set
# CONFIG_ARCH_ZYNQMP is not set
# CONFIG_TEGRA is not set
# CONFIG_TARGET_VEXPRESS64_AEMV8A is not set
# CONFIG_TARGET_VEXPRESS64_BASE_FVP is not set
# CONFIG_TARGET_VEXPRESS64_BASE_FVP_DRAM is not set
# CONFIG_TARGET_VEXPRESS64_JUNO is not set
# CONFIG_TARGET_LS2080A_EMU is not set
# CONFIG_TARGET_LS2080A_SIMU is not set
# CONFIG_TARGET_LS1088AQDS is not set
# CONFIG_TARGET_LS2080AQDS is not set
# CONFIG_TARGET_LS2080ARDB is not set
# CONFIG_TARGET_LS2081ARDB is not set
# CONFIG_TARGET_HIKEY is not set
# CONFIG_TARGET_POPLAR is not set
# CONFIG_TARGET_LS1012AQDS is not set
# CONFIG_TARGET_LS1012ARDB is not set
# CONFIG_TARGET_LS1012A2G5RDB is not set
# CONFIG_TARGET_LS1012AFRWY is not set
# CONFIG_TARGET_LS1012AFRDM is not set
# CONFIG_TARGET_LS1088ARDB is not set
# CONFIG_TARGET_LS1021AQDS is not set
# CONFIG_TARGET_LS1021ATWR is not set
# CONFIG_TARGET_LS1021AIOT is not set
# CONFIG_TARGET_LS1043AQDS is not set
# CONFIG_TARGET_LS1043ARDB is not set
# CONFIG_TARGET_LS1046AQDS is not set
# CONFIG_TARGET_LS1046ARDB is not set
# CONFIG_TARGET_H2200 is not set
# CONFIG_TARGET_ZIPITZ2 is not set
# CONFIG_TARGET_COLIBRI_PXA270 is not set
# CONFIG_ARCH_UNIPHIER is not set
# CONFIG_STM32 is not set
# CONFIG_ARCH_STI is not set
# CONFIG_ARCH_STM32MP is not set
# CONFIG_ARCH_ROCKCHIP is not set
# CONFIG_TARGET_THUNDERX_88XX is not set
# CONFIG_ARCH_ASPEED is not set
# CONFIG_TI_SECURE_DEVICE is not set
CONFIG_SYS_TEXT_BASE=0x80800000
CONFIG_TI_I2C_BOARD_DETECT=y
CONFIG_EEPROM_BUS_ADDRESS=0
CONFIG_EEPROM_CHIP_ADDRESS=0x50
CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
# CONFIG_OMAP34XX is not set
# CONFIG_OMAP44XX is not set
CONFIG_OMAP54XX=y
# CONFIG_TI814X is not set
# CONFIG_TI816X is not set
# CONFIG_AM43XX is not set
# CONFIG_AM33XX is not set
CONFIG_ISW_ENTRY_ADDR=0x40301350
CONFIG_DRA7XX=y
# CONFIG_TARGET_CL_SOM_AM57X is not set
# CONFIG_TARGET_CM_T54 is not set
# CONFIG_TARGET_OMAP5_UEVM is not set
# CONFIG_TARGET_DRA7XX_EVM is not set
CONFIG_TARGET_AM57XX_EVM=y
CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC=31219
#
# Voltage Domain OPP selections
#
CONFIG_DRA7_MPU_OPP_NOM=y
# CONFIG_DRA7_DSPEVE_OPP_NOM is not set
# CONFIG_DRA7_DSPEVE_OPP_OD is not set
CONFIG_DRA7_DSPEVE_OPP_HIGH=y
# CONFIG_DRA7_IVA_OPP_NOM is not set
# CONFIG_DRA7_IVA_OPP_OD is not set
CONFIG_DRA7_IVA_OPP_HIGH=y
# CONFIG_DRA7_GPU_OPP_NOM is not set
# CONFIG_DRA7_GPU_OPP_OD is not set
CONFIG_DRA7_GPU_OPP_HIGH=y
# CONFIG_TFABOOT is not set
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
# CONFIG_SPL_DRIVERS_MISC_SUPPORT is not set
CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL=y
CONFIG_IDENT_STRING=""
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_SPL_FAT_SUPPORT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_ARMV7_LPAE=y
# CONFIG_CMD_DEKBLOB is not set
# CONFIG_CMD_HDMIDETECT is not set
#
# ARM debug
#
CONFIG_DEBUG_LL=y
CONFIG_DEBUG_LL_UART_8250=y
CONFIG_DEBUG_LL_INCLUDE="debug/8250.S"
CONFIG_DEBUG_UART_PHYS=0x48020000
CONFIG_DEBUG_UART_VIRT=0x48020000
CONFIG_DEBUG_UART_8250_SHIFT=2
# CONFIG_DEBUG_UART_8250_WORD is not set
# CONFIG_DEBUG_UART_8250_FLOW_CONTROL is not set
CONFIG_SMBIOS_PRODUCT_NAME="am57xx"
# CONFIG_DEBUG_UART is not set
CONFIG_AHCI=y
#
# General setup
#
CONFIG_LOCALVERSION=""
CONFIG_LOCALVERSION_AUTO=y
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_NR_DRAM_BANKS=2
# CONFIG_SYS_BOOT_GET_CMDLINE is not set
# CONFIG_SYS_BOOT_GET_KBD is not set
CONFIG_SYS_MALLOC_F=y
CONFIG_TPL_SYS_MALLOC_F_LEN=0x2000
CONFIG_EXPERT=y
CONFIG_SYS_MALLOC_CLEAR_ON_INIT=y
# CONFIG_TOOLS_DEBUG is not set
# CONFIG_PHYS_64BIT is not set
#
# Boot images
#
CONFIG_ANDROID_BOOT_IMAGE=y
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x0
CONFIG_FIT_ENABLE_SHA256_SUPPORT=y
# CONFIG_FIT_SIGNATURE is not set
# CONFIG_FIT_VERBOSE is not set
# CONFIG_FIT_BEST_MATCH is not set
CONFIG_SPL_FIT=y
# CONFIG_SPL_FIT_PRINT is not set
# CONFIG_SPL_FIT_SIGNATURE is not set
CONFIG_SPL_LOAD_FIT=y
# CONFIG_SPL_LOAD_FIT_FULL is not set
# CONFIG_SPL_FIT_IMAGE_POST_PROCESS is not set
CONFIG_SPL_FIT_SOURCE=""
CONFIG_SPL_FIT_GENERATOR=""
CONFIG_IMAGE_FORMAT_LEGACY=y
CONFIG_OF_BOARD_SETUP=y
# CONFIG_OF_SYSTEM_SETUP is not set
# CONFIG_OF_STDOUT_VIA_ALIAS is not set
CONFIG_SYS_EXTRA_OPTIONS=""
CONFIG_ARCH_FIXUP_FDT_MEMORY=y
#
# API
#
# CONFIG_API is not set
#
# Boot timing
#
# CONFIG_BOOTSTAGE is not set
CONFIG_BOOTSTAGE_RECORD_COUNT=30
CONFIG_SPL_BOOTSTAGE_RECORD_COUNT=5
CONFIG_BOOTSTAGE_STASH_ADDR=0
CONFIG_BOOTSTAGE_STASH_SIZE=0x1000
#
# Boot media
#
# CONFIG_NAND_BOOT is not set
# CONFIG_ONENAND_BOOT is not set
# CONFIG_QSPI_BOOT is not set
# CONFIG_SATA_BOOT is not set
# CONFIG_SD_BOOT is not set
# CONFIG_SPI_BOOT is not set
CONFIG_BOOTDELAY=2
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="androidboot.serialno=${serial#} console=ttyS2,115200 androidboot.console=ttyS2 androidboot.hardware=beagle_x15board"
# CONFIG_USE_BOOTCOMMAND is not set
#
# Console
#
CONFIG_MENU=y
# CONFIG_CONSOLE_RECORD is not set
# CONFIG_DISABLE_CONSOLE is not set
CONFIG_LOGLEVEL=4
CONFIG_SPL_LOGLEVEL=4
CONFIG_TPL_LOGLEVEL=4
# CONFIG_SILENT_CONSOLE is not set
# CONFIG_PRE_CONSOLE_BUFFER is not set
# CONFIG_CONSOLE_MUX is not set
# CONFIG_SYS_CONSOLE_IS_IN_ENV is not set
# CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE is not set
# CONFIG_SYS_CONSOLE_ENV_OVERWRITE is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_SYS_STDIO_DEREGISTER is not set
#
# Logging
#
# CONFIG_LOG is not set
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_DEFAULT_FDT_FILE=""
# CONFIG_MISC_INIT_R is not set
CONFIG_VERSION_VARIABLE=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
# CONFIG_DISPLAY_BOARDINFO_LATE is not set
#
# Start-up hooks
#
# CONFIG_ARCH_EARLY_INIT_R is not set
# CONFIG_ARCH_MISC_INIT is not set
CONFIG_BOARD_EARLY_INIT_F=y
# CONFIG_BOARD_EARLY_INIT_R is not set
# CONFIG_LAST_STAGE_INIT is not set
#
# Security support
#
CONFIG_HASH=y
#
# Update support
#
# CONFIG_UPDATE_TFTP is not set
#
# Blob list
#
# CONFIG_BLOBLIST is not set
#
# SPL / TPL
#
CONFIG_SUPPORT_SPL=y
CONFIG_SPL_FRAMEWORK=y
CONFIG_SPL_BOARD_INIT=y
# CONFIG_SPL_BOOTROM_SUPPORT is not set
# CONFIG_SPL_BOOTCOUNT_LIMIT is not set
CONFIG_SPL_RAW_IMAGE_SUPPORT=y
CONFIG_SPL_LEGACY_IMAGE_SUPPORT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
# CONFIG_TPL_SYS_MALLOC_SIMPLE is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x100000
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SPL_BANNER_PRINT=y
CONFIG_TPL_BANNER_PRINT=y
# CONFIG_SPL_SKIP_CLEAR_BSS is not set
CONFIG_SPL_DISPLAY_PRINT=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION is not set
# CONFIG_SPL_CRC32_SUPPORT is not set
# CONFIG_SPL_MD5_SUPPORT is not set
# CONFIG_SPL_SHA1_SUPPORT is not set
# CONFIG_SPL_SHA256_SUPPORT is not set
# CONFIG_SPL_FIT_IMAGE_TINY is not set
# CONFIG_SPL_CPU_SUPPORT is not set
# CONFIG_SPL_CRYPTO_SUPPORT is not set
# CONFIG_SPL_HASH_SUPPORT is not set
# CONFIG_TPL_HASH_SUPPORT is not set
CONFIG_SPL_DMA_SUPPORT=y
CONFIG_SPL_ENV_SUPPORT=y
# CONFIG_SPL_SAVEENV is not set
# CONFIG_SPL_ETH_SUPPORT is not set
CONFIG_SPL_EXT_SUPPORT=y
# CONFIG_SPL_FPGA_SUPPORT is not set
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_SPL_DM_MAILBOX is not set
# CONFIG_SPL_MMC_WRITE is not set
# CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT is not set
# CONFIG_SPL_MTD_SUPPORT is not set
# CONFIG_SPL_MUSB_NEW_SUPPORT is not set
# CONFIG_SPL_NAND_SUPPORT is not set
# CONFIG_SPL_NET_SUPPORT is not set
# CONFIG_SPL_NO_CPU_SUPPORT is not set
# CONFIG_SPL_NOR_SUPPORT is not set
# CONFIG_SPL_XIP_SUPPORT is not set
# CONFIG_SPL_ONENAND_SUPPORT is not set
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_PAYLOAD="u-boot.bin"
# CONFIG_SPL_PCI is not set
# CONFIG_SPL_PCH_SUPPORT is not set
# CONFIG_SPL_POST_MEM_SUPPORT is not set
# CONFIG_SPL_DM_RESET is not set
CONFIG_SPL_POWER_SUPPORT=y
# CONFIG_SPL_POWER_DOMAIN is not set
# CONFIG_SPL_RAM_SUPPORT is not set
# CONFIG_SPL_REMOTEPROC is not set
# CONFIG_SPL_RTC_SUPPORT is not set
# CONFIG_SPL_SATA_SUPPORT is not set
CONFIG_SPL_SPI_FLASH_TINY=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SPL_THERMAL=y
# CONFIG_SPL_USB_HOST_SUPPORT is not set
# CONFIG_SPL_USB_GADGET is not set
# CONFIG_SPL_WATCHDOG_SUPPORT is not set
CONFIG_SPL_YMODEM_SUPPORT=y
# CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC is not set
# CONFIG_SPL_OPTEE is not set
#
# Command line interface
#
CONFIG_CMDLINE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMDLINE_EDITING=y
CONFIG_AUTO_COMPLETE=y
CONFIG_SYS_LONGHELP=y
CONFIG_SYS_PROMPT="=> "
#
# Autoboot options
#
CONFIG_AUTOBOOT=y
# CONFIG_AUTOBOOT_KEYED is not set
#
# Commands
#
#
# Info commands
#
CONFIG_CMD_BDI=y
# CONFIG_CMD_CONFIG is not set
CONFIG_CMD_CONSOLE=y
# CONFIG_CMD_CPU is not set
# CONFIG_CMD_LICENSE is not set
#
# Boot commands
#
CONFIG_CMD_BOOTD=y
CONFIG_CMD_BOOTM=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_BOOTEFI=y
CONFIG_CMD_BOOTEFI_HELLO_COMPILE=y
# CONFIG_CMD_BOOTEFI_HELLO is not set
# CONFIG_CMD_BOOTEFI_SELFTEST is not set
# CONFIG_CMD_BOOTMENU is not set
# CONFIG_CMD_DTIMG is not set
CONFIG_CMD_ELF=y
CONFIG_CMD_FDT=y
CONFIG_CMD_GO=y
CONFIG_CMD_RUN=y
CONFIG_CMD_IMI=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_XIMG=y
CONFIG_CMD_SPL=y
CONFIG_CMD_SPL_NAND_OFS=0
CONFIG_CMD_SPL_WRITE_SIZE=0x2000
# CONFIG_CMD_FITUPD is not set
# CONFIG_CMD_THOR_DOWNLOAD is not set
# CONFIG_CMD_ZBOOT is not set
#
# Environment commands
#
CONFIG_CMD_ASKENV=y
CONFIG_CMD_EXPORTENV=y
CONFIG_CMD_IMPORTENV=y
CONFIG_CMD_EDITENV=y
# CONFIG_CMD_GREPENV is not set
CONFIG_CMD_SAVEENV=y
CONFIG_CMD_ENV_EXISTS=y
# CONFIG_CMD_ENV_CALLBACK is not set
# CONFIG_CMD_ENV_FLAGS is not set
#
# Memory commands
#
# CONFIG_CMD_BINOP is not set
CONFIG_CMD_CRC32=y
# CONFIG_CRC32_VERIFY is not set
# CONFIG_LOOPW is not set
# CONFIG_CMD_MD5SUM is not set
# CONFIG_CMD_MEMINFO is not set
CONFIG_CMD_MEMORY=y
# CONFIG_CMD_MEMTEST is not set
# CONFIG_CMD_MX_CYCLIC is not set
# CONFIG_CMD_SHA1SUM is not set
# CONFIG_CMD_STRINGS is not set
#
# Compression commands
#
# CONFIG_CMD_LZMADEC is not set
# CONFIG_CMD_UNZIP is not set
# CONFIG_CMD_ZIP is not set
#
# Device access commands
#
# CONFIG_CMD_ARMFLASH is not set
# CONFIG_CMD_ADC is not set
# CONFIG_CMD_BIND is not set
# CONFIG_CMD_CLK is not set
# CONFIG_CMD_DEMO is not set
CONFIG_CMD_DFU=y
# CONFIG_CMD_DM is not set
CONFIG_CMD_FASTBOOT=y
# CONFIG_CMD_FDC is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGAD is not set
# CONFIG_CMD_FUSE is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_RANDOM_UUID=y
# CONFIG_CMD_GPT_RENAME is not set
# CONFIG_CMD_IDE is not set
# CONFIG_CMD_IO is not set
# CONFIG_CMD_IOTRACE is not set
CONFIG_CMD_I2C=y
CONFIG_CMD_LOADB=y
CONFIG_CMD_LOADS=y
CONFIG_CMD_MMC=y
# CONFIG_CMD_MMC_RPMB is not set
# CONFIG_CMD_MMC_SWRITE is not set
# CONFIG_CMD_MTD is not set
# CONFIG_CMD_NAND is not set
# CONFIG_CMD_MMC_SPI is not set
# CONFIG_CMD_ONENAND is not set
# CONFIG_CMD_OSD is not set
CONFIG_CMD_PART=y
# CONFIG_CMD_PCI is not set
# CONFIG_CMD_PCMCIA is not set
# CONFIG_CMD_PINMUX is not set
# CONFIG_CMD_POWEROFF is not set
# CONFIG_CMD_READ is not set
# CONFIG_CMD_SATA is not set
# CONFIG_CMD_SAVES is not set
CONFIG_CMD_SCSI=y
# CONFIG_CMD_SDRAM is not set
CONFIG_CMD_SF=y
# CONFIG_CMD_SF_TEST is not set
CONFIG_CMD_SPI=y
# CONFIG_CMD_TSI148 is not set
# CONFIG_CMD_UNIVERSE is not set
CONFIG_CMD_USB=y
# CONFIG_CMD_USB_SDP is not set
# CONFIG_CMD_USB_MASS_STORAGE is not set
#
# Shell scripting commands
#
CONFIG_CMD_ECHO=y
CONFIG_CMD_ITEST=y
CONFIG_CMD_SOURCE=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_NET=y
CONFIG_CMD_BOOTP=y
CONFIG_CMD_DHCP=y
CONFIG_BOOTP_BOOTPATH=y
CONFIG_BOOTP_DNS=y
# CONFIG_BOOTP_DNS2 is not set
CONFIG_BOOTP_GATEWAY=y
CONFIG_BOOTP_HOSTNAME=y
# CONFIG_BOOTP_PREFER_SERVERIP is not set
CONFIG_BOOTP_SUBNETMASK=y
# CONFIG_BOOTP_NTPSERVER is not set
CONFIG_BOOTP_PXE=y
CONFIG_BOOTP_PXE_CLIENTARCH=0x15
CONFIG_BOOTP_VCI_STRING="U-Boot.armv7"
CONFIG_CMD_TFTPBOOT=y
# CONFIG_CMD_TFTPPUT is not set
# CONFIG_CMD_TFTPSRV is not set
CONFIG_NET_TFTP_VARS=y
# CONFIG_CMD_RARP is not set
CONFIG_CMD_NFS=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
# CONFIG_CMD_CDP is not set
# CONFIG_CMD_SNTP is not set
# CONFIG_CMD_DNS is not set
# CONFIG_CMD_LINK_LOCAL is not set
# CONFIG_CMD_ETHSW is not set
CONFIG_CMD_PXE=y
# CONFIG_CMD_WOL is not set
#
# Misc commands
#
# CONFIG_CMD_BSP is not set
# CONFIG_CMD_BKOPS_ENABLE is not set
CONFIG_CMD_BLOCK_CACHE=y
# CONFIG_CMD_CACHE is not set
# CONFIG_CMD_CONITRACE is not set
# CONFIG_CMD_DISPLAY is not set
# CONFIG_CMD_LED is not set
# CONFIG_CMD_DATE is not set
CONFIG_CMD_TIME=y
# CONFIG_CMD_GETTIME is not set
CONFIG_CMD_MISC=y
# CONFIG_MP is not set
# CONFIG_CMD_TIMER is not set
# CONFIG_CMD_QFW is not set
# CONFIG_CMD_TERMINAL is not set
# CONFIG_CMD_UUID is not set
#
# TI specific command line interface
#
CONFIG_CMD_DDR3=y
#
# Power commands
#
# CONFIG_CMD_PMIC is not set
CONFIG_CMD_REGULATOR=y
#
# Security commands
#
# CONFIG_CMD_AES is not set
# CONFIG_CMD_BLOB is not set
# CONFIG_CMD_HASH is not set
#
# Firmware commands
#
#
# Filesystem commands
#
# CONFIG_CMD_BTRFS is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
# CONFIG_CMD_FS_UUID is not set
# CONFIG_CMD_JFFS2 is not set
# CONFIG_CMD_MTDPARTS is not set
# CONFIG_CMD_REISER is not set
# CONFIG_CMD_ZFS is not set
#
# Debug commands
#
# CONFIG_CMD_BEDBUG is not set
# CONFIG_CMD_DIAG is not set
# CONFIG_CMD_LOG is not set
# CONFIG_CMD_TRACE is not set
# CONFIG_CMD_UBI is not set
#
# Partition Types
#
CONFIG_PARTITIONS=y
# CONFIG_MAC_PARTITION is not set
# CONFIG_SPL_MAC_PARTITION is not set
CONFIG_DOS_PARTITION=y
CONFIG_SPL_DOS_PARTITION=y
CONFIG_ISO_PARTITION=y
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_AMIGA_PARTITION is not set
# CONFIG_SPL_AMIGA_PARTITION is not set
CONFIG_EFI_PARTITION=y
CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=128
CONFIG_EFI_PARTITION_ENTRIES_OFF=0
CONFIG_SPL_EFI_PARTITION=y
CONFIG_PARTITION_UUIDS=y
CONFIG_SPL_PARTITION_UUIDS=y
# CONFIG_PARTITION_TYPE_GUID is not set
CONFIG_SUPPORT_OF_CONTROL=y
CONFIG_DTC=y
#
# Device Tree Control
#
CONFIG_OF_CONTROL=y
# CONFIG_OF_BOARD_FIXUP is not set
CONFIG_SPL_OF_CONTROL=y
# CONFIG_OF_LIVE is not set
CONFIG_OF_SEPARATE=y
# CONFIG_OF_EMBED is not set
# CONFIG_OF_BOARD is not set
# CONFIG_OF_PRIOR_STAGE is not set
CONFIG_DEFAULT_DEVICE_TREE="am572x-idk"
CONFIG_OF_LIST="am57xx-beagle-x15 am57xx-beagle-x15-revb1 am57xx-beagle-x15-revc am572x-idk am571x-idk am574x-idk"
# CONFIG_MULTI_DTB_FIT is not set
# CONFIG_SPL_MULTI_DTB_FIT is not set
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clocks clock-names interrupt-parent"
# CONFIG_SPL_OF_PLATDATA is not set
CONFIG_MKIMAGE_DTC_PATH="dtc"
#
# Environment
#
# CONFIG_ENV_IS_IN_EEPROM is not set
CONFIG_ENV_IS_IN_FAT=y
# CONFIG_ENV_IS_IN_EXT4 is not set
# CONFIG_ENV_IS_IN_FLASH is not set
CONFIG_ENV_IS_IN_MMC=y
# CONFIG_ENV_IS_IN_NAND is not set
# CONFIG_ENV_IS_IN_NVRAM is not set
# CONFIG_ENV_IS_IN_ONENAND is not set
# CONFIG_ENV_IS_IN_REMOTE is not set
# CONFIG_ENV_IS_IN_SPI_FLASH is not set
# CONFIG_ENV_IS_IN_UBI is not set
CONFIG_ENV_FAT_INTERFACE="mmc"
CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
CONFIG_ENV_FAT_FILE="uboot.env"
# CONFIG_USE_DEFAULT_ENV_FILE is not set
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
# CONFIG_SPL_ENV_IS_NOWHERE is not set
CONFIG_SPL_ENV_IS_IN_MMC=y
CONFIG_SPL_ENV_IS_IN_FAT=y
CONFIG_NET=y
# CONFIG_NET_RANDOM_ETHADDR is not set
# CONFIG_NETCONSOLE is not set
#
# Device Drivers
#
#
# Generic Driver Options
#
CONFIG_DM=y
CONFIG_SPL_DM=y
CONFIG_DM_WARN=y
# CONFIG_DM_DEBUG is not set
CONFIG_DM_DEVICE_REMOVE=y
# CONFIG_SPL_DM_DEVICE_REMOVE is not set
CONFIG_DM_STDIO=y
CONFIG_DM_SEQ_ALIAS=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_REGMAP=y
# CONFIG_SPL_REGMAP is not set
CONFIG_SYSCON=y
# CONFIG_DEVRES is not set
CONFIG_SIMPLE_BUS=y
CONFIG_SPL_SIMPLE_BUS=y
CONFIG_OF_TRANSLATE=y
CONFIG_SPL_OF_TRANSLATE=y
CONFIG_DM_DEV_READ_INLINE=y
# CONFIG_ADC is not set
# CONFIG_ADC_EXYNOS is not set
# CONFIG_ADC_SANDBOX is not set
# CONFIG_SARADC_MESON is not set
# CONFIG_SARADC_ROCKCHIP is not set
# CONFIG_SATA is not set
CONFIG_LIBATA=y
CONFIG_SCSI_AHCI=y
#
# SATA/SCSI device support
#
# CONFIG_AHCI_PCI is not set
# CONFIG_SATA_CEVA is not set
CONFIG_DWC_AHCI=y
# CONFIG_DWC_AHSATA is not set
# CONFIG_FSL_SATA is not set
# CONFIG_MVSATA_IDE is not set
# CONFIG_SATA_MV is not set
# CONFIG_SATA_SIL is not set
# CONFIG_SATA_SIL3114 is not set
# CONFIG_AXI is not set
CONFIG_BLK=y
CONFIG_HAVE_BLOCK_DEVICE=y
CONFIG_SPL_BLK=y
CONFIG_BLOCK_CACHE=y
# CONFIG_SPL_BLOCK_CACHE is not set
# CONFIG_IDE is not set
# CONFIG_BOOTCOUNT_LIMIT is not set
#
# Clock
#
# CONFIG_CLK is not set
# CONFIG_CPU is not set
#
# Hardware crypto devices
#
# CONFIG_FSL_CAAM is not set
# CONFIG_SYS_FSL_SEC_BE is not set
# CONFIG_SYS_FSL_SEC_LE is not set
# CONFIG_IMX8M_DRAM is not set
# CONFIG_IMX8M_LPDDR4 is not set
# CONFIG_IMX8M_DDR4 is not set
CONFIG_SAVED_DRAM_TIMING_BASE=0x180000
#
# Demo for driver model
#
# CONFIG_DM_DEMO is not set
# CONFIG_BOARD is not set
#
# DFU support
#
CONFIG_DFU=y
CONFIG_DFU_OVER_USB=y
# CONFIG_DFU_TFTP is not set
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
#
# DMA Support
#
# CONFIG_DMA is not set
# CONFIG_TI_EDMA3 is not set
#
# Fastboot support
#
CONFIG_FASTBOOT=y
CONFIG_USB_FUNCTION_FASTBOOT=y
# CONFIG_UDP_FUNCTION_FASTBOOT is not set
CONFIG_FASTBOOT_BUF_ADDR=0x82000000
CONFIG_FASTBOOT_BUF_SIZE=0x2F000000
CONFIG_FASTBOOT_USB_DEV=1
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=1
CONFIG_FASTBOOT_GPT_NAME="gpt"
CONFIG_FASTBOOT_MBR_NAME="mbr"
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
# CONFIG_FIRMWARE is not set
#
# FPGA support
#
# CONFIG_FPGA_ALTERA is not set
# CONFIG_FPGA_SOCFPGA is not set
# CONFIG_FPGA_XILINX is not set
# CONFIG_FPGA_SPARTAN3 is not set
#
# GPIO Support
#
CONFIG_DM_GPIO=y
# CONFIG_ALTERA_PIO is not set
# CONFIG_DWAPB_GPIO is not set
# CONFIG_AT91_GPIO is not set
# CONFIG_ATMEL_PIO4 is not set
# CONFIG_DA8XX_GPIO is not set
# CONFIG_INTEL_BROADWELL_GPIO is not set
# CONFIG_INTEL_ICH6_GPIO is not set
# CONFIG_IMX_RGPIO2P is not set
# CONFIG_HSDK_CREG_GPIO is not set
# CONFIG_LPC32XX_GPIO is not set
# CONFIG_MSM_GPIO is not set
# CONFIG_MXC_GPIO is not set
CONFIG_OMAP_GPIO=y
# CONFIG_CMD_PCA953X is not set
# CONFIG_PCF8575_GPIO is not set
# CONFIG_ROCKCHIP_GPIO is not set
# CONFIG_XILINX_GPIO is not set
# CONFIG_CMD_TCA642X is not set
# CONFIG_TEGRA_GPIO is not set
# CONFIG_TEGRA186_GPIO is not set
# CONFIG_VYBRID_GPIO is not set
# CONFIG_DM_74X164 is not set
# CONFIG_DM_PCA953X is not set
# CONFIG_MPC8XXX_GPIO is not set
#
# Hardware Spinlock Support
#
# CONFIG_DM_HWSPINLOCK is not set
#
# I2C support
#
CONFIG_DM_I2C=y
# CONFIG_DM_I2C_COMPAT is not set
# CONFIG_I2C_SET_DEFAULT_BUS_NUM is not set
# CONFIG_DM_I2C_GPIO is not set
# CONFIG_SYS_I2C_FSL is not set
# CONFIG_SYS_I2C_DW is not set
# CONFIG_SYS_I2C_INTEL is not set
# CONFIG_SYS_I2C_IMX_LPI2C is not set
# CONFIG_SYS_I2C_MXC is not set
CONFIG_SYS_I2C_OMAP24XX=y
CONFIG_SYS_OMAP24_I2C_SLAVE=1
CONFIG_SYS_OMAP24_I2C_SPEED=100000
# CONFIG_SYS_I2C_ROCKCHIP is not set
# CONFIG_SYS_I2C_MVTWSI is not set
CONFIG_SYS_I2C_BUS_MAX=5
# CONFIG_SYS_I2C_IHS is not set
# CONFIG_I2C_MUX is not set
CONFIG_INPUT=y
# CONFIG_SPL_INPUT is not set
# CONFIG_DM_KEYBOARD is not set
# CONFIG_SPL_DM_KEYBOARD is not set
# CONFIG_CROS_EC_KEYB is not set
# CONFIG_TWL4030_INPUT is not set
#
# LED Support
#
# CONFIG_LED is not set
# CONFIG_SPL_LED is not set
# CONFIG_LED_STATUS is not set
#
# Mailbox Controller Support
#
# CONFIG_DM_MAILBOX is not set
#
# Memory Controller drivers
#
#
# Multifunction device drivers
#
CONFIG_MISC=y
# CONFIG_ALTERA_SYSID is not set
# CONFIG_ATSHA204A is not set
# CONFIG_ROCKCHIP_EFUSE is not set
# CONFIG_VEXPRESS_CONFIG is not set
# CONFIG_CROS_EC is not set
# CONFIG_DS4510 is not set
# CONFIG_FSL_SEC_MON is not set
# CONFIG_MXC_OCOTP is not set
# CONFIG_NUVOTON_NCT6102D is not set
# CONFIG_PWRSEQ is not set
# CONFIG_PCA9551_LED is not set
# CONFIG_TWL4030_LED is not set
# CONFIG_WINBOND_W83627 is not set
# CONFIG_I2C_EEPROM is not set
# CONFIG_SPL_I2C_EEPROM is not set
CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0x0
# CONFIG_GDSYS_RXAUI_CTRL is not set
# CONFIG_GDSYS_IOEP is not set
# CONFIG_MPC83XX_SERDES is not set
# CONFIG_FS_LOADER is not set
# CONFIG_GDSYS_SOC is not set
# CONFIG_IHS_FPGA is not set
#
# MMC Host controller Support
#
CONFIG_MMC=y
CONFIG_MMC_WRITE=y
# CONFIG_MMC_BROKEN_CD is not set
CONFIG_DM_MMC=y
CONFIG_SPL_DM_MMC=y
# CONFIG_ARM_PL180_MMCI is not set
CONFIG_MMC_QUIRKS=y
CONFIG_MMC_HW_PARTITIONING=y
# CONFIG_SUPPORT_EMMC_RPMB is not set
# CONFIG_MMC_IO_VOLTAGE is not set
# CONFIG_SPL_MMC_IO_VOLTAGE is not set
# CONFIG_MMC_HS400_SUPPORT is not set
# CONFIG_SPL_MMC_HS400_SUPPORT is not set
# CONFIG_MMC_HS200_SUPPORT is not set
# CONFIG_SPL_MMC_HS200_SUPPORT is not set
CONFIG_MMC_VERBOSE=y
# CONFIG_MMC_TRACE is not set
# CONFIG_SPL_MMC_TINY is not set
# CONFIG_MMC_DW is not set
# CONFIG_MMC_MXC is not set
# CONFIG_MMC_PCI is not set
CONFIG_MMC_OMAP_HS=y
CONFIG_MMC_OMAP_HS_ADMA=y
# CONFIG_MMC_SDHCI is not set
# CONFIG_STM32_SDMMC2 is not set
# CONFIG_FTSDC010 is not set
# CONFIG_FSL_ESDHC is not set
#
# MTD Support
#
# CONFIG_MTD is not set
# CONFIG_MTD_NOR_FLASH is not set
# CONFIG_MTD_DEVICE is not set
# CONFIG_FLASH_CFI_DRIVER is not set
# CONFIG_NAND is not set
#
# SPI Flash Support
#
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
# CONFIG_SPI_FLASH_SFDP_SUPPORT is not set
# CONFIG_SPI_FLASH_BAR is not set
# CONFIG_SF_DUAL_FLASH is not set
# CONFIG_SPI_FLASH_ATMEL is not set
# CONFIG_SPI_FLASH_EON is not set
# CONFIG_SPI_FLASH_GIGADEVICE is not set
# CONFIG_SPI_FLASH_ISSI is not set
# CONFIG_SPI_FLASH_MACRONIX is not set
CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_STMICRO is not set
# CONFIG_SPI_FLASH_SST is not set
# CONFIG_SPI_FLASH_WINBOND is not set
# CONFIG_SPI_FLASH_XMC is not set
CONFIG_SPI_FLASH_USE_4K_SECTORS=y
# CONFIG_SPI_FLASH_DATAFLASH is not set
# CONFIG_SPI_FLASH_MTD is not set
#
# UBI support
#
# CONFIG_CONFIG_UBI_SILENCE_MSG is not set
# CONFIG_MTD_UBI is not set
# CONFIG_BITBANGMII is not set
# CONFIG_MV88E6352_SWITCH is not set
CONFIG_PHYLIB=y
# CONFIG_PHY_ADDR_ENABLE is not set
# CONFIG_B53_SWITCH is not set
# CONFIG_MV88E61XX_SWITCH is not set
# CONFIG_PHYLIB_10G is not set
# CONFIG_PHY_AQUANTIA is not set
# CONFIG_PHY_ATHEROS is not set
# CONFIG_PHY_BROADCOM is not set
# CONFIG_PHY_CORTINA is not set
# CONFIG_PHY_DAVICOM is not set
# CONFIG_PHY_ET1011C is not set
# CONFIG_PHY_LXT is not set
# CONFIG_PHY_MARVELL is not set
# CONFIG_PHY_MESON_GXL is not set
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
# CONFIG_PHY_MICREL_KSZ8XXX is not set
# CONFIG_PHY_MSCC is not set
# CONFIG_PHY_NATSEMI is not set
# CONFIG_PHY_REALTEK is not set
# CONFIG_PHY_SMSC is not set
# CONFIG_PHY_TERANETICS is not set
# CONFIG_PHY_TI is not set
# CONFIG_PHY_VITESSE is not set
# CONFIG_PHY_XILINX is not set
# CONFIG_PHY_FIXED is not set
# CONFIG_FSL_PFE is not set
CONFIG_DM_ETH=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
# CONFIG_ALTERA_TSE is not set
# CONFIG_BCM_SF2_ETH is not set
# CONFIG_DWC_ETH_QOS is not set
# CONFIG_E1000 is not set
# CONFIG_ETH_DESIGNWARE is not set
# CONFIG_ETHOC is not set
# CONFIG_FTMAC100 is not set
# CONFIG_FTGMAC100 is not set
# CONFIG_MACB is not set
# CONFIG_RGMII is not set
CONFIG_MII=y
# CONFIG_RTL8139 is not set
# CONFIG_RTL8169 is not set
# CONFIG_SMC911X is not set
# CONFIG_SUN7I_GMAC is not set
# CONFIG_SUN4I_EMAC is not set
# CONFIG_SUN8I_EMAC is not set
# CONFIG_SH_ETHER is not set
CONFIG_DRIVER_TI_CPSW=y
# CONFIG_DRIVER_TI_EMAC is not set
# CONFIG_DRIVER_TI_KEYSTONE_NET is not set
# CONFIG_SYS_DPAA_QBMAN is not set
# CONFIG_TSEC_ENET is not set
# CONFIG_PCI is not set
#
# PHY Subsystem
#
CONFIG_PHY=y
# CONFIG_SPL_PHY is not set
# CONFIG_NOP_PHY is not set
CONFIG_PIPE3_PHY=y
# CONFIG_MSM8916_USB_PHY is not set
CONFIG_OMAP_USB2_PHY=y
# CONFIG_MVEBU_COMPHY_SUPPORT is not set
#
# Pin controllers
#
# CONFIG_PINCTRL is not set
# CONFIG_SPL_PINCTRL is not set
#
# Power
#
#
# Power Domain Support
#
# CONFIG_POWER_DOMAIN is not set
CONFIG_DM_PMIC=y
CONFIG_PMIC_CHILDREN=y
CONFIG_SPL_PMIC_CHILDREN=y
# CONFIG_PMIC_ACT8846 is not set
# CONFIG_PMIC_AS3722 is not set
# CONFIG_DM_PMIC_FAN53555 is not set
# CONFIG_DM_PMIC_PFUZE100 is not set
# CONFIG_DM_PMIC_MAX77686 is not set
# CONFIG_DM_PMIC_MAX8998 is not set
# CONFIG_DM_PMIC_MC34708 is not set
# CONFIG_PMIC_MAX8997 is not set
# CONFIG_PMIC_PM8916 is not set
# CONFIG_PMIC_RK8XX is not set
# CONFIG_PMIC_S2MPS11 is not set
# CONFIG_DM_PMIC_SANDBOX is not set
# CONFIG_PMIC_S5M8767 is not set
# CONFIG_PMIC_RN5T567 is not set
# CONFIG_PMIC_TPS65090 is not set
CONFIG_PMIC_PALMAS=y
# CONFIG_PMIC_LP873X is not set
# CONFIG_PMIC_LP87565 is not set
# CONFIG_POWER_MC34VR500 is not set
# CONFIG_DM_PMIC_TPS65910 is not set
# CONFIG_PMIC_STPMU1 is not set
CONFIG_DM_REGULATOR=y
# CONFIG_SPL_DM_REGULATOR is not set
# CONFIG_REGULATOR_PWM is not set
# CONFIG_DM_REGULATOR_FIXED is not set
# CONFIG_DM_REGULATOR_GPIO is not set
CONFIG_DM_REGULATOR_PALMAS=y
CONFIG_DM_REGULATOR_PBIAS=y
# CONFIG_DM_REGULATOR_TPS62360 is not set
# CONFIG_DM_PWM is not set
# CONFIG_PWM_SANDBOX is not set
# CONFIG_U_QE is not set
# CONFIG_RAM is not set
#
# Remote Processor drivers
#
#
# Reset Controller Support
#
# CONFIG_DM_RESET is not set
#
# Real Time Clock
#
# CONFIG_DM_RTC is not set
# CONFIG_SPL_DM_RTC is not set
# CONFIG_RTC_PL031 is not set
# CONFIG_RTC_S35392A is not set
# CONFIG_RTC_MC146818 is not set
# CONFIG_RTC_M41T62 is not set
CONFIG_SCSI=y
CONFIG_DM_SCSI=y
#
# Serial drivers
#
CONFIG_BAUDRATE=115200
CONFIG_REQUIRE_SERIAL_CONSOLE=y
# CONFIG_SPECIFY_CONSOLE_INDEX is not set
CONFIG_SERIAL_PRESENT=y
CONFIG_SPL_SERIAL_PRESENT=y
CONFIG_TPL_SERIAL_PRESENT=y
CONFIG_DM_SERIAL=y
# CONFIG_SERIAL_RX_BUFFER is not set
# CONFIG_SERIAL_SEARCH_ALL is not set
CONFIG_SPL_DM_SERIAL=y
# CONFIG_TPL_DM_SERIAL is not set
# CONFIG_DEBUG_UART_SKIP_INIT is not set
# CONFIG_ALTERA_JTAG_UART is not set
# CONFIG_ALTERA_UART is not set
# CONFIG_ARC_SERIAL is not set
# CONFIG_ATMEL_USART is not set
# CONFIG_BCM6345_SERIAL is not set
# CONFIG_FSL_LINFLEXUART is not set
# CONFIG_FSL_LPUART is not set
# CONFIG_MVEBU_A3700_UART is not set
# CONFIG_NULLDEV_SERIAL is not set
CONFIG_SYS_NS16550=y
# CONFIG_PL01X_SERIAL is not set
# CONFIG_MSM_SERIAL is not set
CONFIG_OMAP_SERIAL=y
# CONFIG_PXA_SERIAL is not set
# CONFIG_SIFIVE_SERIAL is not set
# CONFIG_MTK_SERIAL is not set
# CONFIG_SMEM is not set
#
# Sound support
#
# CONFIG_SOUND is not set
#
# SOC (System On Chip) specific Drivers
#
# CONFIG_SOC_TI is not set
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_SPI_MEM=y
# CONFIG_ALTERA_SPI is not set
# CONFIG_ATCSPI200_SPI is not set
# CONFIG_ATMEL_SPI is not set
# CONFIG_BCMSTB_SPI is not set
# CONFIG_CADENCE_QSPI is not set
# CONFIG_DESIGNWARE_SPI is not set
# CONFIG_EXYNOS_SPI is not set
# CONFIG_FSL_DSPI is not set
# CONFIG_ICH_SPI is not set
# CONFIG_MTK_QSPI is not set
# CONFIG_MVEBU_A3700_SPI is not set
# CONFIG_PL022_SPI is not set
# CONFIG_ROCKCHIP_SPI is not set
# CONFIG_SUN4I_SPI is not set
# CONFIG_TEGRA114_SPI is not set
# CONFIG_TEGRA20_SFLASH is not set
# CONFIG_TEGRA20_SLINK is not set
# CONFIG_TEGRA210_QSPI is not set
CONFIG_TI_QSPI=y
# CONFIG_XILINX_SPI is not set
# CONFIG_SOFT_SPI is not set
# CONFIG_CF_SPI is not set
# CONFIG_FSL_ESPI is not set
# CONFIG_FSL_QSPI is not set
# CONFIG_SH_SPI is not set
# CONFIG_SH_QSPI is not set
# CONFIG_KIRKWOOD_SPI is not set
# CONFIG_LPC32XX_SSP is not set
# CONFIG_MPC8XXX_SPI is not set
# CONFIG_MXC_SPI is not set
# CONFIG_MXS_SPI is not set
# CONFIG_OMAP3_SPI is not set
#
# SPMI support
#
# CONFIG_SPMI is not set
#
# System reset device drivers
#
# CONFIG_SYSRESET is not set
# CONFIG_SYSRESET_SYSCON is not set
# CONFIG_SYSRESET_WATCHDOG is not set
# CONFIG_SYSRESET_MCP83XX is not set
# CONFIG_TEE is not set
# CONFIG_OPTEE is not set
CONFIG_DM_THERMAL=y
CONFIG_TI_DRA7_THERMAL=y
#
# Timer Support
#
# CONFIG_TIMER is not set
#
# TPM support
#
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_SPL_DM_USB=y
CONFIG_DM_USB_GADGET=y
CONFIG_SPL_DM_USB_GADGET=y
#
# USB Host Controller Drivers
#
CONFIG_USB_HOST=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y
# CONFIG_USB_XHCI_PCI is not set
CONFIG_USB_XHCI_DRA7XX_INDEX=0
# CONFIG_USB_XHCI_FSL is not set
# CONFIG_USB_EHCI_HCD is not set
# CONFIG_USB_OHCI_HCD is not set
# CONFIG_USB_UHCI_HCD is not set
# CONFIG_USB_DWC2 is not set
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GADGET=y
#
# Platform Glue Driver Support
#
# CONFIG_USB_DWC3_OMAP is not set
CONFIG_USB_DWC3_GENERIC=y
#
# PHY Subsystem
#
# CONFIG_USB_DWC3_PHY_OMAP is not set
# CONFIG_USB_DWC3_PHY_SAMSUNG is not set
#
# Legacy MUSB Support
#
# CONFIG_USB_MUSB_HCD is not set
# CONFIG_USB_MUSB_UDC is not set
# CONFIG_USB_OMAP3 is not set
# CONFIG_USB_AM35X is not set
#
# MUSB Controller Driver
#
# CONFIG_USB_MUSB_HOST is not set
# CONFIG_USB_MUSB_GADGET is not set
# CONFIG_USB_MUSB_TI is not set
# CONFIG_USB_MUSB_OMAP2PLUS is not set
# CONFIG_USB_MUSB_AM35X is not set
# CONFIG_USB_MUSB_DSPS is not set
# CONFIG_USB_MUSB_PIO_ONLY is not set
#
# USB Phy
#
# CONFIG_TWL4030_USB is not set
# CONFIG_OMAP_USB_PHY is not set
# CONFIG_ROCKCHIP_USB2_PHY is not set
#
# ULPI drivers
#
#
# USB peripherals
#
CONFIG_USB_STORAGE=y
# CONFIG_USB_KEYBOARD is not set
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
CONFIG_USB_GADGET_VENDOR_NUM=0x0451
CONFIG_USB_GADGET_PRODUCT_NUM=0xd022
# CONFIG_USB_GADGET_ATMEL_USBA is not set
# CONFIG_USB_GADGET_BCM_UDC_OTG_PHY is not set
# CONFIG_USB_GADGET_DWC2_OTG is not set
# CONFIG_CI_UDC is not set
CONFIG_USB_GADGET_VBUS_DRAW=2
CONFIG_USB_GADGET_DUALSPEED=y
CONFIG_USB_GADGET_DOWNLOAD=y
# CONFIG_USB_FUNCTION_MASS_STORAGE is not set
# CONFIG_USB_FUNCTION_ROCKUSB is not set
# CONFIG_USB_FUNCTION_SDP is not set
# CONFIG_USB_FUNCTION_THOR is not set
# CONFIG_USB_ETHER is not set
# CONFIG_USB_HOST_ETHER is not set
#
# Graphics support
#
# CONFIG_DM_VIDEO is not set
# CONFIG_SYS_WHITE_ON_BLACK is not set
# CONFIG_NO_FB_CLEAR is not set
#
# TrueType Fonts
#
# CONFIG_VIDEO_VESA is not set
# CONFIG_VIDEO_LCD_ANX9804 is not set
# CONFIG_VIDEO_LCD_SSD2828 is not set
# CONFIG_VIDEO_MVEBU is not set
# CONFIG_VIDEO_OMAP3 is not set
# CONFIG_I2C_EDID is not set
# CONFIG_DISPLAY is not set
# CONFIG_VIDEO_TEGRA20 is not set
# CONFIG_VIDEO_BRIDGE is not set
# CONFIG_VIDEO is not set
# CONFIG_LCD is not set
# CONFIG_VIDEO_SIMPLE is not set
# CONFIG_VIDEO_DT_SIMPLEFB is not set
# CONFIG_OSD is not set
#
# VirtIO Drivers
#
# CONFIG_VIRTIO_MMIO is not set
#
# 1-Wire support
#
# CONFIG_W1 is not set
#
# 1-wire EEPROM support
#
# CONFIG_W1_EEPROM is not set
#
# Watchdog Timer Support
#
# CONFIG_WATCHDOG is not set
# CONFIG_WATCHDOG_RESET_DISABLE is not set
# CONFIG_BCM2835_WDT is not set
# CONFIG_OMAP_WATCHDOG is not set
# CONFIG_ULP_WATCHDOG is not set
# CONFIG_WDT is not set
# CONFIG_IMX_WATCHDOG is not set
# CONFIG_PHYS_TO_BUS is not set
#
# File systems
#
# CONFIG_FS_BTRFS is not set
# CONFIG_FS_CBFS is not set
CONFIG_FS_EXT4=y
CONFIG_EXT4_WRITE=y
CONFIG_FS_FAT=y
CONFIG_FAT_WRITE=y
CONFIG_FS_FAT_MAX_CLUSTSIZE=65536
# CONFIG_FS_JFFS2 is not set
# CONFIG_UBIFS_SILENCE_MSG is not set
# CONFIG_FS_CRAMFS is not set
# CONFIG_YAFFS2 is not set
#
# Library routines
#
# CONFIG_BCH is not set
# CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED is not set
# CONFIG_DYNAMIC_CRC_TABLE is not set
CONFIG_HAVE_PRIVATE_LIBGCC=y
CONFIG_LIB_UUID=y
CONFIG_PRINTF=y
CONFIG_SPL_PRINTF=y
CONFIG_SPRINTF=y
CONFIG_SPL_SPRINTF=y
CONFIG_STRTO=y
CONFIG_SPL_STRTO=y
CONFIG_IMAGE_SPARSE=y
CONFIG_IMAGE_SPARSE_FILLBUF_SIZE=0x80000
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_SYS_HZ=1000
# CONFIG_USE_TINY_PRINTF is not set
# CONFIG_PANIC_HANG is not set
CONFIG_REGEX=y
CONFIG_LIB_RAND=y
# CONFIG_LIB_HW_RAND is not set
# CONFIG_SPL_TINY_MEMSET is not set
# CONFIG_TPL_TINY_MEMSET is not set
# CONFIG_BITREVERSE is not set
# CONFIG_CMD_DHRYSTONE is not set
#
# Security support
#
# CONFIG_AES is not set
# CONFIG_RSA is not set
# CONFIG_TPM is not set
# CONFIG_SPL_TPM is not set
#
# Android Verified Boot
#
# CONFIG_LIBAVB is not set
#
# Hashing Support
#
CONFIG_SHA1=y
CONFIG_SHA256=y
# CONFIG_SHA_HW_ACCEL is not set
CONFIG_MD5=y
#
# Compression Support
#
# CONFIG_LZ4 is not set
# CONFIG_LZMA is not set
# CONFIG_LZO is not set
# CONFIG_SPL_LZ4 is not set
# CONFIG_SPL_LZO is not set
# CONFIG_SPL_GZIP is not set
# CONFIG_ERRNO_STR is not set
# CONFIG_HEXDUMP is not set
CONFIG_OF_LIBFDT=y
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_SPL_OF_LIBFDT=y
# CONFIG_TPL_OF_LIBFDT is not set
#
# System tables
#
CONFIG_GENERATE_SMBIOS_TABLE=y
CONFIG_SMBIOS_MANUFACTURER="ti"
CONFIG_EFI_LOADER=y
CONFIG_EFI_UNICODE_CAPITALIZATION=y
CONFIG_OPTEE_TZDRAM_SIZE=0x0000000
CONFIG_OPTEE_TZDRAM_BASE=0x00000000
# CONFIG_UNIT_TEST is not set
--------------------------------------------------------
Make kernel
make clean
make distclean
make tisdk_am57xx-evm-rt_defconfig
make menuconfig
-> DEBUG_LL [=y]
-> DEBUG_OMAP4UART3 [=y]
-> EARLY_PRINTK [=y]
-> DEBUG_UART_PHYS [=0x48020000]
-> DEBUG_UART_VIRT [=0xfa020000]
make -j8 zImage
make -j8 zImage dtbs
copy zImage to bootpartition as zImage
copy arch/arm/boot/dts/am57xx-beagle-x15.dtb to bootpartition save as custom.dtb
I have don´t have changed files now!
diff --git a/.config b/.config index c95fc1d..269a652 100644 --- a/.config +++ b/.config @@ -6085,8 +6085,33 @@ CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y # CONFIG_DEBUG_WX is not set # CONFIG_ARM_UNWIND is not set # CONFIG_DEBUG_USER is not set -# CONFIG_DEBUG_LL is not set -CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" +CONFIG_DEBUG_LL=y +# CONFIG_DEBUG_OMAP2UART1 is not set +# CONFIG_DEBUG_OMAP2UART2 is not set +# CONFIG_DEBUG_OMAP2UART3 is not set +# CONFIG_DEBUG_OMAP3UART3 is not set +CONFIG_DEBUG_OMAP4UART3=y +# CONFIG_DEBUG_OMAP3UART4 is not set +# CONFIG_DEBUG_OMAP4UART4 is not set +# CONFIG_DEBUG_TI81XXUART1 is not set +# CONFIG_DEBUG_TI81XXUART2 is not set +# CONFIG_DEBUG_TI81XXUART3 is not set +# CONFIG_DEBUG_AM33XXUART1 is not set +# CONFIG_DEBUG_ZOOM_UART is not set +# CONFIG_DEBUG_ICEDCC is not set +# CONFIG_DEBUG_SEMIHOSTING is not set +# CONFIG_DEBUG_LL_UART_8250 is not set +# CONFIG_DEBUG_LL_UART_PL01X is not set +CONFIG_DEBUG_LL_INCLUDE="debug/8250.S" +CONFIG_DEBUG_UART_8250=y +CONFIG_DEBUG_UART_PHYS=0x48020000 +CONFIG_DEBUG_UART_VIRT=0xfa020000 +CONFIG_DEBUG_UART_8250_SHIFT=2 +# CONFIG_DEBUG_UART_8250_WORD is not set +# CONFIG_DEBUG_UART_8250_PALMCHIP is not set +# CONFIG_DEBUG_UART_8250_FLOW_CONTROL is not set +# CONFIG_DEBUG_UNCOMPRESS is not set CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" +CONFIG_EARLY_PRINTK=y # CONFIG_PID_IN_CONTEXTIDR is not set # CONFIG_CORESIGHT is not set
Here the converted dts from am57xx-beagle-x15.dtb
x15--rt_conv.dts.txt
-----------------------------------------------------------
I start the board and MLO start. I interrupt the start and write:
setenv bootargs console=ttyS2,115200 debug verbose panic=0 earlyprintk mem=0x40000000 loglevel=7
load mmc 0:1 0x88000000 custom.dtb
load mmc 0:1 0x82000000 zImage
bootz 0x82000000 - 0x88000000
you can see the Messages in text-file
