Other Parts Discussed in Thread: TLV320AIC3106, PCM5102A, BEAGLEBOARD-X15
Hi
we have to port codec driver in AM571-idk to explore the codec functionality before our custom board arrived.Based on the reference design (AM572x-GP-EVM), we have connected AM571x-idk with TLV320AIC3106 EVM. We modified the design by feeding 24.576 MHz (1.8V) clock from external source to AC15(osc1). Also we did the pinmuxing in u-boot.wehave verified the I2c write from user space.we have selected clockout2(24.576MHz),I2c1 and McASP3 as interface. We did the configuration as suggested from the SDK doccumentation( menuconfig).we expect 24.576MHz clock at clockout2 pin. But no clock at the clockout2 pin.I am attaching the modified dts,dtsi,.config and kernel log file with this mail.I can route system clock2(24.576Mhz) to clockout2 by writing register directly.I think clock must be needed for configuring McASP and TLV320AIC3106 before initialisation.I have following queries
1) is attached DTS is enough or something is needed ?
2) is clock is needed for McASP and codec at the time of probing?
3)How can i proceed further?
Regards
Satheesh Kumar S
/*
* Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
#include "am571x-idk-common.dtsi"
/ {
model = "TI AM5718 IDK";
aliases {
ethernet4 = &pruss1_emac0;
ethernet5 = &pruss1_emac1;
};
/* Dual mac ethernet application node on icss2 */
pruss1_eth: pruss1_eth {
status = "okay";
compatible = "ti,am57-prueth";
prus = <&pru1_0>, <&pru1_1>;
firmware-name = "ti-pruss/am57xx-pru0-prueth-fw.elf",
"ti-pruss/am57xx-pru1-prueth-fw.elf";
ti,pruss-gp-mux-sel = <0>, /* GP, default */
<4>; /* MII2, needed for PRUSS1_MII1 */
sram = <&ocmcram1>;
interrupt-parent = <&pruss1_intc>;
interrupts = <20>, <21>;
interrupt-names = "rx_red_hp", "rx_red_lp";
pruss1_emac0: ethernet-mii0 {
phy-handle = <&pruss1_eth0_phy>;
phy-mode = "mii";
interrupts = <20>, <22>, <23>, <26>;
interrupt-names = "rx", "tx", "hsrprp_ptp_tx",
"emac_ptp_tx";
/* Filled in by bootloader */
local-mac-address = [00 00 00 00 00 00];
};
pruss1_emac1: ethernet-mii1 {
phy-handle = <&pruss1_eth1_phy>;
phy-mode = "mii";
interrupts = <21>, <23>, <24>, <27>;
interrupt-names = "rx", "tx", "hsrprp_ptp_tx",
"emac_ptp_tx";
/* Filled in by bootloader */
local-mac-address = [00 00 00 00 00 00];
};
};
sound0: sound0 {
compatible = "simple-audio-card";
simple-audio-card,name = "BeagleBoard-X15";
simple-audio-card,widgets =
"Line", "Line Out",
"Line", "Line In";
simple-audio-card,routing =
"Line Out", "LLOUT",
"Line Out", "RLOUT",
"MIC2L", "Line In",
"MIC2R", "Line In";
simple-audio-card,format = "dsp_b";
simple-audio-card,bitclock-master = <&sound0_master>;
simple-audio-card,frame-master = <&sound0_master>;
simple-audio-card,bitclock-inversion;
simple-audio-card,cpu {
sound-dai = <&mcasp3>;
};
sound0_master: simple-audio-card,codec {
sound-dai = <&tlv320aic3106>;
clocks = <&clkout2_clk>;
};
};
};
&pruss1_mdio {
status = "okay";
reset-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
reset-delay-us = <2>; /* PHY datasheet states 1uS min */
pruss1_eth0_phy: ethernet-phy@0 {
reg = <0>;
interrupt-parent = <&gpio3>;
interrupts = <28 IRQ_TYPE_EDGE_FALLING>;
};
pruss1_eth1_phy: ethernet-phy@1 {
reg = <1>;
interrupt-parent = <&gpio3>;
interrupts = <29 IRQ_TYPE_EDGE_FALLING>;
};
};
&pruss2_eth {
ti,pruss-gp-mux-sel = <4>, /* MII2, needed for PRUSS1_MII0 */
<4>; /* MII2, needed for PRUSS1_MII1 */
};
&mcasp3 {
#sound-dai-cells = <0>;
assigned-clocks = <&mcasp3_ahclkx_mux>;
assigned-clock-parents = <&sys_clkin2>;
status = "okay";
op-mode = <0>; /* MCASP_IIS_MODE */
tdm-slots = <2>;
/* 4 serializers */
serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
1 2 0 0
>;
tx-num-evt = <32>;
rx-num-evt = <32>;
};
#include "am57xx-evm-cmem-am571x.dtsi"
/*
* Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include "am57xx-industrial-grade.dtsi"
/ {
aliases {
rtc0 = &tps659038_rtc;
rtc1 = &rtc;
display0 = &hdmi0;
ethernet2 = &pruss2_emac0;
ethernet3 = &pruss2_emac1;
};
chosen {
stdout-path = &uart3;
};
vmain: fixedregulator-vmain {
compatible = "regulator-fixed";
regulator-name = "VMAIN";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
regulator-boot-on;
};
v3_3d: fixedregulator-v3_3d {
compatible = "regulator-fixed";
regulator-name = "V3_3D";
vin-supply = <&smps9_reg>;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
};
vtt_fixed: fixedregulator-vtt {
/* TPS51200 */
compatible = "regulator-fixed";
regulator-name = "vtt_fixed";
vin-supply = <&v3_3d>;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
};
vdd_3v3: fixedregulator-vdd_3v3 {
compatible = "regulator-fixed";
regulator-name = "vdd_3v3";
vin-supply = <®en1>;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
aic_dvdd: fixedregulator-aic_dvdd {
compatible = "regulator-fixed";
regulator-name = "aic_dvdd_fixed";
vin-supply = <&vdd_3v3>;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
src_clk_x1: src_clk_x1 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <20000000>;
};
leds-iio {
status = "disabled";
compatible = "gpio-leds";
led-out0 {
label = "out0";
gpios = <&tpic2810 0 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led-out1 {
label = "out1";
gpios = <&tpic2810 1 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led-out2 {
label = "out2";
gpios = <&tpic2810 2 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led-out3 {
label = "out3";
gpios = <&tpic2810 3 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led-out4 {
label = "out4";
gpios = <&tpic2810 4 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led-out5 {
label = "out5";
gpios = <&tpic2810 5 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led-out6 {
label = "out6";
gpios = <&tpic2810 6 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led-out7 {
label = "out7";
gpios = <&tpic2810 7 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
};
hdmi0: connector@0 {
compatible = "hdmi-connector";
label = "hdmi";
type = "a";
port {
hdmi_connector_in: endpoint {
remote-endpoint = <&tpd12s015_out>;
};
};
};
tpd12s015: encoder@0 {
compatible = "ti,tpd12s016", "ti,tpd12s015";
gpios = <0>, /* optional CT_CP_HPD */
<0>, /* optional LS_OE */
<&gpio7 12 GPIO_ACTIVE_HIGH>; /* HPD */
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
tpd12s015_in: endpoint@0 {
remote-endpoint = <&hdmi_out>;
};
};
port@1 {
reg = <1>;
tpd12s015_out: endpoint@0 {
remote-endpoint = <&hdmi_connector_in>;
};
};
};
};
src_clk_x1: src_clk_x1 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <20000000>;
};
/* Dual-MAC Ethernet application node on PRU-ICSS2 */
pruss2_eth: pruss2_eth {
compatible = "ti,am57-prueth";
prus = <&pru2_0>, <&pru2_1>;
firmware-name = "ti-pruss/am57xx-pru0-prueth-fw.elf",
"ti-pruss/am57xx-pru1-prueth-fw.elf";
sram = <&ocmcram1>;
interrupt-parent = <&pruss2_intc>;
interrupts = <20>, <21>;
interrupt-names = "rx_red_hp", "rx_red_lp";
pruss2_emac0: ethernet-mii0 {
phy-handle = <&pruss2_eth0_phy>;
phy-mode = "mii";
interrupts = <20>, <22>, <23>, <26>;
interrupt-names = "rx", "tx", "hsrprp_ptp_tx",
"emac_ptp_tx";
/* Filled in by bootloader */
local-mac-address = [00 00 00 00 00 00];
};
pruss2_emac1: ethernet-mii1 {
phy-handle = <&pruss2_eth1_phy>;
phy-mode = "mii";
interrupts = <21>, <23>, <24>, <27>;
interrupt-names = "rx", "tx", "hsrprp_ptp_tx",
"emac_ptp_tx";
/* Filled in by bootloader */
local-mac-address = [00 00 00 00 00 00];
};
};
ptp_bc: ptp_bc {
compatible = "ti,am57-bc";
status = "disabled";
};
};
&dra7_pmx_core {
dcan1_pins_default: dcan1_pins_default {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
DRA7XX_CORE_IOPAD(0x37d4, PIN_INPUT_PULLUP | MUX_MODE0) /* dcan1_rx */
>;
};
dcan1_pins_sleep: dcan1_pins_sleep {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x37d0, MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
DRA7XX_CORE_IOPAD(0x37d4, MUX_MODE15 | PULL_UP) /* dcan1_rx.off */
>;
};
};
&i2c1 {
status = "okay";
clock-frequency = <400000>;
tps659038: tps659038@58 {
compatible = "ti,tps659038";
reg = <0x58>;
interrupts-extended = <&gpio6 16 IRQ_TYPE_LEVEL_HIGH
&dra7_pmx_core 0x418>;
#interrupt-cells = <2>;
interrupt-controller;
ti,system-power-controller;
ti,palmas-override-powerhold;
tps659038_pmic {
compatible = "ti,tps659038-pmic";
smps12-in-supply = <&vmain>;
smps3-in-supply = <&vmain>;
smps45-in-supply = <&vmain>;
smps6-in-supply = <&vmain>;
smps7-in-supply = <&vmain>;
smps8-in-supply = <&vmain>;
smps9-in-supply = <&vmain>;
ldo1-in-supply = <&vmain>;
ldo2-in-supply = <&vmain>;
ldo3-in-supply = <&vmain>;
ldo4-in-supply = <&vmain>;
ldo9-in-supply = <&vmain>;
ldoln-in-supply = <&vmain>;
ldousb-in-supply = <&vmain>;
ldortc-in-supply = <&vmain>;
regulators {
smps12_reg: smps12 {
/* VDD_MPU */
regulator-name = "smps12";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1250000>;
regulator-always-on;
regulator-boot-on;
};
smps3_reg: smps3 {
/* VDD_DDR EMIF1 EMIF2 */
regulator-name = "smps3";
regulator-min-microvolt = <1350000>;
regulator-max-microvolt = <1350000>;
regulator-always-on;
regulator-boot-on;
};
smps45_reg: smps45 {
/* VDD_DSPEVE on AM572 */
/* VDD_IVA + VDD_DSP on AM571 */
regulator-name = "smps45";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1250000>;
regulator-always-on;
regulator-boot-on;
};
smps6_reg: smps6 {
/* VDD_GPU */
regulator-name = "smps6";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1250000>;
regulator-always-on;
regulator-boot-on;
};
smps7_reg: smps7 {
/* VDD_CORE */
regulator-name = "smps7";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1150000>;
regulator-always-on;
regulator-boot-on;
};
smps8_reg: smps8 {
/* 5728 - VDD_IVAHD */
/* 5718 - N.C. test point */
regulator-name = "smps8";
};
smps9_reg: smps9 {
/* VDD_3_3D */
regulator-name = "smps9";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
};
ldo1_reg: ldo1 {
/* VDDSHV8 - VSDMMC */
/* NOTE: on rev 1.3a, data supply */
regulator-name = "ldo1";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldo2_reg: ldo2 {
/* VDDSH18V */
regulator-name = "ldo2";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
ldo3_reg: ldo3 {
/* R1.3a 572x V1_8PHY_LDO3: USB, SATA */
regulator-name = "ldo3";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
ldo4_reg: ldo4 {
/* R1.3a 572x V1_8PHY_LDO4: PCIE, HDMI*/
regulator-name = "ldo4";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
/* LDO5-8 unused */
ldo9_reg: ldo9 {
/* VDD_RTC */
regulator-name = "ldo9";
regulator-min-microvolt = <840000>;
regulator-max-microvolt = <1160000>;
regulator-always-on;
regulator-boot-on;
};
ldoln_reg: ldoln {
/* VDDA_1V8_PLL */
regulator-name = "ldoln";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
ldousb_reg: ldousb {
/* VDDA_3V_USB: VDDA_USBHS33 */
regulator-name = "ldousb";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
};
ldortc_reg: ldortc {
/* VDDA_RTC */
regulator-name = "ldortc";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
regen1: regen1 {
/* VDD_3V3_ON */
regulator-name = "regen1";
regulator-boot-on;
regulator-always-on;
};
regen2: regen2 {
/* Needed for PMIC internal resource */
regulator-name = "regen2";
regulator-boot-on;
regulator-always-on;
};
};
};
tps659038_rtc: tps659038_rtc {
compatible = "ti,palmas-rtc";
interrupt-parent = <&tps659038>;
interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
wakeup-source;
};
tps659038_pwr_button: tps659038_pwr_button {
compatible = "ti,palmas-pwrbutton";
interrupt-parent = <&tps659038>;
interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
wakeup-source;
ti,palmas-long-press-seconds = <12>;
};
tps659038_gpio: tps659038_gpio {
compatible = "ti,palmas-gpio";
gpio-controller;
#gpio-cells = <2>;
};
extcon_usb2: tps659038_usb {
compatible = "ti,palmas-usb-vid";
ti,enable-vbus-detection;
ti,enable-id-detection;
/* ID & VBUS GPIOs provided in board dts */
};
};
tpic2810: tpic2810@60 {
compatible = "ti,tpic2810";
reg = <0x60>;
gpio-controller;
#gpio-cells = <2>;
};
tc358778: tc358778@0e {
compatible = "toshiba,tc358778", "toshiba,tc358768";
reg = <0x0e>;
status = "disabled";
clocks = <&src_clk_x1>;
clock-names = "refclk";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
tc358778_in: endpoint {
remote-endpoint = <&dpi_out>;
data-lines = <24>;
};
};
port@1 {
reg = <1>;
tc358778_out: endpoint {
/*
* lanes and remote-endpoint defined per
* panel.
*/
};
};
};
};
ov2659: ov2659@30 {
compatible = "ovti,ov2659";
reg = <0x30>;
clocks = <&src_clk_x1>;
clock-names = "xvclk";
pwrdn-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
port {
ov2659_1: endpoint {
hsync-active = <1>;
vsync-active = <1>;
pclk-sample = <1>;
link-frequencies = /bits/ 64 <70000000>;
};
};
};
tlv320aic3106: tlv320aic3106@18 {
#sound-dai-cells = <0>;
compatible = "ti,tlv320aic3106";
reg = <0x18>;
assigned-clocks = <&clkoutmux2_clk_mux>;
assigned-clock-parents = <&sys_clk2_dclk_div>;
status = "okay";
adc-settle-ms = <40>;
AVDD-supply = <&vdd_3v3>; //vdd_3v3 v3_3d
IOVDD-supply = <&vdd_3v3>;
DRVDD-supply = <&vdd_3v3>;
DVDD-supply = <&aic_dvdd>; //aic_dvdd ldo2_reg
};
};
&mcspi3 {
status = "okay";
ti,pindir-d0-out-d1-in;
sn65hvs882: sn65hvs882@0 {
compatible = "pisosr-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0>;
spi-max-frequency = <1000000>;
spi-cpol;
};
};
&uart3 {
status = "okay";
interrupts-extended = <&crossbar_mpu GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH
&dra7_pmx_core 0x248>;
};
&rtc {
status = "okay";
ext-clk-src;
};
&mac {
status = "okay";
dual_emac;
};
&cpsw_emac0 {
phy_id = <&davinci_mdio>, <0>;
phy-mode = "rgmii";
dual_emac_res_vlan = <1>;
};
&cpsw_emac1 {
phy_id = <&davinci_mdio>, <1>;
phy-mode = "rgmii";
dual_emac_res_vlan = <2>;
};
&usb2_phy1 {
phy-supply = <&ldousb_reg>;
};
&usb2_phy2 {
phy-supply = <&ldousb_reg>;
};
&usb1 {
dr_mode = "host";
};
&omap_dwc3_2 {
extcon = <&extcon_usb2>;
};
&usb2 {
extcon = <&extcon_usb2>;
dr_mode = "otg";
};
&mmc1 {
status = "okay";
vmmc-supply = <&v3_3d>;
vqmmc-supply = <&ldo1_reg>;
bus-width = <4>;
cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; /* gpio 219 */
};
&mmc2 {
status = "okay";
vmmc-supply = <&v3_3d>;
vqmmc-supply = <&v3_3d>;
bus-width = <8>;
non-removable;
max-frequency = <96000000>;
no-1-8-v;
};
&dcan1 {
status = "okay";
pinctrl-names = "default", "sleep", "active";
pinctrl-0 = <&dcan1_pins_sleep>;
pinctrl-1 = <&dcan1_pins_sleep>;
pinctrl-2 = <&dcan1_pins_default>;
};
&qspi {
status = "okay";
spi-max-frequency = <76800000>;
m25p80@0 {
compatible = "s25fl256s1", "jedec,spi-nor";
spi-max-frequency = <76800000>;
reg = <0>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>;
#address-cells = <1>;
#size-cells = <1>;
/* MTD partition table.
* The ROM checks the first four physical blocks
* for a valid file to boot and the flash here is
* 64KiB block size.
*/
partition@0 {
label = "QSPI.SPL";
reg = <0x00000000 0x000040000>;
};
partition@1 {
label = "QSPI.u-boot";
reg = <0x00040000 0x00100000>;
};
partition@2 {
label = "QSPI.u-boot-spl-os";
reg = <0x00140000 0x00080000>;
};
partition@3 {
label = "QSPI.u-boot-env";
reg = <0x001c0000 0x00010000>;
};
partition@4 {
label = "QSPI.u-boot-env.backup1";
reg = <0x001d0000 0x0010000>;
};
partition@5 {
label = "QSPI.kernel";
reg = <0x001e0000 0x0800000>;
};
partition@6 {
label = "QSPI.file-system";
reg = <0x009e0000 0x01620000>;
};
};
};
&gpu {
status = "ok";
};
&hdmi {
status = "okay";
/*
* XXX: Support AM572x-Rev 1.2a. this is wrong for AM571x-rev 1.3a,
* AM572x-Rev1.3a - but thanks to always-on, they work.
* TODO: SWITCH TO LDO4 once rev 1.2a is deprecated
* (on rev 1.3a availability)
*/
vdda-supply = <&ldo3_reg>;
port {
hdmi_out: endpoint {
remote-endpoint = <&tpd12s015_in>;
};
};
};
&dss {
status = "okay";
vdda_video-supply = <&ldoln_reg>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dpi_out: endpoint {
remote-endpoint = <&tc358778_in>;
data-lines = <24>;
};
};
};
};
&bb2d {
status = "okay";
};
&pruss_soc_bus1 {
status = "okay";
pruss1: pruss@0 {
status = "okay";
};
};
&pruss_soc_bus2 {
status = "okay";
pruss2: pruss@0 {
status = "okay";
};
};
&pruss2_mdio {
status = "okay";
pruss2_eth0_phy: ethernet-phy@0 {
reg = <0>;
interrupt-parent = <&gpio3>;
interrupts = <30 IRQ_TYPE_EDGE_FALLING>;
};
pruss2_eth1_phy: ethernet-phy@1 {
reg = <1>;
interrupt-parent = <&gpio3>;
interrupts = <31 IRQ_TYPE_EDGE_FALLING>;
};
};
&cpu0 {
vdd-supply = <&smps12_reg>;
};
/*
* Device Tree Source for DRA7xx clock data
*
* Copyright (C) 2013 Texas Instruments, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
&cm_core_aon_clocks {
atl_clkin0_ck: atl_clkin0_ck {
#clock-cells = <0>;
compatible = "ti,dra7-atl-clock";
clocks = <&atl_gfclk_mux>;
};
atl_clkin1_ck: atl_clkin1_ck {
#clock-cells = <0>;
compatible = "ti,dra7-atl-clock";
clocks = <&atl_gfclk_mux>;
};
atl_clkin2_ck: atl_clkin2_ck {
#clock-cells = <0>;
compatible = "ti,dra7-atl-clock";
clocks = <&atl_gfclk_mux>;
};
atl_clkin3_ck: atl_clkin3_ck {
#clock-cells = <0>;
compatible = "ti,dra7-atl-clock";
clocks = <&atl_gfclk_mux>;
};
hdmi_clkin_ck: hdmi_clkin_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
};
mlb_clkin_ck: mlb_clkin_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
};
mlbp_clkin_ck: mlbp_clkin_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
};
pciesref_acs_clk_ck: pciesref_acs_clk_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <100000000>;
};
ref_clkin0_ck: ref_clkin0_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
};
ref_clkin1_ck: ref_clkin1_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
};
ref_clkin2_ck: ref_clkin2_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
};
ref_clkin3_ck: ref_clkin3_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
};
rmii_clk_ck: rmii_clk_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
};
sdvenc_clkin_ck: sdvenc_clkin_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
};
secure_32k_clk_src_ck: secure_32k_clk_src_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32768>;
};
sys_clk32_crystal_ck: sys_clk32_crystal_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32768>;
};
sys_clk32_pseudo_ck: sys_clk32_pseudo_ck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&sys_clkin1>;
clock-mult = <1>;
clock-div = <610>;
};
virt_12000000_ck: virt_12000000_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <12000000>;
};
virt_13000000_ck: virt_13000000_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <13000000>;
};
virt_16800000_ck: virt_16800000_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <16800000>;
};
virt_19200000_ck: virt_19200000_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <19200000>;
};
virt_20000000_ck: virt_20000000_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <20000000>;
};
virt_26000000_ck: virt_26000000_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <26000000>;
};
virt_27000000_ck: virt_27000000_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <27000000>;
};
virt_38400000_ck: virt_38400000_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <38400000>;
};
sys_clkin2: sys_clkin2 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24576000>;
};
usb_otg_clkin_ck: usb_otg_clkin_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
};
video1_clkin_ck: video1_clkin_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
};
video1_m2_clkin_ck: video1_m2_clkin_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
};
video2_clkin_ck: video2_clkin_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
};
video2_m2_clkin_ck: video2_m2_clkin_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
};
dpll_abe_ck: dpll_abe_ck@1e0 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-m4xen-clock";
clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>;
reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>;
assigned-clocks = <&dpll_abe_ck>;
assigned-clock-rates = <50000000>;
};
dpll_abe_x2_ck: dpll_abe_x2_ck {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-x2-clock";
clocks = <&dpll_abe_ck>;
};
dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@1f0 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_abe_x2_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
reg = <0x01f0>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
};
abe_clk: abe_clk@108 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_abe_m2x2_ck>;
ti,max-div = <4>;
reg = <0x0108>;
ti,index-power-of-two;
};
dpll_abe_m2_ck: dpll_abe_m2_ck@1f0 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_abe_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
reg = <0x01f0>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
};
dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@1f4 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_abe_x2_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
reg = <0x01f4>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
};
dpll_core_byp_mux: dpll_core_byp_mux@12c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
ti,bit-shift = <23>;
reg = <0x012c>;
};
dpll_core_ck: dpll_core_ck@120 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-core-clock";
clocks = <&sys_clkin1>, <&dpll_core_byp_mux>;
reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>;
};
dpll_core_x2_ck: dpll_core_x2_ck {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-x2-clock";
clocks = <&dpll_core_ck>;
};
dpll_core_h12x2_ck: dpll_core_h12x2_ck@13c {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <63>;
ti,autoidle-shift = <8>;
reg = <0x013c>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
};
mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&dpll_core_h12x2_ck>;
clock-mult = <1>;
clock-div = <1>;
};
dpll_mpu_ck: dpll_mpu_ck@160 {
#clock-cells = <0>;
compatible = "ti,omap5-mpu-dpll-clock";
clocks = <&sys_clkin1>, <&mpu_dpll_hs_clk_div>;
reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>;
};
dpll_mpu_m2_ck: dpll_mpu_m2_ck@170 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_mpu_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
reg = <0x0170>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
};
mpu_dclk_div: mpu_dclk_div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&dpll_mpu_m2_ck>;
clock-mult = <1>;
clock-div = <1>;
};
dsp_dpll_hs_clk_div: dsp_dpll_hs_clk_div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&dpll_core_h12x2_ck>;
clock-mult = <1>;
clock-div = <1>;
};
dpll_dsp_byp_mux: dpll_dsp_byp_mux@240 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&dsp_dpll_hs_clk_div>;
ti,bit-shift = <23>;
reg = <0x0240>;
};
dpll_dsp_ck: dpll_dsp_ck@234 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
clocks = <&sys_clkin1>, <&dpll_dsp_byp_mux>;
reg = <0x0234>, <0x0238>, <0x0240>, <0x023c>;
assigned-clocks = <&dpll_dsp_ck>;
assigned-clock-rates = <600000000>;
};
dpll_dsp_m2_ck: dpll_dsp_m2_ck@244 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_dsp_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
reg = <0x0244>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
assigned-clocks = <&dpll_dsp_m2_ck>;
assigned-clock-rates = <600000000>;
};
iva_dpll_hs_clk_div: iva_dpll_hs_clk_div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&dpll_core_h12x2_ck>;
clock-mult = <1>;
clock-div = <1>;
};
dpll_iva_byp_mux: dpll_iva_byp_mux@1ac {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&iva_dpll_hs_clk_div>;
ti,bit-shift = <23>;
reg = <0x01ac>;
};
dpll_iva_ck: dpll_iva_ck@1a0 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
clocks = <&sys_clkin1>, <&dpll_iva_byp_mux>;
reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
assigned-clocks = <&dpll_iva_ck>;
assigned-clock-rates = <1165000000>;
};
dpll_iva_m2_ck: dpll_iva_m2_ck@1b0 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_iva_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
reg = <0x01b0>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
assigned-clocks = <&dpll_iva_m2_ck>;
assigned-clock-rates = <388333334>;
};
iva_dclk: iva_dclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&dpll_iva_m2_ck>;
clock-mult = <1>;
clock-div = <1>;
};
dpll_gpu_byp_mux: dpll_gpu_byp_mux@2e4 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
ti,bit-shift = <23>;
reg = <0x02e4>;
};
dpll_gpu_ck: dpll_gpu_ck@2d8 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
clocks = <&sys_clkin1>, <&dpll_gpu_byp_mux>;
reg = <0x02d8>, <0x02dc>, <0x02e4>, <0x02e0>;
assigned-clocks = <&dpll_gpu_ck>;
assigned-clock-rates = <1277000000>;
};
dpll_gpu_m2_ck: dpll_gpu_m2_ck@2e8 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_gpu_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
reg = <0x02e8>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
assigned-clocks = <&dpll_gpu_m2_ck>;
assigned-clock-rates = <425666667>;
};
dpll_core_m2_ck: dpll_core_m2_ck@130 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_core_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
reg = <0x0130>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
};
core_dpll_out_dclk_div: core_dpll_out_dclk_div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&dpll_core_m2_ck>;
clock-mult = <1>;
clock-div = <1>;
};
dpll_ddr_byp_mux: dpll_ddr_byp_mux@21c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
ti,bit-shift = <23>;
reg = <0x021c>;
};
dpll_ddr_ck: dpll_ddr_ck@210 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
clocks = <&sys_clkin1>, <&dpll_ddr_byp_mux>;
reg = <0x0210>, <0x0214>, <0x021c>, <0x0218>;
};
dpll_ddr_m2_ck: dpll_ddr_m2_ck@220 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_ddr_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
reg = <0x0220>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
};
dpll_gmac_byp_mux: dpll_gmac_byp_mux@2b4 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
ti,bit-shift = <23>;
reg = <0x02b4>;
};
dpll_gmac_ck: dpll_gmac_ck@2a8 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
clocks = <&sys_clkin1>, <&dpll_gmac_byp_mux>;
reg = <0x02a8>, <0x02ac>, <0x02b4>, <0x02b0>;
};
dpll_gmac_m2_ck: dpll_gmac_m2_ck@2b8 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_gmac_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
reg = <0x02b8>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
};
video2_dclk_div: video2_dclk_div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&video2_m2_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
video1_dclk_div: video1_dclk_div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&video1_m2_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
hdmi_dclk_div: hdmi_dclk_div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&hdmi_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
per_dpll_hs_clk_div: per_dpll_hs_clk_div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&dpll_abe_m3x2_ck>;
clock-mult = <1>;
clock-div = <2>;
};
usb_dpll_hs_clk_div: usb_dpll_hs_clk_div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&dpll_abe_m3x2_ck>;
clock-mult = <1>;
clock-div = <3>;
};
eve_dpll_hs_clk_div: eve_dpll_hs_clk_div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&dpll_core_h12x2_ck>;
clock-mult = <1>;
clock-div = <1>;
};
dpll_eve_byp_mux: dpll_eve_byp_mux@290 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&eve_dpll_hs_clk_div>;
ti,bit-shift = <23>;
reg = <0x0290>;
};
dpll_eve_ck: dpll_eve_ck@284 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
clocks = <&sys_clkin1>, <&dpll_eve_byp_mux>;
reg = <0x0284>, <0x0288>, <0x0290>, <0x028c>;
};
dpll_eve_m2_ck: dpll_eve_m2_ck@294 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_eve_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
reg = <0x0294>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
};
eve_dclk_div: eve_dclk_div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&dpll_eve_m2_ck>;
clock-mult = <1>;
clock-div = <1>;
};
dpll_core_h13x2_ck: dpll_core_h13x2_ck@140 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <63>;
ti,autoidle-shift = <8>;
reg = <0x0140>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
};
dpll_core_h14x2_ck: dpll_core_h14x2_ck@144 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <63>;
ti,autoidle-shift = <8>;
reg = <0x0144>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
};
dpll_core_h22x2_ck: dpll_core_h22x2_ck@154 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <63>;
ti,autoidle-shift = <8>;
reg = <0x0154>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
};
dpll_core_h23x2_ck: dpll_core_h23x2_ck@158 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <63>;
ti,autoidle-shift = <8>;
reg = <0x0158>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
};
dpll_core_h24x2_ck: dpll_core_h24x2_ck@15c {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <63>;
ti,autoidle-shift = <8>;
reg = <0x015c>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
};
dpll_ddr_x2_ck: dpll_ddr_x2_ck {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-x2-clock";
clocks = <&dpll_ddr_ck>;
};
dpll_ddr_h11x2_ck: dpll_ddr_h11x2_ck@228 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_ddr_x2_ck>;
ti,max-div = <63>;
ti,autoidle-shift = <8>;
reg = <0x0228>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
};
dpll_dsp_x2_ck: dpll_dsp_x2_ck {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-x2-clock";
clocks = <&dpll_dsp_ck>;
};
dpll_dsp_m3x2_ck: dpll_dsp_m3x2_ck@248 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_dsp_x2_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
reg = <0x0248>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
assigned-clocks = <&dpll_dsp_m3x2_ck>;
assigned-clock-rates = <400000000>;
};
dpll_gmac_x2_ck: dpll_gmac_x2_ck {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-x2-clock";
clocks = <&dpll_gmac_ck>;
};
dpll_gmac_h11x2_ck: dpll_gmac_h11x2_ck@2c0 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_gmac_x2_ck>;
ti,max-div = <63>;
ti,autoidle-shift = <8>;
reg = <0x02c0>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
};
dpll_gmac_h12x2_ck: dpll_gmac_h12x2_ck@2c4 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_gmac_x2_ck>;
ti,max-div = <63>;
ti,autoidle-shift = <8>;
reg = <0x02c4>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
};
dpll_gmac_h13x2_ck: dpll_gmac_h13x2_ck@2c8 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_gmac_x2_ck>;
ti,max-div = <63>;
ti,autoidle-shift = <8>;
reg = <0x02c8>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
};
dpll_gmac_m3x2_ck: dpll_gmac_m3x2_ck@2bc {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_gmac_x2_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
reg = <0x02bc>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
};
gmii_m_clk_div: gmii_m_clk_div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&dpll_gmac_h11x2_ck>;
clock-mult = <1>;
clock-div = <2>;
};
hdmi_clk2_div: hdmi_clk2_div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&hdmi_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
hdmi_div_clk: hdmi_div_clk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&hdmi_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
l3_iclk_div: l3_iclk_div@100 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
ti,max-div = <2>;
ti,bit-shift = <4>;
reg = <0x0100>;
clocks = <&dpll_core_h12x2_ck>;
ti,index-power-of-two;
};
l4_root_clk_div: l4_root_clk_div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&l3_iclk_div>;
clock-mult = <1>;
clock-div = <2>;
};
video1_clk2_div: video1_clk2_div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&video1_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
video1_div_clk: video1_div_clk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&video1_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
video2_clk2_div: video2_clk2_div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&video2_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
video2_div_clk: video2_div_clk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&video2_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
ipu1_gfclk_mux: ipu1_gfclk_mux@520 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&dpll_abe_m2x2_ck>, <&dpll_core_h22x2_ck>;
ti,bit-shift = <24>;
reg = <0x0520>;
assigned-clocks = <&ipu1_gfclk_mux>;
assigned-clock-parents = <&dpll_core_h22x2_ck>;
};
mcasp1_ahclkr_mux: mcasp1_ahclkr_mux@550 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
ti,bit-shift = <28>;
reg = <0x0550>;
};
mcasp1_ahclkx_mux: mcasp1_ahclkx_mux@550 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
ti,bit-shift = <24>;
reg = <0x0550>;
};
mcasp1_aux_gfclk_mux: mcasp1_aux_gfclk_mux@550 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
ti,bit-shift = <22>;
reg = <0x0550>;
};
timer5_gfclk_mux: timer5_gfclk_mux@558 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
ti,bit-shift = <24>;
reg = <0x0558>;
};
timer6_gfclk_mux: timer6_gfclk_mux@560 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
ti,bit-shift = <24>;
reg = <0x0560>;
};
timer7_gfclk_mux: timer7_gfclk_mux@568 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
ti,bit-shift = <24>;
reg = <0x0568>;
};
timer8_gfclk_mux: timer8_gfclk_mux@570 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
ti,bit-shift = <24>;
reg = <0x0570>;
};
uart6_gfclk_mux: uart6_gfclk_mux@580 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
ti,bit-shift = <24>;
reg = <0x0580>;
};
dummy_ck: dummy_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
};
};
&prm_clocks {
sys_clkin1: sys_clkin1@110 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&virt_12000000_ck>, <&virt_20000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
reg = <0x0110>;
ti,index-starts-at-one;
};
abe_dpll_sys_clk_mux: abe_dpll_sys_clk_mux@118 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&sys_clkin2>;
reg = <0x0118>;
};
abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux@114 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>;
reg = <0x0114>;
};
abe_dpll_clk_mux: abe_dpll_clk_mux@10c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>;
reg = <0x010c>;
};
abe_24m_fclk: abe_24m_fclk@11c {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_abe_m2x2_ck>;
reg = <0x011c>;
ti,dividers = <8>, <16>;
};
aess_fclk: aess_fclk@178 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&abe_clk>;
reg = <0x0178>;
ti,max-div = <2>;
};
abe_giclk_div: abe_giclk_div@174 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&aess_fclk>;
reg = <0x0174>;
ti,max-div = <2>;
};
abe_lp_clk_div: abe_lp_clk_div@1d8 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_abe_m2x2_ck>;
reg = <0x01d8>;
ti,dividers = <16>, <32>;
};
abe_sys_clk_div: abe_sys_clk_div@120 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&sys_clkin1>;
reg = <0x0120>;
ti,max-div = <2>;
};
adc_gfclk_mux: adc_gfclk_mux@1dc {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&sys_clkin2>, <&sys_32k_ck>;
reg = <0x01dc>;
};
sys_clk1_dclk_div: sys_clk1_dclk_div@1c8 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&sys_clkin1>;
ti,max-div = <64>;
reg = <0x01c8>;
ti,index-power-of-two;
};
sys_clk2_dclk_div: sys_clk2_dclk_div@1cc {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&sys_clkin2>;
ti,max-div = <64>;
reg = <0x01cc>;
ti,index-power-of-two;
};
per_abe_x1_dclk_div: per_abe_x1_dclk_div@1bc {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_abe_m2_ck>;
ti,max-div = <64>;
reg = <0x01bc>;
ti,index-power-of-two;
};
dsp_gclk_div: dsp_gclk_div@18c {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_dsp_m2_ck>;
ti,max-div = <64>;
reg = <0x018c>;
ti,index-power-of-two;
};
gpu_dclk: gpu_dclk@1a0 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_gpu_m2_ck>;
ti,max-div = <64>;
reg = <0x01a0>;
ti,index-power-of-two;
};
emif_phy_dclk_div: emif_phy_dclk_div@190 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_ddr_m2_ck>;
ti,max-div = <64>;
reg = <0x0190>;
ti,index-power-of-two;
};
gmac_250m_dclk_div: gmac_250m_dclk_div@19c {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_gmac_m2_ck>;
ti,max-div = <64>;
reg = <0x019c>;
ti,index-power-of-two;
};
gmac_main_clk: gmac_main_clk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&gmac_250m_dclk_div>;
clock-mult = <1>;
clock-div = <2>;
};
l3init_480m_dclk_div: l3init_480m_dclk_div@1ac {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_usb_m2_ck>;
ti,max-div = <64>;
reg = <0x01ac>;
ti,index-power-of-two;
};
usb_otg_dclk_div: usb_otg_dclk_div@184 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&usb_otg_clkin_ck>;
ti,max-div = <64>;
reg = <0x0184>;
ti,index-power-of-two;
};
sata_dclk_div: sata_dclk_div@1c0 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&sys_clkin1>;
ti,max-div = <64>;
reg = <0x01c0>;
ti,index-power-of-two;
};
pcie2_dclk_div: pcie2_dclk_div@1b8 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_pcie_ref_m2_ck>;
ti,max-div = <64>;
reg = <0x01b8>;
ti,index-power-of-two;
};
pcie_dclk_div: pcie_dclk_div@1b4 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&apll_pcie_m2_ck>;
ti,max-div = <64>;
reg = <0x01b4>;
ti,index-power-of-two;
};
emu_dclk_div: emu_dclk_div@194 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&sys_clkin1>;
ti,max-div = <64>;
reg = <0x0194>;
ti,index-power-of-two;
};
secure_32k_dclk_div: secure_32k_dclk_div@1c4 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&secure_32k_clk_src_ck>;
ti,max-div = <64>;
reg = <0x01c4>;
ti,index-power-of-two;
};
clkoutmux0_clk_mux: clkoutmux0_clk_mux@158 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
reg = <0x0158>;
};
clkoutmux1_clk_mux: clkoutmux1_clk_mux@15c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
reg = <0x015c>;
};
clkoutmux2_clk_mux: clkoutmux2_clk_mux@160 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
reg = <0x0160>;
};
custefuse_sys_gfclk_div: custefuse_sys_gfclk_div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&sys_clkin1>;
clock-mult = <1>;
clock-div = <2>;
};
eve_clk: eve_clk@180 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&dpll_eve_m2_ck>, <&dpll_dsp_m3x2_ck>;
reg = <0x0180>;
};
hdmi_dpll_clk_mux: hdmi_dpll_clk_mux@164 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&sys_clkin2>;
reg = <0x0164>;
};
mlb_clk: mlb_clk@134 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&mlb_clkin_ck>;
ti,max-div = <64>;
reg = <0x0134>;
ti,index-power-of-two;
};
mlbp_clk: mlbp_clk@130 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&mlbp_clkin_ck>;
ti,max-div = <64>;
reg = <0x0130>;
ti,index-power-of-two;
};
per_abe_x1_gfclk2_div: per_abe_x1_gfclk2_div@138 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_abe_m2_ck>;
ti,max-div = <64>;
reg = <0x0138>;
ti,index-power-of-two;
};
timer_sys_clk_div: timer_sys_clk_div@144 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&sys_clkin1>;
reg = <0x0144>;
ti,max-div = <2>;
};
video1_dpll_clk_mux: video1_dpll_clk_mux@168 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&sys_clkin2>;
reg = <0x0168>;
};
video2_dpll_clk_mux: video2_dpll_clk_mux@16c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&sys_clkin2>;
reg = <0x016c>;
};
wkupaon_iclk_mux: wkupaon_iclk_mux@108 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&abe_lp_clk_div>;
reg = <0x0108>;
};
gpio1_dbclk: gpio1_dbclk@1838 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
ti,bit-shift = <8>;
reg = <0x1838>;
};
dcan1_sys_clk_mux: dcan1_sys_clk_mux@1888 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&sys_clkin2>;
ti,bit-shift = <24>;
reg = <0x1888>;
};
timer1_gfclk_mux: timer1_gfclk_mux@1840 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
ti,bit-shift = <24>;
reg = <0x1840>;
};
uart10_gfclk_mux: uart10_gfclk_mux@1880 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
ti,bit-shift = <24>;
reg = <0x1880>;
};
};
&cm_core_clocks {
dpll_pcie_ref_ck: dpll_pcie_ref_ck@200 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
clocks = <&sys_clkin1>, <&sys_clkin1>;
reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>;
};
dpll_pcie_ref_m2ldo_ck: dpll_pcie_ref_m2ldo_ck@210 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_pcie_ref_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
reg = <0x0210>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
};
apll_pcie_in_clk_mux: apll_pcie_in_clk_mux@4ae06118 {
compatible = "ti,mux-clock";
clocks = <&dpll_pcie_ref_m2ldo_ck>, <&pciesref_acs_clk_ck>;
#clock-cells = <0>;
reg = <0x021c 0x4>;
ti,bit-shift = <7>;
};
apll_pcie_ck: apll_pcie_ck@21c {
#clock-cells = <0>;
compatible = "ti,dra7-apll-clock";
clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>;
reg = <0x021c>, <0x0220>;
};
optfclk_pciephy1_32khz: optfclk_pciephy1_32khz@4a0093b0 {
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
#clock-cells = <0>;
reg = <0x13b0>;
ti,bit-shift = <8>;
};
optfclk_pciephy2_32khz: optfclk_pciephy2_32khz@4a0093b8 {
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
#clock-cells = <0>;
reg = <0x13b8>;
ti,bit-shift = <8>;
};
optfclk_pciephy_div: optfclk_pciephy_div@4a00821c {
compatible = "ti,divider-clock";
clocks = <&apll_pcie_ck>;
#clock-cells = <0>;
reg = <0x021c>;
ti,dividers = <2>, <1>;
ti,bit-shift = <8>;
ti,max-div = <2>;
};
optfclk_pciephy1_clk: optfclk_pciephy1_clk@4a0093b0 {
compatible = "ti,gate-clock";
clocks = <&apll_pcie_ck>;
#clock-cells = <0>;
reg = <0x13b0>;
ti,bit-shift = <9>;
};
optfclk_pciephy2_clk: optfclk_pciephy2_clk@4a0093b8 {
compatible = "ti,gate-clock";
clocks = <&apll_pcie_ck>;
#clock-cells = <0>;
reg = <0x13b8>;
ti,bit-shift = <9>;
};
optfclk_pciephy1_div_clk: optfclk_pciephy1_div_clk@4a0093b0 {
compatible = "ti,gate-clock";
clocks = <&optfclk_pciephy_div>;
#clock-cells = <0>;
reg = <0x13b0>;
ti,bit-shift = <10>;
};
optfclk_pciephy2_div_clk: optfclk_pciephy2_div_clk@4a0093b8 {
compatible = "ti,gate-clock";
clocks = <&optfclk_pciephy_div>;
#clock-cells = <0>;
reg = <0x13b8>;
ti,bit-shift = <10>;
};
apll_pcie_clkvcoldo: apll_pcie_clkvcoldo {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&apll_pcie_ck>;
clock-mult = <1>;
clock-div = <1>;
};
apll_pcie_clkvcoldo_div: apll_pcie_clkvcoldo_div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&apll_pcie_ck>;
clock-mult = <1>;
clock-div = <1>;
};
apll_pcie_m2_ck: apll_pcie_m2_ck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&apll_pcie_ck>;
clock-mult = <1>;
clock-div = <1>;
};
dpll_per_byp_mux: dpll_per_byp_mux@14c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&per_dpll_hs_clk_div>;
ti,bit-shift = <23>;
reg = <0x014c>;
};
dpll_per_ck: dpll_per_ck@140 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
clocks = <&sys_clkin1>, <&dpll_per_byp_mux>;
reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;
};
dpll_per_m2_ck: dpll_per_m2_ck@150 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_per_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
reg = <0x0150>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
};
func_96m_aon_dclk_div: func_96m_aon_dclk_div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&dpll_per_m2_ck>;
clock-mult = <1>;
clock-div = <1>;
};
dpll_usb_byp_mux: dpll_usb_byp_mux@18c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&usb_dpll_hs_clk_div>;
ti,bit-shift = <23>;
reg = <0x018c>;
};
dpll_usb_ck: dpll_usb_ck@180 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-j-type-clock";
clocks = <&sys_clkin1>, <&dpll_usb_byp_mux>;
reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>;
};
dpll_usb_m2_ck: dpll_usb_m2_ck@190 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_usb_ck>;
ti,max-div = <127>;
ti,autoidle-shift = <8>;
reg = <0x0190>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
};
dpll_pcie_ref_m2_ck: dpll_pcie_ref_m2_ck@210 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_pcie_ref_ck>;
ti,max-div = <127>;
ti,autoidle-shift = <8>;
reg = <0x0210>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
};
dpll_per_x2_ck: dpll_per_x2_ck {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-x2-clock";
clocks = <&dpll_per_ck>;
};
dpll_per_h11x2_ck: dpll_per_h11x2_ck@158 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_per_x2_ck>;
ti,max-div = <63>;
ti,autoidle-shift = <8>;
reg = <0x0158>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
};
dpll_per_h12x2_ck: dpll_per_h12x2_ck@15c {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_per_x2_ck>;
ti,max-div = <63>;
ti,autoidle-shift = <8>;
reg = <0x015c>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
};
dpll_per_h13x2_ck: dpll_per_h13x2_ck@160 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_per_x2_ck>;
ti,max-div = <63>;
ti,autoidle-shift = <8>;
reg = <0x0160>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
};
dpll_per_h14x2_ck: dpll_per_h14x2_ck@164 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_per_x2_ck>;
ti,max-div = <63>;
ti,autoidle-shift = <8>;
reg = <0x0164>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
};
dpll_per_m2x2_ck: dpll_per_m2x2_ck@150 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_per_x2_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
reg = <0x0150>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
};
dpll_usb_clkdcoldo: dpll_usb_clkdcoldo {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&dpll_usb_ck>;
clock-mult = <1>;
clock-div = <1>;
};
func_128m_clk: func_128m_clk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&dpll_per_h11x2_ck>;
clock-mult = <1>;
clock-div = <2>;
};
func_12m_fclk: func_12m_fclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&dpll_per_m2x2_ck>;
clock-mult = <1>;
clock-div = <16>;
};
func_24m_clk: func_24m_clk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&dpll_per_m2_ck>;
clock-mult = <1>;
clock-div = <4>;
};
func_48m_fclk: func_48m_fclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&dpll_per_m2x2_ck>;
clock-mult = <1>;
clock-div = <4>;
};
func_96m_fclk: func_96m_fclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&dpll_per_m2x2_ck>;
clock-mult = <1>;
clock-div = <2>;
};
l3init_60m_fclk: l3init_60m_fclk@104 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_usb_m2_ck>;
reg = <0x0104>;
ti,dividers = <1>, <8>;
};
clkout2_clk: clkout2_clk@6b0 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&clkoutmux2_clk_mux>;
ti,bit-shift = <8>;
reg = <0x06b0>;
};
l3init_960m_gfclk: l3init_960m_gfclk@6c0 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&dpll_usb_clkdcoldo>;
ti,bit-shift = <8>;
reg = <0x06c0>;
};
dss_32khz_clk: dss_32khz_clk@1120 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
ti,bit-shift = <11>;
reg = <0x1120>;
};
dss_48mhz_clk: dss_48mhz_clk@1120 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&func_48m_fclk>;
ti,bit-shift = <9>;
reg = <0x1120>;
};
dss_dss_clk: dss_dss_clk@1120 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&dpll_per_h12x2_ck>;
ti,bit-shift = <8>;
reg = <0x1120>;
ti,set-rate-parent;
};
dss_hdmi_clk: dss_hdmi_clk@1120 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&hdmi_dpll_clk_mux>;
ti,bit-shift = <10>;
reg = <0x1120>;
};
dss_video1_clk: dss_video1_clk@1120 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&video1_dpll_clk_mux>;
ti,bit-shift = <12>;
reg = <0x1120>;
};
dss_video2_clk: dss_video2_clk@1120 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&video2_dpll_clk_mux>;
ti,bit-shift = <13>;
reg = <0x1120>;
};
gpio2_dbclk: gpio2_dbclk@1760 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
ti,bit-shift = <8>;
reg = <0x1760>;
};
gpio3_dbclk: gpio3_dbclk@1768 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
ti,bit-shift = <8>;
reg = <0x1768>;
};
gpio4_dbclk: gpio4_dbclk@1770 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
ti,bit-shift = <8>;
reg = <0x1770>;
};
gpio5_dbclk: gpio5_dbclk@1778 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
ti,bit-shift = <8>;
reg = <0x1778>;
};
gpio6_dbclk: gpio6_dbclk@1780 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
ti,bit-shift = <8>;
reg = <0x1780>;
};
gpio7_dbclk: gpio7_dbclk@1810 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
ti,bit-shift = <8>;
reg = <0x1810>;
};
gpio8_dbclk: gpio8_dbclk@1818 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
ti,bit-shift = <8>;
reg = <0x1818>;
};
mmc1_clk32k: mmc1_clk32k@1328 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
ti,bit-shift = <8>;
reg = <0x1328>;
};
mmc2_clk32k: mmc2_clk32k@1330 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
ti,bit-shift = <8>;
reg = <0x1330>;
};
mmc3_clk32k: mmc3_clk32k@1820 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
ti,bit-shift = <8>;
reg = <0x1820>;
};
mmc4_clk32k: mmc4_clk32k@1828 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
ti,bit-shift = <8>;
reg = <0x1828>;
};
sata_ref_clk: sata_ref_clk@1388 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_clkin1>;
ti,bit-shift = <8>;
reg = <0x1388>;
};
usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m@13f0 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&l3init_960m_gfclk>;
ti,bit-shift = <8>;
reg = <0x13f0>;
};
usb_otg_ss2_refclk960m: usb_otg_ss2_refclk960m@1340 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&l3init_960m_gfclk>;
ti,bit-shift = <8>;
reg = <0x1340>;
};
usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k@640 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
ti,bit-shift = <8>;
reg = <0x0640>;
};
usb_phy2_always_on_clk32k: usb_phy2_always_on_clk32k@688 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
ti,bit-shift = <8>;
reg = <0x0688>;
};
usb_phy3_always_on_clk32k: usb_phy3_always_on_clk32k@698 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
ti,bit-shift = <8>;
reg = <0x0698>;
};
atl_dpll_clk_mux: atl_dpll_clk_mux@c00 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_32k_ck>, <&video1_clkin_ck>, <&video2_clkin_ck>, <&hdmi_clkin_ck>;
ti,bit-shift = <24>;
reg = <0x0c00>;
};
atl_gfclk_mux: atl_gfclk_mux@c00 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&l3_iclk_div>, <&dpll_abe_m2_ck>, <&atl_dpll_clk_mux>;
ti,bit-shift = <26>;
reg = <0x0c00>;
};
rmii_50mhz_clk_mux: rmii_50mhz_clk_mux@13d0 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&dpll_gmac_h11x2_ck>, <&rmii_clk_ck>;
ti,bit-shift = <24>;
reg = <0x13d0>;
};
gmac_rft_clk_mux: gmac_rft_clk_mux@13d0 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&video1_clkin_ck>, <&video2_clkin_ck>, <&dpll_abe_m2_ck>, <&hdmi_clkin_ck>, <&l3_iclk_div>;
ti,bit-shift = <25>;
reg = <0x13d0>;
};
gpu_core_gclk_mux: gpu_core_gclk_mux@1220 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
ti,bit-shift = <24>;
reg = <0x1220>;
assigned-clocks = <&gpu_core_gclk_mux>;
assigned-clock-parents = <&dpll_gpu_m2_ck>;
};
gpu_hyd_gclk_mux: gpu_hyd_gclk_mux@1220 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
ti,bit-shift = <26>;
reg = <0x1220>;
assigned-clocks = <&gpu_hyd_gclk_mux>;
assigned-clock-parents = <&dpll_gpu_m2_ck>;
};
l3instr_ts_gclk_div: l3instr_ts_gclk_div@e50 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&wkupaon_iclk_mux>;
ti,bit-shift = <24>;
reg = <0x0e50>;
ti,dividers = <8>, <16>, <32>;
};
mcasp2_ahclkr_mux: mcasp2_ahclkr_mux@1860 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
ti,bit-shift = <28>;
reg = <0x1860>;
};
mcasp2_ahclkx_mux: mcasp2_ahclkx_mux@1860 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
ti,bit-shift = <24>;
reg = <0x1860>;
};
mcasp2_aux_gfclk_mux: mcasp2_aux_gfclk_mux@1860 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
ti,bit-shift = <22>;
reg = <0x1860>;
};
mcasp3_ahclkx_mux: mcasp3_ahclkx_mux@1868 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
ti,bit-shift = <24>;
reg = <0x1868>;
assigned-clocks = <&mcasp3_ahclkx_mux>;
assigned-clock-parents = <&abe_24m_fclk>;
};
mcasp3_aux_gfclk_mux: mcasp3_aux_gfclk_mux@1868 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
ti,bit-shift = <22>;
reg = <0x1868>;
};
mcasp4_ahclkx_mux: mcasp4_ahclkx_mux@1898 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
ti,bit-shift = <24>;
reg = <0x1898>;
};
mcasp4_aux_gfclk_mux: mcasp4_aux_gfclk_mux@1898 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
ti,bit-shift = <22>;
reg = <0x1898>;
};
mcasp5_ahclkx_mux: mcasp5_ahclkx_mux@1878 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
ti,bit-shift = <24>;
reg = <0x1878>;
};
mcasp5_aux_gfclk_mux: mcasp5_aux_gfclk_mux@1878 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
ti,bit-shift = <22>;
reg = <0x1878>;
};
mcasp6_ahclkx_mux: mcasp6_ahclkx_mux@1904 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
ti,bit-shift = <24>;
reg = <0x1904>;
};
mcasp6_aux_gfclk_mux: mcasp6_aux_gfclk_mux@1904 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
ti,bit-shift = <22>;
reg = <0x1904>;
};
mcasp7_ahclkx_mux: mcasp7_ahclkx_mux@1908 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
ti,bit-shift = <24>;
reg = <0x1908>;
};
mcasp7_aux_gfclk_mux: mcasp7_aux_gfclk_mux@1908 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
ti,bit-shift = <22>;
reg = <0x1908>;
};
mcasp8_ahclkx_mux: mcasp8_ahclkx_mux@1890 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
ti,bit-shift = <22>;
reg = <0x1890>;
};
mcasp8_aux_gfclk_mux: mcasp8_aux_gfclk_mux@1890 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
ti,bit-shift = <24>;
reg = <0x1890>;
};
mmc1_fclk_mux: mmc1_fclk_mux@1328 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
ti,bit-shift = <24>;
reg = <0x1328>;
};
mmc1_fclk_div: mmc1_fclk_div@1328 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&mmc1_fclk_mux>;
ti,bit-shift = <25>;
ti,max-div = <4>;
reg = <0x1328>;
ti,index-power-of-two;
};
mmc2_fclk_mux: mmc2_fclk_mux@1330 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
ti,bit-shift = <24>;
reg = <0x1330>;
};
mmc2_fclk_div: mmc2_fclk_div@1330 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&mmc2_fclk_mux>;
ti,bit-shift = <25>;
ti,max-div = <4>;
reg = <0x1330>;
ti,index-power-of-two;
};
mmc3_gfclk_mux: mmc3_gfclk_mux@1820 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
ti,bit-shift = <24>;
reg = <0x1820>;
};
mmc3_gfclk_div: mmc3_gfclk_div@1820 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&mmc3_gfclk_mux>;
ti,bit-shift = <25>;
ti,max-div = <4>;
reg = <0x1820>;
ti,index-power-of-two;
};
mmc4_gfclk_mux: mmc4_gfclk_mux@1828 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
ti,bit-shift = <24>;
reg = <0x1828>;
};
mmc4_gfclk_div: mmc4_gfclk_div@1828 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&mmc4_gfclk_mux>;
ti,bit-shift = <25>;
ti,max-div = <4>;
reg = <0x1828>;
ti,index-power-of-two;
};
qspi_gfclk_mux: qspi_gfclk_mux@1838 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_128m_clk>, <&dpll_per_h13x2_ck>;
ti,bit-shift = <24>;
reg = <0x1838>;
};
qspi_gfclk_div: qspi_gfclk_div@1838 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&qspi_gfclk_mux>;
ti,bit-shift = <25>;
ti,max-div = <4>;
reg = <0x1838>;
ti,index-power-of-two;
};
timer10_gfclk_mux: timer10_gfclk_mux@1728 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
ti,bit-shift = <24>;
reg = <0x1728>;
};
timer11_gfclk_mux: timer11_gfclk_mux@1730 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
ti,bit-shift = <24>;
reg = <0x1730>;
};
timer13_gfclk_mux: timer13_gfclk_mux@17c8 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
ti,bit-shift = <24>;
reg = <0x17c8>;
};
timer14_gfclk_mux: timer14_gfclk_mux@17d0 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
ti,bit-shift = <24>;
reg = <0x17d0>;
};
timer15_gfclk_mux: timer15_gfclk_mux@17d8 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
ti,bit-shift = <24>;
reg = <0x17d8>;
};
timer16_gfclk_mux: timer16_gfclk_mux@1830 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
ti,bit-shift = <24>;
reg = <0x1830>;
assigned-clocks = <&timer16_gfclk_mux>;
assigned-clock-parents = <&abe_giclk_div>;
};
timer2_gfclk_mux: timer2_gfclk_mux@1738 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
ti,bit-shift = <24>;
reg = <0x1738>;
};
timer3_gfclk_mux: timer3_gfclk_mux@1740 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
ti,bit-shift = <24>;
reg = <0x1740>;
};
timer4_gfclk_mux: timer4_gfclk_mux@1748 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
ti,bit-shift = <24>;
reg = <0x1748>;
};
timer9_gfclk_mux: timer9_gfclk_mux@1750 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
ti,bit-shift = <24>;
reg = <0x1750>;
};
uart1_gfclk_mux: uart1_gfclk_mux@1840 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
ti,bit-shift = <24>;
reg = <0x1840>;
};
uart2_gfclk_mux: uart2_gfclk_mux@1848 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
ti,bit-shift = <24>;
reg = <0x1848>;
};
uart3_gfclk_mux: uart3_gfclk_mux@1850 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
ti,bit-shift = <24>;
reg = <0x1850>;
};
uart4_gfclk_mux: uart4_gfclk_mux@1858 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
ti,bit-shift = <24>;
reg = <0x1858>;
};
uart5_gfclk_mux: uart5_gfclk_mux@1870 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
ti,bit-shift = <24>;
reg = <0x1870>;
};
uart7_gfclk_mux: uart7_gfclk_mux@18d0 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
ti,bit-shift = <24>;
reg = <0x18d0>;
};
uart8_gfclk_mux: uart8_gfclk_mux@18e0 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
ti,bit-shift = <24>;
reg = <0x18e0>;
};
uart9_gfclk_mux: uart9_gfclk_mux@18e8 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
ti,bit-shift = <24>;
reg = <0x18e8>;
};
vip1_gclk_mux: vip1_gclk_mux@1020 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
ti,bit-shift = <24>;
reg = <0x1020>;
};
vip2_gclk_mux: vip2_gclk_mux@1028 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
ti,bit-shift = <24>;
reg = <0x1028>;
};
vip3_gclk_mux: vip3_gclk_mux@1030 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
ti,bit-shift = <24>;
reg = <0x1030>;
};
};
&cm_core_clockdomains {
coreaon_clkdm: coreaon_clkdm {
compatible = "ti,clockdomain";
clocks = <&dpll_usb_ck>;
};
};
&scm_conf_clocks {
dss_deshdcp_clk: dss_deshdcp_clk@558 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&l3_iclk_div>;
ti,bit-shift = <0>;
reg = <0x558>;
};
ehrpwm0_tbclk: ehrpwm0_tbclk@558 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&l4_root_clk_div>;
ti,bit-shift = <20>;
reg = <0x0558>;
};
ehrpwm1_tbclk: ehrpwm1_tbclk@558 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&l4_root_clk_div>;
ti,bit-shift = <21>;
reg = <0x0558>;
};
ehrpwm2_tbclk: ehrpwm2_tbclk@558 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&l4_root_clk_div>;
ti,bit-shift = <22>;
reg = <0x0558>;
};
sys_32k_ck: sys_32k_ck {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clk32_crystal_ck>, <&sys_clk32_pseudo_ck>, <&sys_clk32_pseudo_ck>, <&sys_clk32_pseudo_ck>;
ti,bit-shift = <8>;
reg = <0x6c4>;
};
};
Filename 'am571x-idk.dtb'.
Load address: 0x88000000
Loading: #######
2.4 MiB/s
done
Bytes transferred = 98581 (18115 hex)
## Flattened Device Tree blob at 88000000
Booting using the fdt blob at 0x88000000
Loading Device Tree to 8ffe4000, end 8ffff114 ... OK
Starting kernel ...
[ 0.000000] Booting Linux on physical CPU 0x0
[ 0.000000] Linux version 4.14.79-ge669d52447 (bcg@BCGI142) (gcc version 7.29
[ 0.000000] CPU: ARMv7 Processor [412fc0f2] revision 2 (ARMv7), cr=30c5387d
[ 0.000000] CPU: div instructions available: patching division code
[ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, PIPT instruction cache
[ 0.000000] OF: fdt: Machine model: TI AM5718 IDK
[ 0.000000] Memory policy: Data cache writealloc
[ 0.000000] efi: Getting EFI parameters from FDT:
[ 0.000000] efi: UEFI not found.
[ 0.000000] Reserved memory: created CMA memory pool at 0x0000000095800000, B
[ 0.000000] OF: reserved mem: initialized node ipu2-memory@95800000, compatil
[ 0.000000] Reserved memory: created CMA memory pool at 0x0000000099000000, B
[ 0.000000] OF: reserved mem: initialized node dsp1-memory@99000000, compatil
[ 0.000000] Reserved memory: created CMA memory pool at 0x000000009d000000, B
[ 0.000000] OF: reserved mem: initialized node ipu1-memory@9d000000, compatil
[ 0.000000] cma: Reserved 24 MiB at 0x00000000be400000
[ 0.000000] OMAP4: Map 0x00000000bfd00000 to fe600000 for dram barrier
[ 0.000000] DRA722 ES2.0
[ 0.000000] percpu: Embedded 15 pages/cpu @ef648000 s31372 r8192 d21876 u6140
[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 210496
[ 0.000000] Kernel command line: console=ttyO2,115200n8 root=/dev/nfs nfsroop
[ 0.000000] PID hash table entries: 4096 (order: 2, 16384 bytes)
[ 0.000000] Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)
[ 0.000000] Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
[ 0.000000] Memory: 644568K/848896K available (8192K kernel code, 350K rwdat)
[ 0.000000] Virtual kernel memory layout:
[ 0.000000] vector : 0xffff0000 - 0xffff1000 ( 4 kB)
[ 0.000000] fixmap : 0xffc00000 - 0xfff00000 (3072 kB)
[ 0.000000] vmalloc : 0xf0800000 - 0xff800000 ( 240 MB)
[ 0.000000] lowmem : 0xc0000000 - 0xf0000000 ( 768 MB)
[ 0.000000] pkmap : 0xbfe00000 - 0xc0000000 ( 2 MB)
[ 0.000000] modules : 0xbf000000 - 0xbfe00000 ( 14 MB)
[ 0.000000] .text : 0xc0008000 - 0xc0a00000 (10208 kB)
[ 0.000000] .init : 0xc0e00000 - 0xc1000000 (2048 kB)
[ 0.000000] .data : 0xc1000000 - 0xc10578d8 ( 351 kB)
[ 0.000000] .bss : 0xc1059000 - 0xc109fbe0 ( 283 kB)
[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
[ 0.000000] Preemptible hierarchical RCU implementation.
[ 0.000000] RCU restricting CPUs from NR_CPUS=2 to nr_cpu_ids=1.
[ 0.000000] Tasks RCU enabled.
[ 0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
[ 0.000000] GIC: Using split EOI/Deactivate mode
[ 0.000000] OMAP clockevent source: timer1 at 32786 Hz
[ 0.000000] arch_timer: cp15 timer(s) running at 6.14MHz (phys).
[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycless
[ 0.000005] sched_clock: 56 bits at 6MHz, resolution 162ns, wraps every 4398s
[ 0.000017] Switching to timer-based delay loop, resolution 162ns
[ 0.000347] clocksource: 32k_counter: mask: 0xffffffff max_cycles: 0xfffffffs
[ 0.000356] OMAP clocksource: 32k_counter at 32768 Hz
[ 0.000811] Console: colour dummy device 80x30
[ 0.000829] WARNING: Your 'console=ttyO2' has been replaced by 'ttyS2'
[ 0.000837] This ensures that you still see kernel messages. Please
[ 0.000844] update your kernel commandline.
[ 0.000864] Calibrating delay loop (skipped), value calculated using timer f)
[ 0.000879] pid_max: default: 32768 minimum: 301
[ 0.000993] Mount-cache hash table entries: 2048 (order: 1, 8192 bytes)
[ 0.001007] Mountpoint-cache hash table entries: 2048 (order: 1, 8192 bytes)
[ 0.001531] CPU: Testing write buffer coherency: ok
[ 0.001568] CPU0: Spectre v2: using ICIALLU workaround
[ 0.001768] /cpus/cpu@0 missing clock-frequency property
[ 0.001782] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
[ 0.039847] Setting up static identity map for 0x80200000 - 0x80200060
[ 0.059854] Hierarchical SRCU implementation.
[ 0.080038] EFI services will not be available.
[ 0.099910] smp: Bringing up secondary CPUs ...
[ 0.099920] smp: Brought up 1 node, 1 CPU
[ 0.099930] SMP: Total of 1 processors activated (12.29 BogoMIPS).
[ 0.099937] CPU: All CPU(s) started in HYP mode.
[ 0.099944] CPU: Virtualization extensions available.
[ 0.100366] devtmpfs: initialized
[ 0.118436] random: get_random_u32 called from bucket_table_alloc+0x108/0x230
[ 0.120057] VFP support v0.3: implementor 41 architecture 4 part 30 variant 0
[ 0.120257] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, ms
[ 0.120275] futex hash table entries: 256 (order: 2, 16384 bytes)
[ 0.124020] pinctrl core: initialized pinctrl subsystem
[ 0.124512] DMI not present or invalid.
[ 0.124764] NET: Registered protocol family 16
[ 0.130820] DMA: preallocated 256 KiB pool for atomic coherent allocations
[ 0.131678] omap_hwmod: l3_main_2 using broken dt data from ocp
[ 0.325737] cpuidle: using governor ladder
[ 0.325771] cpuidle: using governor menu
[ 0.334252] OMAP GPIO hardware version 0.1
[ 0.362491] No ATAGs?
[ 0.362539] hw-breakpoint: found 5 (+1 reserved) breakpoint and 4 watchpoint.
[ 0.362553] hw-breakpoint: maximum watchpoint size is 8 bytes.
[ 0.362942] omap4_sram_init:Unable to allocate sram needed to handle errata 8
[ 0.362953] omap4_sram_init:Unable to get sram pool needed to handle errata 8
[ 0.363501] OMAP DMA hardware revision 0.0
[ 0.402757] edma 43300000.edma: memcpy is disabled
[ 0.406029] edma 43300000.edma: TI EDMA DMA engine driver
[ 0.412985] omap-dma-engine 4a056000.dma-controller: OMAP DMA engine driver )
[ 0.417198] omap-iommu 40d01000.mmu: 40d01000.mmu registered
[ 0.417405] omap-iommu 40d02000.mmu: 40d02000.mmu registered
[ 0.417657] omap-iommu 58882000.mmu: 58882000.mmu registered
[ 0.417904] omap-iommu 55082000.mmu: 55082000.mmu registered
[ 0.418240] iommu: Adding device 58820000.ipu to group 1
[ 0.418325] iommu: Adding device 55020000.ipu to group 2
[ 0.418477] iommu: Adding device 40800000.dsp to group 0
[ 0.420923] palmas 0-0058: Irq flag is 0x00000004
[ 0.452602] palmas 0-0058: Muxing GPIO 2f, PWM 0, LED 0
[ 0.454231] SMPS12: supplied by regulator-dummy
[ 0.456055] SMPS3: supplied by VMAIN
[ 0.457693] SMPS45: supplied by regulator-dummy
[ 0.459624] SMPS6: supplied by VMAIN
[ 0.461392] SMPS7: supplied by VMAIN
[ 0.463331] SMPS8: supplied by VMAIN
[ 0.464697] SMPS9: supplied by VMAIN
[ 0.465755] LDO1: supplied by VMAIN
[ 0.471751] LDO2: supplied by VMAIN
[ 0.471802] random: fast init done
[ 0.481618] LDO3: supplied by VMAIN
[ 0.491625] LDO4: supplied by VMAIN
[ 0.501631] LDO5: supplied by regulator-dummy
[ 0.502435] LDO6: supplied by regulator-dummy
[ 0.503227] LDO7: supplied by regulator-dummy
[ 0.504020] LDO8: supplied by regulator-dummy
[ 0.504823] LDO9: supplied by VMAIN
[ 0.511986] LDOLN: supplied by VMAIN
[ 0.521687] LDOUSB: supplied by VMAIN
[ 0.535005] omap_i2c 48070000.i2c: bus 0 rev0.12 at 400 kHz
[ 0.535231] media: Linux media interface: v0.10
[ 0.535270] Linux video capture interface: v2.00
[ 0.535352] pps_core: LinuxPPS API ver. 1 registered
[ 0.535361] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giom>
[ 0.535381] PTP clock support registered
[ 0.535412] EDAC MC: Ver: 3.0.0
[ 0.541075] dmi: Firmware registration failed.
[ 0.541512] omap-mailbox 48840000.mailbox: omap mailbox rev 0x400
[ 0.541720] omap-mailbox 48842000.mailbox: omap mailbox rev 0x400
[ 0.542097] Advanced Linux Sound Architecture Driver Initialized.
[ 0.551155] clocksource: Switched to clocksource arch_sys_counter
[ 0.558670] NET: Registered protocol family 2
[ 0.559207] TCP established hash table entries: 8192 (order: 3, 32768 bytes)
[ 0.559272] TCP bind hash table entries: 8192 (order: 4, 65536 bytes)
[ 0.559397] TCP: Hash tables configured (established 8192 bind 8192)
[ 0.559467] UDP hash table entries: 512 (order: 2, 16384 bytes)
[ 0.559500] UDP-Lite hash table entries: 512 (order: 2, 16384 bytes)
[ 0.559620] NET: Registered protocol family 1
[ 0.579974] RPC: Registered named UNIX socket transport module.
[ 0.579984] RPC: Registered udp transport module.
[ 0.579992] RPC: Registered tcp transport module.
[ 0.579999] RPC: Registered tcp NFSv4.1 backchannel transport module.
[ 0.580922] hw perfevents: no interrupt-affinity property for /pmu, guessing.
[ 0.581055] hw perfevents: enabled with armv7_cortex_a15 PMU driver, 7 counte
[ 0.582129] workingset: timestamp_bits=14 max_order=18 bucket_order=4
[ 0.586254] squashfs: version 4.0 (2009/01/31) Phillip Lougher
[ 0.596796] NFS: Registering the id_resolver key type
[ 0.596820] Key type id_resolver registered
[ 0.596829] Key type id_legacy registered
[ 0.596865] ntfs: driver 2.1.32 [Flags: R/O].
[ 0.598504] bounce: pool size: 64 pages
[ 0.598551] Block layer SCSI generic (bsg) driver version 0.4 loaded (major )
[ 0.598562] io scheduler noop registered
[ 0.598571] io scheduler deadline registered
[ 0.598666] io scheduler cfq registered (default)
[ 0.598676] io scheduler mq-deadline registered
[ 0.598685] io scheduler kyber registered
[ 0.603383] pinctrl-single 4a003400.pinmux: 282 pins at pa fc003400 size 1128
[ 0.603533] pinctrl-single 4a002e8c.pinmux: please update dts to use #pinctr>
[ 0.603607] pinctrl-single 4a002e8c.pinmux: initialized with no interrupts
[ 0.603619] pinctrl-single 4a002e8c.pinmux: 1 pins at pa fc002e8c size 4
[ 0.616475] dra7-pcie 51000000.pcie: Linked as a consumer to phy-4a094000.pc1
[ 0.616867] OF: PCI: host bridge /ocp/axi@0/pcie@51000000 ranges:
[ 0.616902] OF: PCI: IO 0x20003000..0x20012fff -> 0x00000000
[ 0.616925] OF: PCI: MEM 0x20013000..0x2fffffff -> 0x20013000
[ 1.617180] dra7-pcie 51000000.pcie: phy link never came up
[ 1.617318] dra7-pcie 51000000.pcie: PCI host bridge to bus 0000:00
[ 1.617332] pci_bus 0000:00: root bus resource [bus 00-ff]
[ 1.617343] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
[ 1.617353] pci_bus 0000:00: root bus resource [mem 0x20013000-0x2fffffff]
[ 1.617671] PCI: bus0: Fast back to back transfers disabled
[ 1.617760] PCI: bus1: Fast back to back transfers enabled
[ 1.617797] pci 0000:00:00.0: BAR 0: assigned [mem 0x20100000-0x201fffff 64b]
[ 1.617815] pci 0000:00:00.0: PCI bridge to [bus 01-ff]
[ 1.618146] pcieport 0000:00:00.0: Signaling PME with IRQ 172
[ 1.618271] pcieport 0000:00:00.0: AER enabled with IRQ 172
[ 1.621421] V3_3D: supplied by smps9
[ 1.621701] vtt_fixed: supplied by V3_3D
[ 1.621790] vdd_3v3: supplied by regen1
[ 1.622030] aic_dvdd_fixed: supplied by vdd_3v3
[ 1.664590] Serial: 8250/16550 driver, 10 ports, IRQ sharing disabled
[ 1.667343] 48020000.serial: ttyS2 at MMIO 0x48020000 (irq = 45, base_baud =0
[ 2.721817] console [ttyS2] enabled
[ 2.727273] omap_rng 48090000.rng: Random Number Generator ver. 20
[ 2.734395] DSS: OMAP DSS rev 6.1
[ 2.739419] omapdss_dss 58000000.dss: bound 58001000.dispc (ops dispc_compon)
[ 2.747895] omapdss_dss 58000000.dss: bound 58040000.encoder (ops hdmi5_comp)
[ 2.768190] brd: module loaded
[ 2.776719] loop: module loaded
[ 2.784073] m25p80 spi0.0: s25fl256s1 (32768 Kbytes)
[ 2.789118] 7 ofpart partitions found on MTD device spi0.0
[ 2.794709] Creating 7 MTD partitions on "spi0.0":
[ 2.799524] 0x000000000000-0x000000040000 : "QSPI.SPL"
[ 2.805377] 0x000000040000-0x000000140000 : "QSPI.u-boot"
[ 2.811455] 0x000000140000-0x0000001c0000 : "QSPI.u-boot-spl-os"
[ 2.818110] 0x0000001c0000-0x0000001d0000 : "QSPI.u-boot-env"
[ 2.824504] 0x0000001d0000-0x0000001e0000 : "QSPI.u-boot-env.backup1"
[ 2.831607] 0x0000001e0000-0x0000009e0000 : "QSPI.kernel"
[ 2.837636] 0x0000009e0000-0x000002000000 : "QSPI.file-system"
[ 2.844729] libphy: Fixed MDIO Bus: probed
[ 2.911188] davinci_mdio 48485000.mdio: davinci mdio revision 1.6, bus freq 0
[ 2.918883] davinci_mdio 48485000.mdio: detected phy mask fffffffc
[ 2.939880] libphy: 48485000.mdio: probed
[ 2.943965] davinci_mdio 48485000.mdio: phy[0]: device 48485000.mdio:00, driY
[ 2.953704] davinci_mdio 48485000.mdio: phy[1]: device 48485000.mdio:01, driY
[ 2.964294] cpsw 48484000.ethernet: Detected MACID = 44:ea:d8:17:d8:d6
[ 2.970906] cpsw 48484000.ethernet: initialized cpsw ale version 1.4
[ 2.977342] cpsw 48484000.ethernet: ALE Table size 1024
[ 2.982637] cpsw 48484000.ethernet: device node lookup for pps timer failed
[ 2.989666] cpsw 48484000.ethernet: cpts: overflow check period 500 (jiffies)
[ 2.997568] cpsw 48484000.ethernet: cpsw: Detected MACID = 44:ea:d8:17:d8:d7
[ 3.005839] i2c /dev entries driver
[ 3.010086] IR NEC protocol handler initialized
[ 3.014665] IR RC5(x/sz) protocol handler initialized
[ 3.019737] IR RC6 protocol handler initialized
[ 3.024300] IR JVC protocol handler initialized
[ 3.028848] IR Sony protocol handler initialized
[ 3.033636] IR SANYO protocol handler initialized
[ 3.038360] IR Sharp protocol handler initialized
[ 3.043097] IR MCE Keyboard/mouse protocol handler initialized
[ 3.048953] IR XMP protocol handler initialized
[ 3.059163] sdhci: Secure Digital Host Controller Interface driver
[ 3.065475] sdhci: Copyright(c) Pierre Ossman
[ 3.070936] sdhci-pltfm: SDHCI platform and OF driver helper
[ 3.077396] sdhci-omap 4809c000.mmc: Got CD GPIO
[ 3.082799] sdhci-omap 4809c000.mmc: no pinctrl state for ddr_1_8v mode
[ 3.089442] sdhci-omap 4809c000.mmc: no pinctrl state for hs200_1_8v mode
[ 3.151367] mmc0: SDHCI controller on 4809c000.mmc [4809c000.mmc] using ADMA
[ 3.211305] mmc1: SDHCI controller on 480b4000.mmc [480b4000.mmc] using ADMA
[ 3.223508] ledtrig-cpu: registered to indicate activity on CPUs
[ 3.238242] NET: Registered protocol family 10
[ 3.253920] Segment Routing with IPv6
[ 3.257759] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
[ 3.264276] NET: Registered protocol family 17
[ 3.268944] Key type dns_resolver registered
[ 3.273516] omap_voltage_late_init: Voltage driver support not added
[ 3.279940] Power Management for TI OMAP4+ devices.
[ 3.285280] Registering SWP/SWPB emulation handler
[ 3.299192] dmm 4e000000.dmm: workaround for errata i878 in use
[ 3.306650] dmm 4e000000.dmm: initialized all PAT entries
[ 3.313641] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
[ 3.320317] [drm] No driver support for vblank timestamp query.
[ 3.326351] [drm] Cannot find any crtc or sizes
[ 3.331295] ti-iodelay 4844a000.padconf: Set reg 0x18c Delay(a: 0 g: 0), Ele0
[ 3.340206] ti-iodelay 4844a000.padconf: Set reg 0x1a4 Delay(a: 119 g: 0), E3
[ 3.349806] [drm] Initialized omapdrm 1.0.0 20110917 for omapdrm.0 on minor 0
[ 3.357048] ti-iodelay 4844a000.padconf: Set reg 0x1b0 Delay(a: 0 g: 0), Ele0
[ 3.365986] ti-iodelay 4844a000.padconf: Set reg 0x1bc Delay(a: 18 g: 0), El0
[ 3.375008] ti-iodelay 4844a000.padconf: Set reg 0x1c8 Delay(a: 894 g: 0), Eb
[ 3.384189] ti-iodelay 4844a000.padconf: Set reg 0x1d4 Delay(a: 30 g: 0), El0
[ 3.393195] ti-iodelay 4844a000.padconf: Set reg 0x1e0 Delay(a: 0 g: 0), Ele0
[ 3.402112] ti-iodelay 4844a000.padconf: Set reg 0x1ec Delay(a: 23 g: 0), El0
[ 3.411109] ti-iodelay 4844a000.padconf: Set reg 0x1f8 Delay(a: 0 g: 0), Ele0
[ 3.420027] ti-iodelay 4844a000.padconf: Set reg 0x360 Delay(a: 0 g: 0), Ele0
[ 3.428948] ti-iodelay 4844a000.padconf: Set reg 0x194 Delay(a: 152 g: 0), E4
[ 3.438040] ti-iodelay 4844a000.padconf: Set reg 0x1ac Delay(a: 206 g: 0), E5
[ 3.447133] ti-iodelay 4844a000.padconf: Set reg 0x1b8 Delay(a: 78 g: 0), El2
[ 3.456138] ti-iodelay 4844a000.padconf: Set reg 0x1c4 Delay(a: 2 g: 0), Ele0
[ 3.465055] ti-iodelay 4844a000.padconf: Set reg 0x1d0 Delay(a: 266 g: 0), E7
[ 3.474147] ti-iodelay 4844a000.padconf: Set reg 0x1dc Delay(a: 0 g: 0), Ele0
[ 3.483065] ti-iodelay 4844a000.padconf: Set reg 0x1e8 Delay(a: 0 g: 0), Ele0
[ 3.491982] ti-iodelay 4844a000.padconf: Set reg 0x1f4 Delay(a: 43 g: 0), El1
[ 3.500979] ti-iodelay 4844a000.padconf: Set reg 0x200 Delay(a: 0 g: 0), Ele0
[ 3.509896] ti-iodelay 4844a000.padconf: Set reg 0x368 Delay(a: 0 g: 0), Ele0
[ 3.518814] ti-iodelay 4844a000.padconf: Set reg 0x190 Delay(a: 0 g: 0), Ele0
[ 3.527731] ti-iodelay 4844a000.padconf: Set reg 0x1a8 Delay(a: 0 g: 0), Ele0
[ 3.536649] ti-iodelay 4844a000.padconf: Set reg 0x1b4 Delay(a: 0 g: 0), Ele0
[ 3.545566] ti-iodelay 4844a000.padconf: Set reg 0x1c0 Delay(a: 0 g: 0), Ele0
[ 3.554488] ti-iodelay 4844a000.padconf: Set reg 0x1d8 Delay(a: 0 g: 0), Ele0
[ 3.563408] ti-iodelay 4844a000.padconf: Set reg 0x1e4 Delay(a: 0 g: 0), Ele0
[ 3.572325] ti-iodelay 4844a000.padconf: Set reg 0x1f0 Delay(a: 0 g: 0), Ele0
[ 3.581241] ti-iodelay 4844a000.padconf: Set reg 0x1fc Delay(a: 0 g: 0), Ele0
[ 3.590149] ti-iodelay 4844a000.padconf: Set reg 0x364 Delay(a: 0 g: 0), Ele0
[ 3.600131] hctosys: unable to open rtc device (rtc0)
[ 3.606683] net eth0: initializing cpsw version 1.15 (0)
[ 3.687989] mmc1: new DDR MMC card at address 0001
[ 3.693110] mmcblk1: mmc1:0001 R1J56L 13.8 GiB
[ 3.697799] mmcblk1boot0: mmc1:0001 R1J56L partition 1 4.00 MiB
[ 3.703948] mmcblk1boot1: mmc1:0001 R1J56L partition 2 4.00 MiB
[ 3.710169] mmcblk1rpmb: mmc1:0001 R1J56L partition 3 128 KiB
[ 3.717012] mmcblk1: p1 p2
[ 3.739406] Micrel KSZ9031 Gigabit PHY 48485000.mdio:00: attached PHY driver)
[ 3.760323] IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
[ 3.766602] net eth1: initializing cpsw version 1.15 (0)
[ 3.891899] Micrel KSZ9031 Gigabit PHY 48485000.mdio:01: attached PHY driver)
[ 3.910712] IPv6: ADDRCONF(NETDEV_UP): eth1: link is not ready
[ 4.401205] [drm] Cannot find any crtc or sizes
[ 5.849788] cpsw 48484000.ethernet eth0: Link is Up - 100Mbps/Full - flow cox
[ 5.861187] IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready
[ 5.891175] Sending DHCP requests ., OK
[ 5.975076] IP-Config: Got DHCP answer from 10.176.16.1, my address is 10.178
[ 5.982892] IP-Config: Complete:
[ 5.986138] device=eth0, hwaddr=44:ea:d8:17:d8:d6, ipaddr=10.176.17.2481
[ 5.996440] host=10.176.17.248, domain=tvm.cdac.in, nis-domain=(none)
[ 6.003437] bootserver=0.0.0.0, rootserver=10.176.16.111, rootpath= 1
[ 6.023786] aic_dvdd_fixed: disabling
[ 6.027628] ALSA device list:
[ 6.030605] No soundcards found.
[ 6.197662] VFS: Mounted root (nfs filesystem) on device 0:15.
[ 6.204120] devtmpfs: mounted
[ 6.208349] Freeing unused kernel memory: 2048K
[ 6.948975] systemd[1]: System time before build time, advancing clock.
[ 7.027661] systemd[1]: systemd 234 running in system mode. (+PAM -AUDIT -SE)
[ 7.049625] systemd[1]: Detected architecture arm.
Welcome to Arago 2018.10!
[ 7.112872] systemd[1]: Set hostname to <am57xx-evm>.
[ 7.637935] random: crng init done
[ 7.816590] systemd[1]: Reached target Remote File Systems.
[ OK ] Reached target Remote File Systems.
[ 7.971469] systemd[1]: Listening on Journal Socket (/dev/log).
[ OK ] Listening on Journal Socket (/dev/log).
[ 8.030776] systemd[1]: Listening on Process Core Dump Socket.
[ OK ] Listening on Process Core Dump Socket.
[ 8.061684] systemd[1]: Listening on Syslog Socket.
[ OK ] Listening on Syslog Socket.
[ 8.091349] systemd[1]: Listening on udev Kernel Socket.
[ OK ] Listening on udev Kernel Socket.
[ 8.122880] systemd[1]: Created slice System Slice.
[ OK ] Created slice System Slice.
[ 8.152190] systemd[1]: Created slice system-getty.slice.
[ OK ] Created slice system-getty.slice.
Mounting Kernel Debug File System...
[ OK ] Listening on udev Control Socket.
[ OK ] Created slice system-serial\x2dgetty.slice.
[ OK ] Listening on /dev/initctl Compatibility Named Pipe.
[ OK ] Listening on Network Service Netlink Socket.
Mounting POSIX Message Queue File System...
[ OK ] Reached target Swap.
Mounting Temporary Directory (/tmp)...
[ OK ] Listening on Journal Socket.
Starting Journal Service...
Starting Load Kernel Modules...
[ OK ] Started Dispatch Password Requests to Console Directory Watch.
Starting Create list of required st��ce nodes for the current kernel. .
[ OK ] Started Forward Password Requests to Wall Directory Watch.
[ 8.615260] cmemk: loading out-of-tree module taints kernel.
[ OK ] Reached target Paths.
[ 8.631579] CMEMK module: reference Linux version 4.14.79
[ 8.641606] cmemk initialized
[ OK ] Created slice User and Session Slice.
[ OK ] Reached target Slices.
[ 8.683771] cryptodev: driver 1.9 loaded.
Starting Remount Root and Kernel File Systems...
[ OK ] Mounted Kernel Debug File System.
[ OK ] Mounted POSIX Message Queue File System.
[ 8.763626] usbcore: registered new interface driver usbfs
[ 8.769170] usbcore: registered new interface driver hub
[ OK ] Mounted Temporary Directory (/tmp).
[ 8.785846] usbcore: registered new device driver usb
[ OK ] Started Journal Service.
[ 8.822467] usbcore: registered new interface driver usbserial
[ OK ] Started Create list of required sta��…vice nodes for the current kerne.
[ 8.853057] usbcore: registered new interface driver ftdi_sio
[ 8.859866] usbserial: USB Serial support registered for FTDI USB Serial Deve
[ OK ] Started Remount Root and Kernel File Systems.
[ OK ] Started Load Kernel Modules.
Starting Apply Kernel Variables...
Mounting Kernel Configuration File System...
Starting udev Coldplug all Devices...
Starting Create Static Device Nodes in /dev...
Starting Flush Journal to Persistent Storage...
[ OK ] Mounted Kernel Configuration File System.
[ OK ] Started Apply Kernel Variables.
[ 9.207453] systemd-journald[77]: Received request to flush runtime journal 1
[ OK ] Started Flush Journal to Persistent Storage.
[ OK ] Started Create Static Device Nodes in /dev.
[ OK ] Reached target Local File Systems (Pre).
Mounting /media/ram...
Mounting /var/volatile...
Starting udev Kernel Device Manager...
[ OK ] Mounted /var/volatile.
[ OK ] Mounted /media/ram.
Starting Load/Save Random Seed...
[ OK ] Reached target Local File Systems.
Starting Create Volatile Files and Directories...
[ OK ] Started Load/Save Random Seed.
[ OK ] Started Create Volatile Files and Directories.
Starting Update UTMP about System Boot/Shutdown...
Starting Network Time Synchronization...
[ OK ] Started udev Kernel Device Manager.
[ OK ] Started Update UTMP about System Boot/Shutdown.
[ OK ] Started Network Time Synchronization.
[ OK ] Reached target System Time Synchronized.
[ OK ] Started udev Coldplug all Devices.
[ OK ] Reached target System Initialization.
Starting Network Service...
[ OK ] Started Daily Cleanup of Temporary Directories.
[ OK ] Listening on dropbear.socket.
[ OK ] Listening on RPCbind Server Activation Socket.
[ 10.548298] omap-rproc 58820000.ipu: assigned reserved memory node ipu1-memo0
[ OK ] Listening on D-Bus System Message Bus Socket.[ 10.633092] remoteproce
[ OK ] Started Daily rotation of log files.
[ 10.725016] omap-rproc 55020000.ipu: assigned reserved memory node ipu2-memo0
[ OK ] Reached target Timers.
[ 10.781765] remoteproc remoteproc1: 55020000.ipu is available
[ 10.807978] omap-rproc 40800000.dsp: assigned reserved memory node dsp1-memo0
[ 10.827329] remoteproc remoteproc2: 40800000.dsp is available
[ OK ] Listening on Avahi mDNS/DNS-SD Stack Activation Socket.
[ OK ] Reached target Sockets.
[ OK ] Reached target Basic System.
[ OK ] Reached target Containers.
Starting Print notice about GPLv3 packages...
Starting TI IPC Daemon...
[ OK ] Started Hardware RNG Entropy Gatherer Daemon.
[ OK ] Started Job spooling tools.
Starting RPC Bind Service...
Starting Login Service...
[ OK ] Started Periodic Command Scheduler.
Starting uim-sysfs.service...
Starting TI MultiCore Tools Daemon...
Starting Avahi mDNS/DNS-SD Stack...
[ OK ] Started System Logging Service.
[ OK ] Started Kernel Logging Service.
[ OK ] Started D-Bus System Message Bus.
[ 12.182469] remoteproc remoteproc1: powering up 55020000.ipu
[ 12.188165] remoteproc remoteproc1: Booting fw image dra7-ipu2-fw.xem4, size0
[ 12.256403] omap-iommu 55082000.mmu: 55082000.mmu: version 2.1
[ 12.421521] virtio_rpmsg_bus virtio0: rpmsg host is online
[ 12.441364] remoteproc remoteproc1: registered virtio0 (type 7)
[ 12.447310] remoteproc remoteproc1: remote processor 55020000.ipu is now up
[ 12.477192] virtio_rpmsg_bus virtio0: creating channel rpmsg-rpc addr 0x65
[ 12.504707] virtio_rpmsg_bus virtio0: creating channel rpmsg-rpc addr 0x66
[ 12.646874] palmas-rtc 48070000.i2c:tps659038@58:tps659038_rtc: rtc core: re0
[ 12.684800] asoc-simple-card sound0: tlv320aic3x-hifi <-> 48468000.mcasp mapk
[ 12.684819] asoc-simple-card sound0: ASoC: no sink widget found for MIC2L
[ 12.684823] asoc-simple-card sound0: ASoC: Failed to add route Line In -> diL
[ 12.684828] asoc-simple-card sound0: ASoC: no sink widget found for MIC2R
[ 12.684832] asoc-simple-card sound0: ASoC: Failed to add route Line In -> diR
[ 12.684835] asoc-simple-card sound0: ASoC: no DMI vendor name!
[ 12.871600] ov2659 0-0030: Sensor detection failed (3030, 0)
[ 12.931294] omap-des 480a5000.des: OMAP DES hw accel rev: 2.2
[ 12.934743] omap-des 480a5000.des: will run requests pump with realtime prioy
[ 13.046275] omap_gpio 4805b000.gpio: Could not set line 7 debounce to 20000 )
[ 13.447541] remoteproc remoteproc0: powering up 58820000.ipu
[ 13.505404] remoteproc remoteproc0: Booting fw image dra7-ipu1-fw.xem4, size6
[ 13.543778] omap-iommu 58882000.mmu: 58882000.mmu: version 2.1
[ 13.620035] omap_rtc 48838000.rtc: registered as rtc1
[ 13.722417] virtio_rpmsg_bus virtio1: rpmsg host is online
[ 13.798855] remoteproc remoteproc0: registered virtio1 (type 7)
[ 13.857957] remoteproc remoteproc0: remote processor 58820000.ipu is now up
[ 13.933200] virtio_rpmsg_bus virtio1: creating channel rpmsg-proto addr 0x3d
[ 14.128566] vpe 489d0000.vpe: loading firmware vpdma-1b8.bin
[ 14.201406] vpe 489d0000.vpe: Device registered as /dev/video0
[ 14.459336] vip 48970000.vip: loading firmware vpdma-1b8.bin
[ 14.501311] vip 48970000.vip: VPDMA firmware loaded
[ OK ] Started Avahi mDNS/DNS-SD Stack.
Starting Save/Restore Sound Card State...
[ OK ] Started TI IPC Daemon.
[ OK ] Started RPC Bind Service.
[ OK ] Started TI MultiCore Tools Daemon.
[ OK ] Found device /dev/ttyS2.
[ OK ] Started Network Service.
[ OK ] Started Login Service.
[ OK ] Reached target Network.
Starting Enable and configure wl18xx bluetooth stack...
Starting Simple Network Management Protocol (SNMP) Daemon....
[ 15.895324] EXT4-fs (mmcblk1p2): recovery complete
[ 15.900424] EXT4-fs (mmcblk1p2): mounted filesystem with ordered data mode. )
Starting Lightning Fast Webserver With Light System Requirements...
Starting Permit User Sessions...
[ 16.090695] SCSI subsystem initialized
[ 16.118693] CAN device driver interface
[ 16.129388] omap-sham 4b101000.sham: hw accel on OMAP rev 4.3
[ 16.243107] omap_wdt: OMAP Watchdog Timer Rev 0x01: initial timeout 60 sec
[ 16.311867] c_can_platform 4ae3c000.can: c_can_platform device registered (r)
[ 16.336966] omap-aes 4b500000.aes: OMAP AES hw accel rev: 3.3
[ 16.345809] omap-aes 4b500000.aes: will run requests pump with realtime prioy
[ 16.383244] omap-aes 4b700000.aes: OMAP AES hw accel rev: 3.3
[ 16.387596] omap-aes 4b700000.aes: will run requests pump with realtime prioy
[ 16.481418] FAT-fs (mmcblk1p1): Volume was not properly unmounted. Some data.
[ 16.502672] remoteproc remoteproc2: powering up 40800000.dsp
[ 16.502683] remoteproc remoteproc2: Booting fw image dra7-dsp1-fw.xe66, size4
[ 16.509361] omap_hwmod: mmu0_dsp1: _wait_target_disable failed
[ 16.509395] omap-iommu 40d01000.mmu: 40d01000.mmu: version 3.0
[ 16.509432] omap-iommu 40d02000.mmu: 40d02000.mmu: version 3.0
[ 16.702266] virtio_rpmsg_bus virtio2: rpmsg host is online
[ 16.702390] remoteproc remoteproc2: registered virtio2 (type 7)
[ 16.702444] remoteproc remoteproc2: remote processor 40800000.dsp is now up
[ 16.738632] virtio_rpmsg_bus virtio2: creating channel rpmsg-proto addr 0x3d
[ 16.899825] [drm] Initialized pvr 1.14.3699939 20110701 for 56000000.gpu on 1
[ 17.566308] omap-hdmi-audio omap-hdmi-audio.0.auto: snd-soc-dummy-dai <-> 58k
[ 17.566315] omap-hdmi-audio omap-hdmi-audio.0.auto: ASoC: no DMI vendor name!
[ 17.897275] pruss 4b200000.pruss: creating PRU cores and other child platfors
[ 17.916113] snd_soc_simple_card_utils: exports duplicate symbol asoc_simple_)
[ 17.951221] davinci_mdio 4b232400.mdio: davinci mdio revision 1.6, bus freq 0
[ 17.951227] libphy: 4b232400.mdio: probed
[ 17.973969] snd_soc_simple_card_utils: exports duplicate symbol asoc_simple_)
[ 18.051327] davinci_mdio 4b232400.mdio: timed out waiting for user access
[ 18.151518] davinci_mdio 4b232400.mdio: timed out waiting for idle
[ 18.151581] davinci_mdio: probe of 4b232400.mdio failed with error -5
[ 18.151954] pruss 4b280000.pruss: creating PRU cores and other child platfors
[ 18.211213] davinci_mdio 4b2b2400.mdio: davinci mdio revision 1.6, bus freq 0
[ 18.211219] libphy: 4b2b2400.mdio: probed
[ 18.311309] davinci_mdio 4b2b2400.mdio: timed out waiting for user access
[ 18.413182] davinci_mdio 4b2b2400.mdio: timed out waiting for idle
[ 18.413251] davinci_mdio: probe of 4b2b2400.mdio failed with error -5
[ 18.430180] remoteproc remoteproc3: 4b234000.pru is available
[ 18.430223] pru-rproc 4b234000.pru: PRU rproc node /ocp/pruss_soc_bus@4b2260y
[ 18.430443] remoteproc remoteproc4: 4b238000.pru is available
[ 18.430478] pru-rproc 4b238000.pru: PRU rproc node /ocp/pruss_soc_bus@4b2260y
[ 18.430688] remoteproc remoteproc5: 4b2b4000.pru is available
[ 18.430723] pru-rproc 4b2b4000.pru: PRU rproc node /ocp/pruss_soc_bus@4b2a60y
[ 18.430901] remoteproc remoteproc6: 4b2b8000.pru is available
[ 18.430929] pru-rproc 4b2b8000.pru: PRU rproc node /ocp/pruss_soc_bus@4b2a60y
[ OK ] Started Redis In-Memory Data Store.
Starting Network Name Resolution...
Starting Wait for Network to be Configured...
[ 19.719366] ahci 4a140000.sata: SSS flag set, parallel bus scan disabled
[ 19.785277] ahci 4a140000.sata: AHCI 0001.0300 32 slots 1 ports 3 Gbps 0x1 ie
[ OK ] Started Simple Network Management Protocol (S[ 19.858989] ahci 4a140
NMP) Daemon..
[ OK ] Started uim-sysfs.service.
[ OK ] Started Save/Restore Sound Card State.
[ OK ] Started Enable and configure wl18xx bluetooth stack.
[ OK ] Started Lightning Fast Webserver With Light System Requirements.
[ 19.966926] scsi host0: ahci
[ 19.970018] ata1: SATA max UDMA/133 mmio [mem 0x4a140000-0x4a1410ff] port 0x0
[ OK ] Started Permit User Sessions.
[ OK ] Started Network Name Resolution.
[ 20.383414] ata1: SATA link down (SStatus 0 SControl 300)
[ 20.449368] rpmsg_rpc virtio0.rpmsg-rpc.-1.101: probing service dce-callback1
[ 20.534965] rpmsg_rpc virtio0.rpmsg-rpc.-1.101: published functions = 4
[ 20.542254] rpmsg_rpc virtio0.rpmsg-rpc.-1.102: probing service rpmsg-dce wi2
[ 20.674722] rpmsg_rpc virtio0.rpmsg-rpc.-1.102: published functions = 9
[ 20.809468] NET: Registered protocol family 44
[ OK ] Started Wait for Network to be Configured.
[ 21.056093] xhci-hcd xhci-hcd.1.auto: xHCI Host Controller
[ 21.063121] xhci-hcd xhci-hcd.1.auto: new USB bus registered, assigned bus n1
[ 21.081771] xhci-hcd xhci-hcd.1.auto: hcc params 0x0220f04c hci version 0x100
[ 21.091224] xhci-hcd xhci-hcd.1.auto: irq 179, io mem 0x48890000
[ 21.101342] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002
[ 21.108603] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber1
[ 21.117870] usb usb1: Product: xHCI Host Controller
[ 21.124701] usb usb1: Manufacturer: Linux 4.14.79-ge669d52447 xhci-hcd
[ 21.133298] usb usb1: SerialNumber: xhci-hcd.1.auto
[ 21.142800] hub 1-0:1.0: USB hub found
[ 21.146968] hub 1-0:1.0: 1 port detected
[ 21.161066] xhci-hcd xhci-hcd.1.auto: xHCI Host Controller
[ 21.167828] xhci-hcd xhci-hcd.1.auto: new USB bus registered, assigned bus n2
[ 21.179960] xhci-hcd xhci-hcd.1.auto: Host supports USB 3.0 SuperSpeed
[ 21.189055] usb usb2: We don't know the algorithms for LPM for this host, di.
[ 21.199015] usb usb2: New USB device found, idVendor=1d6b, idProduct=0003
[ 21.207180] usb usb2: New USB device strings: Mfr=3, Product=2, SerialNumber1
[ 21.217158] usb usb2: Product: xHCI Host Controller
[ 21.225096] usb usb2: Manufacturer: Linux 4.14.79-ge669d52447 xhci-hcd
[ 21.233052] usb usb2: SerialNumber: xhci-hcd.1.auto
[ 21.244033] hub 2-0:1.0: USB hub found
[ 21.248506] hub 2-0:1.0: 1 port detected
[ OK ] Reached target Sound Card.
[ OK ] Listening on Load/Save RF Kill Switch Status /dev/rfkill Watch.
[ OK ] Reached target Network is Online.
[ OK ] Started strongSwan IPsec IKEv1/IKEv2 daemon using ipsec.conf.
[ OK ] Reached target Host and Network Name Lookups.
[ OK ] Started NFS status monitor for NFSv2/3 locking..
[ OK ] Started Getty on tty1.
[ OK ] Started Serial Getty on ttyS2.
[ OK ] Reached target Login Prompts.
Starting Synchronize System and HW clocks...
Starting rc.pvr.service...
[ OK ] Started Synchronize System and HW clocks.
[ 24.960256] PVR_K: UM DDK-(3699939) and KM DDK-(3699939) match. [ OK ]
[ OK ] Started rc.pvr.service.
Starting weston.service...
[ 25.235757] NET: Registered protocol family 15
[ 25.510619] Initializing XFRM netlink socket
[ 27.369471] omap_hwmod: mmu0_dsp1: _wait_target_disable failed
[ OK ] Started weston.service.
Starting telnetd.service...
Starting Matrix GUI...
[ OK ] Started telnetd.service.
Starting thttpd.service...
[ OK ] Started Matrix GUI.
[ OK ] Started thttpd.service.
Starting rng-tools.service...
[ OK ] Started rng-tools.service.
Starting LSB: Redis, a key-value store...
[ OK ] Started LSB: Redis, a key-value store.
Starting gdbserverproxy.service...
_____ _____ _ _
| _ |___ ___ ___ ___ | _ |___ ___ |_|___ ___| |_
| | _| .'| . | . | | __| _| . | | | -_| _| _|
|__|__|_| |__,|_ |___| |__| |_| |___|_| |___|___|_|
|___| |___|
Arago Project http://arago-project.org am57xx-evm ttyS2
Arago 2018.10 am57xx-evm ttyS2
am57xx-evm login: root
root@am57xx-evm:~# *************************************************************
***************************************************************
NOTICE: This file system contains the following GPLv3 packages:
autoconf
bash-dev
bash
binutils-dev
binutils
bison-dev
bison
cifs-utils
cpio
cpp-symlinks
cpp
dosfstools
elfutils-dev
elfutils
findutils
g++-symlinks
g++
gawk
gcc-symlinks
gcc
gdb
gdbc6x
gdbserver
gettext
glmark2
gstreamer1.0-libav
gzip
hidapi
libasm1
libcairo-perf-utils
libdw1
libelf1
libgdbm-compat4
libgdbm-dev
libgdbm4
libgettextlib
libgettextsrc
libgmp10
libidn11
libmavconn
libmpc3
libmpfr4
libreadline-dev
libreadline7
libunistring2
m4-dev
m4
make
mavlink
mavros-extras
mavros-msgs
mavros
nettle
parted
python3-pycairo
socketcan-interface
swig-dev
swig
which
If you do not wish to distribute GPLv3 components please remove
the above packages prior to distribution. This can be done using
the opkg remove command. i.e.:
opkg remove <package>
Where <package> is the name printed in the list above
NOTE: If the package is a dependency of another package you
will be notified of the dependent packages. You should
use the --force-removal-of-dependent-packages option to
also remove the dependent packages as well
***************************************************************
***************************************************************
