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J6PEVM577P: Timing in case of abrupt power-down

Francois Charlot
Mastermind 28237 points
Part Number: J6PEVM577P
Other Parts Discussed in Thread: DRA76P, TPS65917-Q1, DRA75, , LP87565-Q1, TPS43351-Q1

Hello,

My customer is designing a DRA76P board and wants to meet the abrupt power down sequencing requirements, especially that of the datasheet, figure 5-10, note 4 that says "porz must be asserted low for 100 μs min to ensure SoC is set to a safe functional state before any voltage begins to ramp down".

Having looked at the schematic of our EVM, I think that this could be driven from the undervoltage detection circuit on page 35 that drives the POWERHOLD signal that goes to the GPIO_5 of the O917A154TRGZRQ1 (TPS65917-Q1) PMIC. But I do not have the details of how this PMIC is programmed, so cannot be sure.

Could you please detail how to implement the above note 4? Thank you.


Best regards,
François.

  • 0
    TI__Mastermind 18400 points

    Hi François,

    If using the regular POR output of a PMIC (i.e. RESET_OUT), this will ensure POR release meets DRA75 timing requirements, provided the PMIC is compliant to DRA75.

    Regards,
    Stan

  • 0 in reply to Stanislav Stilyanov
    TI__Mastermind 28237 points

    Hi Stanlislas,

    Thank you. I could not find any timing data in the TPS65917-Q1 datasheet about RESET_OUT in case of abrupt power-down. Could you provide me with some evidence please? Thank you.


    Best regards,
    François.

  • 0 in reply to Francois Charlot
    TI__Mastermind 18400 points

    François,

    I'm sorry, looks like I didn't read carefully.

    To my knowledge, TPS65917-Q1 will not shut down in a controlled manner in case of abrupt power-down. Additional circuitry could be used to detect power-down on the 12-V supply (if in a vehicle) and assert a signal to PMIC to power down. This implies a sufficient bulk capacitance is present on the VSYS (PMIC) power supply to allow the sequence to complete.

    Regards,

    Stan

  • 0 in reply to Stanislav Stilyanov
    TI__Mastermind 28237 points

    Hi Stan,

    Thank you. This leads back to my initial question. Whichssections of the schematic of our EVM implement the 100 us safe delay of the note 4?

    Best regards,

    François.

  • 0 in reply to Francois Charlot
    TI__Mastermind 18400 points

    1. Normal power down by software or by user push-button:

    The PMIC, provided it is approved by TI for the SoC in question, will perform the required power-down sequence including RESET_OUT ----> PORz assertion.

    2. Abrupt power down

    This needs to be detected by external circuitry which will instruct the PMIC to start a ramp-down as if it was a normal, requested, power-down.

    Regards,

    Stan

  • 0 in reply to Francois Charlot
    TI__Mastermind 18400 points

    "Thank you. I could not find any timing data in the TPS65917-Q1 datasheet about RESET_OUT in case of abrupt power-down. Could you provide me with some evidence please? Thank you."

    > The PMIC has a general datasheet not describing the different EEPROM settings. As a general rule, if a PMIC is told as compatible to a SoC, then this applies to RESET_OUT timing too. I.e. RESET_OUT timing is compliant to the ramp-up and ramp-down diagrams in the respective SoC datasheet.

    Regards,

    Stan

  • 0 in reply to Stanislav Stilyanov
    TI__Mastermind 28237 points

    Hi Stan,

    Could you please reach out to the designer of the J6PEVM577P board and ask which circuitry ensures the detection of an abrupt power-down, or if the EVM does not support this function, if we have an example design for that? Thank you.


    Best regards,
    François.

  • 0 in reply to Stanislav Stilyanov
    TI__Mastermind 28237 points

    Hi Stan,

    I cannot tell to my customer "the TPS65917-Q1 RESET_OUT just works in case of abrupt power-down, just trust me". Do we have evidence to back up this statement that accounts for the specific OTP programming of TPS65917-Q1 for the J6+ processor?


    Thanks,
    François.

  • 0 in reply to Francois Charlot
    TI__Mastermind 18400 points

    François,

    Can you please tell me more about the project?

    Is it automotive?

    How many abrupt power losses are estimated to happen? For ex. per month.

    What needs to happen upon abrupt power loss? Will software be involved to perform any actions before SoC power fully collapses?

    How the conventional shut down will be initiated? By SW? By a push-button? By external HW signal?

    Thanks,

    Stan

  • 0 in reply to Stanislav Stilyanov
    TI__Mastermind 28237 points

    Hi Stan,

    Yes that's automotive. There is no intended abrupt power loss in this system, but an abrupt power loss *may* happen for a random reason outside of the J6+ system.

    Since the datasheet says that a certain condition must be met to "ensure SoC is set to a safe functional state before any voltage begins to ramp down", my customers asks how to fulfill this condition which is to asset porz low for 100 μs min before the power goes away.

    Back to my former question: does the J6PEVM577P board includes any circuit to detect an abrupt power-down? If yes, could you please delineate it so my customer can replicate just that? If not, do we have an example schematic to detect an abrupt power-down? Thank you.


    Best regards,
    François.

  • 0 in reply to Francois Charlot
    TI__Mastermind 18400 points

    Since the datasheet says that a certain condition must be met to "ensure SoC is set to a safe functional state before any voltage begins to ramp down",

    > Yes , this a requirement for a safe SoC ramp-down sequence, but note, when the PMIC controls the power-down sequence. When in abrupt power loss, actually other things may damage the SoC, that is, the uncontrolled ramp-down of all that SoC power supplies. The reason is, there are many voltage and power domains in the SoC, isolated one of another. This isolation works properly only when one domain is powered earlier than its neighbor and the other way around during power down. POR assertion will be of little help in such case.

    Back to my former question: does the J6PEVM577P board includes any circuit to detect an abrupt power-down? If yes, could you please delineate it so my customer can replicate just that? If not, do we have an example schematic to detect an abrupt power-down? Thank you.

    > No circuit in EVM. If power loss can occur extremely rare, they can leave it as is. If it is , however, a car safety requirement, then this would be a new topic to discuss

    Regards,

    Stan.

  • 0 in reply to Stanislav Stilyanov
    TI__Mastermind 28237 points

    Hi Stan,

    Thank you. I am sorry to be a pain, but the note 4 I was referring to is related to Fig. 5-10 "Abrupt Power-Down Sequencing". So we are not in the case of the PMIC controlling the power-down. I understand your statement about the voltage and power domains, and I am fine with it, so we do not have to follow the power-down sequence. But why do we have the 100 us porz requirement?


    Thanks,
    François.

  • 0 in reply to Francois Charlot
    TI__Mastermind 18400 points

    François,

    My bad! I didn't knew we have added an Abrupt Power Down figure at some moment and just because note 4 exists for Recommended Power down figure, I thought we are talking about the Recommended one all the time.

    I'm contacting the datasheet team to comment.

    Stan

  • 0 in reply to Stanislav Stilyanov
    TI__Genius 10000 points

    Francois,

    From the PMIC side in the TPS65917-Q1 datasheet, we have a section about meeting the power down sequence (Section 6.2.2.6). This section provides some options to help ensure a proper power down sequence with loss of power condition. However, if those options can't be implemented, the rails will all shut off at the same time once VCCA hits VSYS_LO threshold.

    Thanks,

    Nastasha

  • 0 in reply to Nastasha
    TI__Mastermind 28237 points

    Hi Natasha and Cyril,

    Thank you. I still found no explanation about why porz needs to be held low for 100 us in case of abrupt power-down.

    And again: does the J6PEVM577P board includes any circuit to detect an abrupt power-down? If yes, could you please delineate it so my customer can replicate just that? If not, do we have an example schematic to detect an abrupt power-down?

    Thank you.

    Best regards,
    François.

  • 0 in reply to Francois Charlot
    TI__Expert 6975 points

    Hey Francois,

    My name is Bill McCracken & I designed the J6Plus EVM PDN & captured PMIC OTP settings to implement recommended power up & down sequences.

    Yes, the J6Plus EVM PDN/SCH implements "early detection" of VBATT power lost by leveraging the capabilities of the 1st Stage Buck Controller (TPS43351-Q1). As the SCH & PDN snap-shots below show, the VLIM_12V0 (VBATT input after reverse voltage & current limiting input conditioning) is divided down by a R-divider network (R39 & R21). This allows the EN_TPS43351 net connected to ENA & ENB input pins to disable 1st Stage Controller as the VLIM_12V0 crosses below 4.02V threshold. The R-Div provides a dividing factor of 0.4232 to convert 4.02V to 1.7V = min VIH for ENA & ENB inputs. As a result, the power good signals (PGA & PGB) assert low immediately while the controller continues operating & supplying VSYS_3V3 input voltage to 2nd stage SoC PDN (TPS65917-Q1 & LP87565-Q1). This provides ~1ms of "early warning" to 2nd Stage PDN so that a standard power down sequence as defined by the TPS65917-Q1's OTP settings can begin a normal power down sequence upon detection of input power loss. The min input voltage to 917 PMIC is 2.75V for internal digital state machine logic.  After crossing below 2.75V, the PMIC's internal state machine stops operating, digital control of the analog power resources stops and all voltage outputs are disabled & begin to discharge. We have measured & validated on the bench the PMIC OTP settings provide 179us of elapsed time from PORz assertion until the VDDSHV_3V3 supply rail (rail with fastest discharge across the group of mainly 3.3V supplies are disabled first in pwr down seq) ramps down below the min SoC domain input voltage. In fact, the total elaped time from PORz asserting low until the VSYS_3V3 supply crosses 2.75V is ~2.44ms which is sufficient time to complete recommended power down seq under full control of PMIC's digital state machine.

    Hope these design & validation testing details meet your needs...:)

    J6Plus EVM SCH snap-shot, pg 32 - zone 2D:

    J6Plus EVM PDN snap-shot:

    Power Down Scope Capture from OTP validation testing:

    Regards,

    Bill McCracken

  • 0 in reply to Bill McCracken
    TI__Mastermind 28237 points

    Hi Bill,

    Fantastic answer, appreciate its thoroughness. Thank you very much.


    Best regards,
    François.