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66AK2H06: USB3.0 programming model

Koichiro Tashiro
Mastermind 22935 points
Part Number: 66AK2H06

Hi,

I have a few questions from customer about USB3.0 programming model.
Customer wants to use USB3.0 with device(peripheral) mode.
Customer refers to "Keystone II Architecture Universal Serial Bus 3.0 User’s guide" (spruhj7a.pdf).

Q1)
Where can I find address mapping of USB_DEPCMD, USB_DEPCMDPAR[0:2]?
There is no address information in UG.

Q2)
In section 2.6.2 Device Programming Model, there are some steps to access USB_DEPCMDn in initialization.
These accesses are done by firmware on device (Keystone2) side?
Or Host side driver accesses them?

Thanks and regards,
Koichiro Tashiro

  • 0
    TI__Guru* 95265 points

    Hi,

    We don't have any USB driver for K2H device. I can only refer to K2G USB driver software for your questions as they are both DWC USB.  

    From the USB driver code of K2G (hw_dwc_usb.h) and KeyStone II Architecture Universal Serial Bus 3.0 (USB 3.0) User Guide http://www.ti.com/lit/ug/spruhj7a/spruhj7a.pdf

    #define DWC_USB_GHWPARAMS8 (0xC600u) ==========>Global Registers
    #define DWC_USB_GHWPARAMS9 (0xC604u)
    #define DWC_USB_GTXFIFOPRIDEV (0xC610u)
    #define DWC_USB_GTXFIFOPRIHST (0xC618u)
    #define DWC_USB_GRXFIFOPRIHST (0xC61Cu)
    #define DWC_USB_GFIFOPRIDBC (0xC620u)
    #define DWC_USB_GDMAHLRATIO (0xC624u)
    #define DWC_USB_DCFG (0xC700u)    ============> Device Registers
    #define DWC_USB_DCTL (0xC704u)
    #define DWC_USB_DEVTEN (0xC708u)
    #define DWC_USB_DSTS (0xC70Cu)
    #define DWC_USB_DGCMDPAR (0xC710u)
    #define DWC_USB_DGCMD (0xC714u)
    #define DWC_USB_DALEPENA (0xC720u)
    #define DWC_USB_OEVT (0xCC08u)
    #define DWC_USB_OEVTEN (0xCC0Cu)
    #define DWC_USB_OSTS (0xCC10u)
    #define DWC_USB_OCFG (0xCC00u)===========> USB2.0 OTG and Battery Charger Registers
    #define DWC_USB_OCTL (0xCC04u)
    #define DWC_USB_ADPCFG(n) (0xcc20U + ((n-1) * 0x14U))
    #define DWC_USB_ADPCTL(n) (0xcc24U + ((n-1) * 0x14U))
    #define DWC_USB_ADPEVT(n) (0xcc28U + ((n-1) * 0x14U))
    #define DWC_USB_ADPEVTEN(n) (0xcc2cU + ((n-1) * 0x14U))
    #define DWC_USB_BCFG(n) (0xcc30U + ((n-1) * 0x10U))
    #define DWC_USB_BCEVT(n) (0xcc38U + ((n-1) * 0x10U))
    #define DWC_USB_BCEVTEN(n) (0xcc3cU + ((n-1) * 0x10U))
    #define DWC_USB_DEPCMDPAR2_0(n) (0xc800U + ((n-1) * 0x10U))
    #define DWC_USB_DEPCMDPAR1_0(n) (0xc804U + ((n-1) * 0x10U))
    #define DWC_USB_DEPCMDPAR0_0(n) (0xc808U + ((n-1) * 0x10U))
    #define DWC_USB_DEPCMD_0(n) (0xc80cU + ((n-1) * 0x10U))

    The registers you questioned in Q1 are not listed in UG. The offset listed in source code seems to be valid, given other offsets matched UG.

    For Q2, let me try the K2G example and get back to you. 

    Regards, Eric

  • 0 in reply to lding
    TI__Guru* 95265 points

    For Q2,  USB_DEPCMDn programming is needed in the device mode, not the host mode.

    Regards, Eric