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DRA76P: mcASP and AES3 questions

Part Number: DRA76P

Dear E2E team,

I'm designing a digital audio transmission system based on:

  • Transmitter: DRA76P
  • Protocol: AES3id

After studying the DRA76P mcASP Technical Reference Manual I found a couple of questions I hope you can help me with:

  1. According to a Technical Reference Manual NOTE in 26.6.2.2.1 (page 7500), McASP outputs are 1V2/1V8. According to its datasheet (IE: page 24), McASP are 1V8/3V3.
    • May you please confirm which voltage value are the correct ones?
  2. DRA76P mcASP are compatible with S/PDIF and AES3 protocols, but only S/PDIF-related information is provided in the Technical Reference Manual (IE: there is a "26.6.2.2.5 S/PDIF Coding Format" but there is no "AES3 Coding Format", or there is in 26.6.5.1.2.1 an explanation of how initialize the McASP to operate with S/PDIF protocol but no for AES3)
    • May you please confirm AES3 is supported by J6? If yes, Does TI provide an application note or something like that to explains how to implement it?
    • As mcASP outputs are single-ended, Does it mean the truly supported AES3 protocol is the AES3id one?
  3. Are the mcASP outputs (after a voltage level adaptation) able to directly manage the long distances the AES3 protocol support
    • If no, Does TI provide any solution?

I look forward your answers.

Thank you very much in advance,

Guillermo.

  • Hi Guillermo,

    My understanding is that S/PDIF and AES3 differ in the channel status word which is configurable in McASP via MCASP_DITCSRAi and MCASP_DITCSRBi registers. I'll check who can help with electrical questions.

  • Hi Misael,

    Thank you for your reply!

    It confirms what I was thinking: "As S/PDIF and AES3 differ only in a few aspects (when talking about codification), by providing an explanation of S/PDIF, AES3 explanation is also (implicitly) provided".

    I was just expecting the Technical Reference Manual to be a little more clear about it.

  • Hi Guillermo,

    DRA7xx IO voltages can be 1.8V or 3.3V , selected during board design.

    MCASP interface is typically connected to external audio codec IC.

    Regards,

    Stan

  • Hi Stan,

    Thank you for your reply.

    Unfortunately, I did not understand your answer. Why should I connect the McASP out to an audio codec for a digital transmission lines?

    Maybe I did not explain my design properly. The idea is:

    1. J6+ with a McASP I/O configured to transmit in DIT mode an AES3id signal
    2. Route directly the McASP I/O to their connector trough some passive components to adapt the voltage levels and impedance
    3. Transmit the digital signal to a DIR placed in an external device

    So my question is: Do I need a transceiver to send the digital AES3 signal over the long distances the protocol supports? or as McASP integrates a DIT, it should be able to directly send the information without any transceiver needed.

    Regards,

  • Guillermo,

    For I/O, MCASP supports LVCMOS buffers at 1.8v/3.3V for its serial DATAn, CLOCK, FRAME_SYNC signals, where n is dependent on MCASP instance.

    This is sufficient for on-board or inter-board connection (~ few 10s cm) to an external audio IC like:

    ADC, DAC, codec, DIR, or S/PDIF transmit PHY.

    regards,

    Stan

  • Hi Stan,

    I'm sorry, but I'm still no understanding why the J6+ is only able to drive such low distances if it integrates a DIT, because as far as I know (by taking a look to your standalone DIT chips and their EVM), they are sufficient for long-distance inter-board connections.

    In any case, May you please recommend me an AES3 transmit PHY from TI?

    Thank you very much for your time and valuable help.

    Regards!

  • Guillermo,

    I'm sorry, PHY is dependent on your exact needs. It is outside the scope of the processor's forum.

    Regards,

    Stan