CCS/66AK2H12: EDMA CSL IPR Setting Problem

Tool/software: Code Composer Studio

Hello all,

I created a sample EDMA project using CSL. I want to interrupt CPU after transfer completion. When I debug the program, EDMA does the transfer correctly, sets the ier bit correctly but is is not setting ipr bit when the transfer is done.

What could be the problem, thanks?

/*
 *  ======== main.c ========
 */

#include <xdc/std.h>

#include <xdc/runtime/Error.h>
#include <xdc/runtime/System.h>

#include <ti/sysbios/BIOS.h>
#include <ti/sysbios/knl/Semaphore.h>
#include <ti/sysbios/knl/Task.h>
#include <ti/sysbios/hal/Hwi.h>


#include <ti/csl/csl.h>
#include <ti/csl/csl_edma3Aux.h>
#include <ti/csl/csl_edma3.h>

#include <ti/csl/csl_cache.h>
#include <ti/csl/csl_cacheAux.h>

#include<ti/csl/csl_cpIntc.h>
#include<ti/csl/csl_cpIntcAux.h>

#include <ti/sysbios/family/c66/tci66xx/CpIntc.h>
#include <ti/sysbios/family/c64p/EventCombiner.h>

#include <c6x.h>

#define CSL_EDMA3 0
#define CSL_EDMA3_CHA_4 4
#define CIC0 0
#define SYS_EVENT_ID 36
#define HOST_INT_ID 35

#define SRC_ADDR (uint8_t volatile *) 0x80000000
#define DST_ADDR (uint8_t volatile *) 0x90000000


void cacheinit(void) {
    int i;
    for(i=128;i<256;i++)
    {
        CACHE_disableCaching(i);
    }

    CACHE_setL2Size(CACHE_0KCACHE);
    CACHE_setL1DSize((CACHE_L1Size)CACHE_L1_32KCACHE);
    CACHE_setL1PSize((CACHE_L1Size)CACHE_L1_32KCACHE);
}

void memoryinit(void) {
    Char i;
    for(i=0;i<100;i++)
    {
        *(SRC_ADDR + i) =1;
    }


}

void edma_isr() //lisrEdma3ComplHandler0
{
    //Log_printf0("WE GOT TO THE ISR \n");
    x=5;
}

void int_init(void)
{

    int  eventId;
    Hwi_Params hwiParams;
    Error_Block eb;

    CpIntc_Module_startup(0);
    // Map system event to host interrupt
    CpIntc_mapSysIntToHostInt(CIC0, SYS_EVENT_ID, HOST_INT_ID);

    // Convert host interrupt to event id for CorePac
    eventId = CpIntc_getEventId(HOST_INT_ID);

    // Initialize the Hwi parameters. EventCombiner assumes eventId is 0, 1, 2 and 3.
    Hwi_Params_init(&hwiParams);
    hwiParams.eventId = eventId;
    hwiParams.arg = hwiParams.eventId;
    hwiParams.enableInt = TRUE;

    // Register EventCombiner dispacher to INT7
    Hwi_create(7,(Hwi_FuncPtr) &edma_isr, &hwiParams, &eb); //&lisrEdma3ComplHandler0

    // Enable host interrupt.
    CpIntc_enableHostInt(CIC0, HOST_INT_ID);

    // Now setup completed. Enable system event.
    CpIntc_enableSysInt(CIC0, SYS_EVENT_ID);


}
/*
 *  ======== main ========
 */
int main()
{ 
    CSL_Edma3Context context;
    CSL_Status status;
    CSL_Edma3Handle hModule;
    CSL_Edma3Obj edmaObj;

    CSL_Edma3ChannelObj chObj;
    CSL_Edma3ChannelAttr chAttr;
    CSL_Edma3ChannelHandle hChannel;

    CSL_Edma3ParamHandle hParam;

    CSL_Edma3HwSetup                hwSetup;
    CSL_Edma3HwDmaChannelSetup      dmahwSetup;

    CSL_Edma3CmdIntr edmaIntr;
    CSL_Edma3CmdIntr regionIntr;
    CSL_Edma3CmdDrae regionAccess;

    cacheinit();
    memoryinit();
    //int_init();
    status= CSL_edma3Init(&context);
    hModule = CSL_edma3Open(&edmaObj, CSL_EDMA3, NULL, &status);


//    regionAccess.region = CSL_EDMA3_REGION_1;
//    regionAccess.drae = (0x1 << CSL_EDMA3_CHA_4);
//    regionAccess.draeh = 0x0;
//    CSL_edma3HwControl(hModule, CSL_EDMA3_CMD_DMAREGION_ENABLE, &regionAccess);

    //    dmahwSetup.paramNum = 0;
    //    dmahwSetup.que      = CSL_EDMA3_QUE_0;
    //    hwSetup.dmaChaSetup = &dmahwSetup;
    //    hwSetup.qdmaChaSetup = NULL;
    //    status = CSL_edma3HwSetup(hModule,&hwSetup);

    edmaIntr.region = CSL_EDMA3_REGION_GLOBAL;
    edmaIntr.intrh = 0; //1<<(CSL_EDMA3_CHA_4-32)
    edmaIntr.intr = 1<<(CSL_EDMA3_CHA_4);
    status= CSL_edma3HwControl(hModule,CSL_EDMA3_CMD_INTR_ENABLE,&edmaIntr);

    chAttr.regionNum = CSL_EDMA3_REGION_GLOBAL;
    chAttr.chaNum = CSL_EDMA3_CHA_4;
    hChannel = CSL_edma3ChannelOpen(&chObj,CSL_EDMA3,&chAttr,&status);

    CSL_Edma3ParamSetup myParamSetup =
    {
     CSL_EDMA3_OPT_MAKE(CSL_EDMA3_ITCCH_DIS,
                        CSL_EDMA3_TCCH_DIS,
                        CSL_EDMA3_ITCINT_DIS,
                        CSL_EDMA3_TCINT_DIS,
                        CSL_EDMA3_CHA_4,
                        CSL_EDMA3_TCC_NORMAL,
                        CSL_EDMA3_FIFOWIDTH_NONE,
                        CSL_EDMA3_STATIC_DIS,
                        CSL_EDMA3_SYNC_AB,
                        CSL_EDMA3_ADDRMODE_INCR,
                        CSL_EDMA3_ADDRMODE_INCR
     ),
     (Uint32)0x80000000,
     CSL_EDMA3_CNT_MAKE(4,3),
     (Uint32)0x90000000,
     CSL_EDMA3_BIDX_MAKE(6,4),
     CSL_EDMA3_LINKBCNTRLD_MAKE(0xFFFF,3),
     CSL_EDMA3_CIDX_MAKE(0,0),
     1
    };



    int PsetNum = 1;
    CSL_edma3HwChannelSetupParam(hChannel,PsetNum);
    hParam = CSL_edma3GetParamHandle(hChannel,PsetNum,&status);
    status = CSL_edma3ParamSetup(hParam,&myParamSetup);


    CSL_edma3HwChannelSetupQue(hChannel,CSL_EDMA3_QUE_0);
    CSL_edma3HwChannelControl(hChannel,CSL_EDMA3_CMD_CHANNEL_ENABLE,NULL);
    CSL_edma3HwChannelControl(hChannel,CSL_EDMA3_CMD_CHANNEL_SET,NULL);

    while(1){};

}

Best Regards,

samseytani