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DM385: u-boot spi load

Part Number: DM385

What can be the reason of the following behavior:

While loading u-boot over spi, processor loads couple of 512-byte pages and stops loading?

My bin file looks OK at first sight: it has header with file length (0x0000C0F8), load address (0x40300000)

and byte order opposite to nand version:

00 00 C0 F8    40 30 00 00    EA 00 00 12    E5 9F F0 14    E5 9F F0 14

E5 9F F0 14    E5 9F F0 14    E5 9F F0 14 etc

  • Hi German,

    If you are using DM38x IPNC RDK, seems that SPI boot is not supported by default, we have SD and NAND boot:

    http://processors.wiki.ti.com/index.php/IPNC_RDK_DM38x_,_DM8127


    For SPI boot, you might need some u-boot source code modifications. You can refer to below guides for hints:

    http://processors.wiki.ti.com/index.php/TI81XX_PSP_UBOOT_User_Guide

    DM38x TRM, ch 4 ROM Code Memory and Peripheral Booting



    Note that this product does not have ongoing direct TI design support. For detailed support while working through your design, you may contact one of the following third parties: D3 Engineering, elnfochips, Ittiam Systems, Path Partner Technology, or Z3 Technologies.

    Regards,
    Pavel

  • Thanks a lot for quick response.

    Just one more clarification before closing the case:

    I think at the described moment processor is controlled not by u-boot yet,

    but by ROM bootloader code.

    Is it possible to look through ROM bootloader text, at least its SPI brunch?

    Regards

  • German,

    ROM Code is not accessible for modifications. If your boot flow stuck at ROM Code stage, then most probably you have HW malfunction.

    For more info regarding ROM Code, you can check TRM chapter 4 and below wiki page:

    http://processors.wiki.ti.com/index.php/AM335x_board_bringup_tips

    Regards,
    Pavel

  • Thanks, Pavel

    By no means I wanted to modify ROM boot code.

    It's just an issue of understanding of proper order of SPI load.

    It looks like I can't correctly follow procedure described in datasheet and tech reference.

    (so probably just an issue of my stupidity)

    Nevertheless, from all descriptions of memory booting (including SPI)

    I got an impression that Image for loading has to have just one header, containing size and address.

    Simple experiments with content of my SPI image show me that EVERY 512-byte page has to

    present some kind of header to make processor to read next 512-byte piece. (By changing first

    bytes of next 512-page I can force processor to read more pages)

    One can find a nice piece of information in Tech Ref, "SPI Read Sector Procedure"

    "From the next iteration onwards, a dummy value is transmitted on the master out line and the data is
    received on the master in line. This needs to be done because SPI protocol always operated in full duplex
    mode. The dummy data transmitted by the ROM is the Read Command appended to the start address"

    But this sentence is not enough for me to understand completely what should be transmitted every page.

    Has the start address be always the initial one or 512-byte shifted for every page? Or it doesn't matter,

    since it's "dummy" operation? And what about file size required for header - is it still in force?

    I, probably can spend some time experimenting and finally figure out, how to load device from SPI,

    But it would be very helpful if TI can submit me with more detailed info then one sentence in tech ref.

    One way of understanding it, was following ROM boot code, that's why I asked about it.

    And yes, I understand that DM38x is kind of abandoned child and don't have a lot of expectations.

    Best regards

  • Hello!

    Excuse me, I didn't understand completely:

    ROMboot is not available for modification, but is it available for viewing?

    I remember for DM365 it was quite possible to overview romboot code,

    Thanks

  • German Baranov said:
    ROMboot is not available for modification, but is it available for viewing?

    Yes, you can view it through JTAG. Tehre are also trace vectors which can be check at which stage ROM Code has pass successful and at which stage it fails.

    Regards,
    Pavel