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DRA829_TDA4VM: C7x memory map

Other Parts Discussed in Thread: TDA4VM

Hello TI Support,

I'm currently porting some code to run on the C7x DSPs on a TDA4VM board. In order to get first code pieces running I'm using linker command files I found on some of the C7x examples. In order to expand those files for my own code, I'll need a memory map for the C7x. The TRM for the board only provides a detailed memory map for the C66x. The main memory map states:

Region Name Start Address End Address Size
COMPUTE_CLUSTER0_DSP0   0x0064000000 0x0064FFFFFF 16 MB
COMPUTE_CLUSTER0_DSP1   0x0065000000 0x0065FFFFFF 16 MB

I have following questions.

  1. What are the regions of DSP0 and DSP1? There is one C7x and two C66x DSPs on the boards.
  2. Is there a detailed memory map for the C7x available, similar to the C66x memory map?
  3. Is the assumption from the example linker command files correct, that the L2SRAM for the C7x starts at 0x64800000 and has a maximal length of 0x080000?
  4. Is there a L2 SRAM/Cache configuration similar to the C66x possible?
  5. How can I access data outside the L2SRAM? Currently I run bare metal applications on the C7x. In the case I have data larger than the allowed heap/stack size, how can I access it from the global memory?

This information would help to write correct linker command files.

Thanks and kind regards,

Florian

  • Hi Florian,

    the DSP experts will reply to your questions soon. Meanwhile you can look at this userguide if you haven's already:

    Regards,

    Yordan

  • Hi Florian,

    I am not sure if you have access to the latest J721E SDK 6.1 which has all the details on the memory map of C7x, C66 DSP's including sample linker command files.

    You can request access to the SDK via TI MySecureSoftware. We highly recommend to start from here for any applications that you intend to develop.

    Regards,
    Shyam 

  • Hi Shyam,

    through a bit of searching I was able to find some helping documents. For everybody who's wondering the same refer to:

    • P-SDK Docs >> 7. Developer Notes >> 7.2. Understanding and updating SDK memory map for J721e
    • ti-processor-sdk-rtos-automotive-j7-evm-06_01_00_15/vision_apps/apps/basic_demos/app_tirtos/tirtos_linux/c7x_1/linker_mem_map.cmd
    • ti-processor-sdk-rtos-automotive-j7-evm-06_01_00_15/vision_apps/apps/basic_demos/app_tirtos/tirtos_linux/c7x_1/linker.cmd

    Kind regards,

    Florian

  • Actually, on question remains:

    Is there a L2 SRAM/Cache configuration similar to the C66x possible? See also this post.

    An answer to this would really be helpful since currently all the data I load from the main DDR is uncached and therefore very slow...

    Regards,

    Florian

  • Hi Florian,

    Yes C7x L2 SRAM supports cache/SRAM configurations similar to C66x. The C7x DSP also requires an MMU page-table setup similar to A72. This is different from MAR setup in C66x. Using CSL we can partition L2/L1 memories to cache/sram but it requires MMU setup to make it cacheable.

    You can take a look at ti-processor-sdk-rtos-automotive-j7-evm-06_01_00_15/vision_apps/apps/basic_demos/app_tirtos/tirtos_linux/c7x_1/c7x_1.cfg

    You will need to register a callback for setting up a page table as per your requirement. For example you can take a look at, appMmuInit() function in ti-processor-sdk-rtos-automotive-j7-evm-06_01_00_15/vision_apps/apps/basic_demos/app_tirtos/tirtos_linux/c7x_1/main.c file.

    To know about C7x architecture, programming and some optimized examples, I recommend going over the C7x Training material v0.5 which should be available along with  ti-processor-sdk-rtos-automotive-j7-evm-06_01_00_15 in MySecureSoftware.

    Regards,
    Shyam

  • Hi Shyam,

    I answered you in the other thread and like to continue the discussion there. You can close this one.

    Best,

    Florian