Hi,
In the TCI6482 processor datasheet the statements in page 23 (Note B and C about McBSP and VLYNQ pin default state) and in table 3-1 "AEA7" are conflicting.
I assume that whatever mentioned in Table 3-1 is correct regarding the default state of McBSP and VLYNQ interface.
That is by default AEA7 is low (internally pulled down) so McBSP0 and McBSP1 pin functionality is enabled and VLYNQ is disabled (as mentioned in table 3-1 pg 55).
If I am wrong please update me on this.
Regards
Sharath Chandra
