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TDA4 model inference problem

Hi,

I have recently tried to import a Jsegnet model downloaded from https://github.com/tidsp/caffe-jacinto-models/tree/caffe-0.17/trained/image_segmentation/cityscapes5_jsegnet21v2/sparse.

After import gave a message :

Name of the Network : jsegnet21v2_deploy
Num Inputs : 1
Num of Layer Detected : 25
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Num|TIDL Layer Name |Original Layer Name |Group |#Ins |#Outs |Inbuf Ids |Outbuf Id |In NCHW |Out NCHW |MACS |
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
0|TIDL_DataLayer |data | 0| -1| 1| x x x x x x x x | 0 | 0 0 0 0 | 1 3 512 1024 | 0 |
1|TIDL_BatchNormLayer |data/bias | 1| 1| 1| 0 x x x x x x x | 1 | 1 3 512 1024 | 1 3 512 1024 | 1572864 |
2|TIDL_ConvolutionLayer |conv1a | 1| 1| 1| 1 x x x x x x x | 2 | 1 3 512 1024 | 1 32 256 512 | 314572800 |
3|TIDL_ConvolutionLayer |pool1 | 1| 1| 1| 2 x x x x x x x | 3 | 1 32 256 512 | 1 32 128 256 | 301989888 |
4|TIDL_ConvolutionLayer |res2a_branch2a | 1| 1| 1| 3 x x x x x x x | 4 | 1 32 128 256 | 1 64 128 256 | 603979776 |
5|TIDL_ConvolutionLayer |pool2 | 1| 1| 1| 4 x x x x x x x | 5 | 1 64 128 256 | 1 64 64 128 | 301989888 |
6|TIDL_ConvolutionLayer |res3a_branch2a | 1| 1| 1| 5 x x x x x x x | 6 | 1 64 64 128 | 1 128 64 128 | 603979776 |
7|TIDL_ConvolutionLayer |res3a_branch2b | 1| 1| 1| 6 x x x x x x x | 7 | 1 128 64 128 | 1 128 64 128 | 301989888 |
8|TIDL_PoolingLayer |pool3 | 1| 1| 1| 7 x x x x x x x | 8 | 1 128 64 128 | 1 128 32 64 | 1048576 |
9|TIDL_ConvolutionLayer |res4a_branch2a | 1| 1| 1| 8 x x x x x x x | 9 | 1 128 32 64 | 1 256 32 64 | 603979776 |
10|TIDL_ConvolutionLayer |res4a_branch2b | 1| 1| 1| 9 x x x x x x x | 10 | 1 256 32 64 | 1 256 32 64 | 301989888 |
11|TIDL_ConvolutionLayer |res5a_branch2a | 1| 1| 1| 10 x x x x x x x | 11 | 1 256 32 64 | 1 512 32 64 |2415919104 |
12|TIDL_ConvolutionLayer |res5a_branch2b | 1| 1| 1| 11 x x x x x x x | 12 | 1 512 32 64 | 1 512 32 64 |1207959552 |
13|TIDL_ConvolutionLayer |out5a | 1| 1| 1| 12 x x x x x x x | 13 | 1 512 32 64 | 1 64 32 64 | 301989888 |
14|TIDL_Deconv2DLayer |out5a_up2 | 1| 1| 1| 13 x x x x x x x | 14 | 1 64 32 64 | 1 64 64 128 | 2097152 |
15|TIDL_ConvolutionLayer |out3a | 1| 1| 1| 7 x x x x x x x | 15 | 1 128 64 128 | 1 64 64 128 | 301989888 |
16|TIDL_EltWiseLayer |out3_out5_combined | 1| 2| 1| 14 15 x x x x x x | 16 | 1 64 64 128 | 1 64 64 128 | 524288 |
17|TIDL_ConvolutionLayer |ctx_conv1 | 1| 1| 1| 16 x x x x x x x | 17 | 1 64 64 128 | 1 64 64 128 | 301989888 |
18|TIDL_ConvolutionLayer |ctx_conv2 | 1| 1| 1| 17 x x x x x x x | 18 | 1 64 64 128 | 1 64 64 128 | 301989888 |
19|TIDL_ConvolutionLayer |ctx_conv3 | 1| 1| 1| 18 x x x x x x x | 19 | 1 64 64 128 | 1 64 64 128 | 301989888 |
20|TIDL_ConvolutionLayer |ctx_conv4 | 1| 1| 1| 19 x x x x x x x | 20 | 1 64 64 128 | 1 64 64 128 | 301989888 |
21|TIDL_ConvolutionLayer |ctx_final | 1| 1| 1| 20 x x x x x x x | 21 | 1 64 64 128 | 1 8 64 128 | 37748736 |
22|TIDL_Deconv2DLayer |out_deconv_final_up2 | 1| 1| 1| 21 x x x x x x x | 22 | 1 8 64 128 | 1 8 128 256 | 1048576 |
23|TIDL_Deconv2DLayer |out_deconv_final_up4 | 1| 1| 1| 22 x x x x x x x | 23 | 1 8 128 256 | 1 8 256 512 | 4194304 |
24|TIDL_Deconv2DLayer |out_deconv_final_up8 | 1| 1| 1| 23 x x x x x x x | 24 | 1 8 256 512 | 1 8 512 1024 | 16777216 |
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Total Giga Macs : 8.8353
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
INFO : Couldn't open perfSimConfig file: , Skipping Performance Simulation


~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~

Processing config file #0 : /home/tda4dev/psdk_rtos_auto_j7_06_00_00_00/tidl_j7_00_09_00_00/ti_dl/utils/tidlModelImport/tempDir/qunat_stats_config.txt
#..testvecs/input/0000000272.png
----------------------- TIDL Process with REF_ONLY FLOW ------------------------

# : 0 .. T 4632.07 !
Completed Processing /home/tda4dev/psdk_rtos_auto_j7_06_00_00_00/tidl_j7_00_09_00_00/ti_dl/utils/tidlModelImport/tempDir/qunat_stats_config.txt
End of config list found !

Then tidl_io.bin and tidl_net.bin were generated.

So I run ./PC_dsp_test_dl_algo.out in console.

Opening config list file : testvecs/config/config_list.txt

Processing config file #0 : testvecs/config/infer/internal/caffe/tidl_infer_jSegNet.txt

Always finished with the message below:

"Could not allocate memory for output .. Exiting"

Could you please help me to fix the problem?

Import.txt , infer.txt , input images and the list used are in the attached file.

Any sample import or infer files for Segnet are available?

Thank you,

Kevin.

1805.att.rar

  • Hi Kevin,

    My first suggestion will be to try this model with TIDL 1.0 release i.e. psdk_rtos_auto_j7_06_01_00.

    I have attached the files that I used for validating this model 

    modelType          = 0
    inputNetFile       = "../../test/testvecs/models/public/caffe/jsegNet21v2/deploy.prototxt"
    inputParamsFile    = "../../test/testvecs/models/public/caffe/jsegNet21v2/deploy.caffemodel"
    outputNetFile      = "../../test/testvecs/config/tidl_models/caffe/tidl_net_jSegNet21v2_1024x512.bin"
    outputParamsFile   = "../../test/testvecs/config/tidl_models/caffe/tidl_io_jSegNet21v2_1024x512_"
    inDataFormat = 0
    perfSimConfig = ../../test/testvecs/config/import/perfsim_base.cfg
    inData  =   "../../test/testvecs/config/segmentation_list.txt"
    postProcType = 3
    foldMaxPoolInConv2D = 0
    

    inFileFormat    = 2
    postProcType = 3
    padInBuffInTB = 1
    netBinFile      = "testvecs/config/tidl_models/caffe/tidl_net_jSegNet21v2_1024x512.bin"
    ioConfigFile    = "testvecs/config/tidl_models/caffe/tidl_io_jSegNet21v2_1024x512_1.bin"
    outData =   "testvecs/output/jsegNet21v2_1024x512.bin"
    inData  =   "testvecs/config/segmentation_list.txt"
    totNumClasses = 5
    debugTraceLevel = 0
    writeTraceLevel = 0
    
    
    
    
    
    

    Regards,

    Rishabh

  • I have changed the import and infer files.

    At the inference phase this message was given..

    "Could not allocate memory for output .. Exiting"

    How can I fix this or what setting may lead to this result?

    Thank you

  • Hi,

    As I mentioned previously you need to try with latest release.

    Regards,

    Rishabh

  • Hi,

    I haven't heard back from you, I'm assuming you were able to resolve your issue.
    If not, just post a reply below (or create a new thread if the thread has locked due to time-out).

    Regards,
    Rishabh