Part Number: TMS320C6654
Tool/software: Code Composer Studio
Hi,
I can't understand what is happening so I wrote such a title of thread what I assumed.
My DSP FW has mcbsp task that is referenced to TI example and it works fine at nomal operation.
If it causes context switch, and Mcbsp task yields other task however other active task occupies some time because other task priority is higher.
Then, returning to mcbsp task, output data sounds something strange.
It sounds like when data bit is shiftted from expected.
This phenomenon doesn't always happen but sometimes happen every time Mcbsp task is pending.
A similar phenomenon occurs when the emulation by the XDS200 debugger is stopped halfway.
Why does this happen ? How should I avoid it ?
My mcbsp frame configuration is the follow. I actually use mcbsp0 and mcbsp1 as same configuration.
DSP I/O always works as audio slave and sync to external frame clock.
Mcbsp_DataConfig mcbspChanConfigRx =
{
Mcbsp_Phase_SINGLE,
Mcbsp_WordLength_32,
Mcbsp_WordLength_32, /* Dont care for single phase*/
INPUT_NUM,
INPUT_NUM, // Only used with dual phase
Mcbsp_FrmSync_DETECT,
//Mcbsp_FrmSync_IGNORE,
//Mcbsp_DataDelay_0_BIT,
Mcbsp_DataDelay_1_BIT,
Mcbsp_Compand_OFF_MSB_FIRST,
Mcbsp_BitReversal_DISABLE,
//Mcbsp_IntMode_ON_SYNCERR,
Mcbsp_IntMode_ON_FSYNC,
Mcbsp_RxJust_RxJUST_LZF,
//Mcbsp_RxJust_RZF, /* Dont care for TX */
Mcbsp_DxEna_OFF
};
Mcbsp_DataConfig mcbspChanConfigTx =
{
Mcbsp_Phase_SINGLE,
Mcbsp_WordLength_32,
Mcbsp_WordLength_32, /* Dont care for single phase*/
OUTPUT_NUM,
OUTPUT_NUM, // Only used with dual phase
Mcbsp_FrmSync_DETECT,
//Mcbsp_FrmSync_IGNORE,
//Mcbsp_DataDelay_0_BIT,
Mcbsp_DataDelay_1_BIT,
Mcbsp_Compand_OFF_MSB_FIRST,
Mcbsp_BitReversal_DISABLE,
//Mcbsp_IntMode_ON_SYNCERR,
Mcbsp_IntMode_ON_FSYNC,
Mcbsp_RxJust_RxJUST_LZF, /* Dont care for TX */
Mcbsp_DxEna_OFF
};
Mcbsp_srgConfig mcbspSrgCfg =
{
TRUE, /* No gsync to be used as input is not CLKS */
//Mcbsp_ClkSPol_RISING_EDGE, /* Dont care as input clock is not clks */
Mcbsp_ClkSPol_FALLING_EDGE, /* Dont care as input clock is not clks */
//Mcbsp_SrgClk_CLKS, /* McBSP External clock to be used */
Mcbsp_SrgClk_CLKX,
//Mcbsp_SrgClk_CLKCPU, /* McBSP internal clock to be used */
//12288000, /* Mcbsp internal clock frequency 12.288MHz */
3072000, /* Mcbsp internal BICK clock frequency 3.072MHz */
0 /* frame sync pulse width (val+1) is used */
};
Mcbsp_ClkSetup mcbspClkConfigTx =
{
//Mcbsp_FsClkMode_INTERNAL,
Mcbsp_FsClkMode_EXTERNAL,
48000, /* 48KHz */
//Mcbsp_TxRxClkMode_INTERNAL,
Mcbsp_TxRxClkMode_EXTERNAL,
Mcbsp_FsPol_ACTIVE_LOW,
Mcbsp_ClkPol_FALLING_EDGE
};
/**< clock setup for the RX section */
Mcbsp_ClkSetup mcbspClkConfigRx =
{
//Mcbsp_FsClkMode_INTERNAL,
Mcbsp_FsClkMode_EXTERNAL,
48000, /* 48KHz */
//Mcbsp_TxRxClkMode_INTERNAL,
Mcbsp_TxRxClkMode_EXTERNAL,
Mcbsp_FsPol_ACTIVE_LOW,
Mcbsp_ClkPol_FALLING_EDGE
};
regards,
