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CCS/AM5718: DDR priority issue

Civet
Intellectual 360 points
Part Number: AM5718

Tool/software: Code Composer Studio

There are many master core in AM5718. These master core may access DDR memory randomly.

I want to assign the priority of access DDR for each cores. For example, assign the Highest priority for DSP.

Is there any method to achieve this?

  • 0
    TI__Guru**** 393215 points

    Please post what software (Linux, TI-RTOS) you are using, and what version?

  • 0 in reply to Biser Gatchev-XID
    Intellectual 360 points

    root@am57xx-evm:~# cat /proc/version
    Linux version 4.4.19-gdb0b54cdad (risc@risc) (gcc version 5.3.1 20160113 (Linaro GCC 5.3-2016.02) ) #7 SMP PREEMPT Thu Sep 7 10:01:08 CST 2017
    root@am57xx-evm:~#

  • 0 in reply to Civet
    TI__Mastermind 30506 points

    Hi, 

    You will want to adjust some registers. I usually recommend doing this in the bootloader so that it is in place when Linux comes up.

    Depending on where in the interconnect you would like the priority decision to be made, take a look at the PEG (see section 15.2.3.5.3.3 in the TRM).  This will bind a priority with a master.  The information gets passed to the EMIF as MTagId to determine priority of requests.  This is discussed in section 15.3.4.1.4
    As an alternative, you can use the CTRL_CORE_EMIF_INITIATOR_PRIORITY registers discussed in section 18.4.6.6, which will do a simple prioritization based on the initiator.
    I hope this is helpful to you.