I'm trying to determine if it's possible to temporarily reenter I/O isolation mode without loss of the contents of DDR3 memory, to be able to reconfigure padconf/iodelay at a later point in u-boot. I had hoped to use some helper code in internal SRAM that puts the DDR3 into self-refresh, enters I/O isolation, performs the reconfiguration, leaves I/O isolation, takes DDR3 out of self-refresh, and returns execution to code in DDR3.
The problem is that to keep DDR3 in self-refresh, CKE needs to be driven low through all this, but my impression is that the DDR3 CKE signals are not exempt from I/O isolation, which means they'd get pulled to VTT resulting in undefined behaviour.
Can you confirm that I/O isolation mode will indeed cause all DDR3 signals to go high-Z, including CKE?
If so, then it would probably be a good idea to recommend am57xx users to use a gpio-controlled switchable VTT supply that's disabled by default to prevent the DDR3 cmd/addr signals from being pulled to VDD_DDR/2 during I/O isolation, which could cause undefined behaviour in the ram and/or excessive current in the ram's input buffers. (It would be desirable to reset the ram if this were to happen, but it is very unclear when exactly EMIF asserts the ddr3 reset signal and whether software can request it to do so.)
