TMS320C6746: Rom Bootloader failed to load User bootloader

GK,

thanks for providing details of the issue that you are facing on the custom board. Can you also please clarify how you are programming the data to NAND and if you are using Block0 or block 1 for booting from NAND? If it is a single bit error in the data stored on NAND page, we expect that to be corrected during boot using the ECC mechanism. In addition to page data, can you also confirm that the ECC data on the NAND is correctly generated.

If the boards, were all working properly when you shipped to customer and have now been reported to be failing in field, I would recommend that you look at the device errata Advisory 2.3.24 to see if you have applied the patch referred to in the errata.

http://www.ti.com/lit/er/sprz304h/sprz304h.pdf

Regards,

Rahul

Hi Rahul,

Hello I work with gili (gk) on this project.

for programming we are using code composer runing nandwriter code. the nandwriter receive as an input an AIS file that is generated by AisGen tool revision 1.9. 

As specified in spraat2f 6.4 the nand is written from block 1 .

who can we confirm that the ECC data on NAND is correctly generate?

If we use recomondation in errata 2.3.24, we need to generate ais using aisGen 1.13 , how we use the patch?

If the patch code is in memory location 0x11800000 we need to make sure this location is not in use by UBL

Thanks

Ilan

Hi Rahul,

Thank you for helpful reply!

In additional to generate the bootloader from aisGen 1.13

we try to understand the issue with the last board that the flash memory is identical to functioning board

We right code that working as RBL, reading the flash memory with ecc data, configure registers according to commands in ais,

copy section data to DDR and execute the program- that's working!

We compared the ROM memory, is also identical

We replaced the flash HW in a new one and the RBL still failed to load the bootloader

Do you have any idea why the loading failed from the original RBL? 

Thank you,

GK

Hi Rahul,

I have to know if the code in bootloader from "C6748_StarterWare_1_20_04_01\nandlib" includes the correction as function in the patch of ecc nand what we found in "sillicon errata " documents.

If not how can we correct the bug in our bootloader? can we get the source code of the patch to replace the wrong function?

Thank you,

Gili

Hi Rahul

we replace the nand_ecc_rom_org by the fixed function nand_ecc_rom_fix. 

We burn several unit and left them in test (power up and down every several seconds) after several on and off loop (~500) one of the unit didnt work. when I check it with debugger

there are some times that the reading pass without any ECC error and some times that the reading has 1 bit error but s not fixed.

the code lines

// Start calcuating the correction addresses and values
AEMIF->NANDFCR |= (0x1U << 13);

// Loop until timeout or the ECC calculations are complete (bit 11:10 == 00b)
i = 1000;
do
{
temp = (AEMIF->NANDFSR & 0x00000F00)>>10;
i--;
}
while((i>0) && (temp != 0x0));

// Read final correction state (should be 0x0, 0x1, 0x2, or 0x3)
corrState = (AEMIF->NANDFSR & 0x00000F00) >> 8;

after putting breackpoint we found out that i=999, temp=0, and corrState=5

in the old code there is a loop cycle for reading corrState and this problem do not accure.

it seems that maybe a delay between start calculation and the first reading is needed maybe - after adding 

temp = (AEMIF->NANDFSR & 0x00000F00)>>10;

before the loop fix it and the reading of corrState return 3 (the ecc was compleated)

Is it correct to add this delay (maybe the status is not update immediately after ecc enable (AEMIF->NANDFCR |= (0x1U << 13); so we need to let the dsp to update the status to a value diffrent from 0 before start testing it?

How can it be that in debug mode some times we get no error in ecc and some times 1 bit error (for the same data). I am expecting to receive all the time the same result from the ecc test? 

This issue is in very high priority in our company as we need to supply the unit to the costumer as soon as possible

Best Regards

Ilan

Hi Rahul

Regarding the problem of no delay in the new patch code, I looked at the c6746 reference manual doc spruh80c,

You can see that in paragraph 8.2.5.6.6.2 page 829 for read in step 10 after enabling 4BITECC_ADD_CALC_START there need to be a dummy read before reading the ecc state.

In the patch code this reading do not exist and so when an error occurred the code do not fix the error.

after that we add a dummy read the code run correctly.

We need to know is this is the exact code that is in the patch, if so problem may occurred when the rom bootloader will use this function 

Thanks

Ilan

Hello Rahul

The DSP is running at speed of 456MHz . The EMIF on CS3 is configured with 0x041020BD. 

You are right, the issue we were facing was during loading the application by user bootloader (using nand driver with fixed function) after adding the dummy read it seems to be OK (this was check with a nand that has 1bit error). 

But as I understand the ROM bootloader read the AIS file from NAND and configure DSP registers as defined in the AIS, and then load the data (user bootloader) from nand to ram and run it. so its mean that the rom bootloader will load the user bootloader after DSP is running at full speed. if this is the case the problem may happens when the rom bootloader try to load the user bootloader.

If the rom bootloader configure the registers after loading the data from NAND, then slower speed may be OK. 

Can you confirm that the rom bootloader do not need this dummy read and if a NAND 1-4 bit error occurred in the user bootloader address space the rom bootloader will fix it correctly?

Thanks 

Ilan