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AM4372: interfacing eMMC to AM437x

Part Number: AM4372

I would like to attach an eMMC memory (compliant to eMMC spec 4.41 or 5.0) to AM437x on a custom board. The eMMC data path should be 8 bits wide.

Timing analysis shows that it is not easy to fulfill data hold timing of the eMMC in HS mode (48MHz):

The eMMC memory requires a hold time of the CMD and DATx signals of at least 3ns, referenced to the rising edge of the CLK signal. This is independent of the version of the eMMC standard (v4, v5). AM437x data sheet (SPRS851E) states an output delay of the CMD and DATx lines of at least 0.8ns in Table 5-129, also referenced to the rising CLK edge.

To get 3ns hold time at the eMMC device with 0.8ns output delay of the AM437x the CMD and DATx routing delay needs to be (3ns-0.8ns)=2.2ns longer than the CLK routing delay. Using FR4 material with a routing delay of ~170ps/in this results in CMD/DATx signal length of ~13 inch more than CLK signal length. However it is not practical to have >13 inch of PCB trace for all 8 DATx lines and the CMD line.

Is there any practical solution to attach a standard eMMC device to AM437x which fulfills timing requirements?

tom

  • Hi Tom,

    It looks like you're looking at the table for HSPE=1.  Please instead refer to the table for HSPE=0.  The timings are satisfied using HSPE=0.

    Best regards,
    Brad

  • Hi Brad,

    Thank you for your answer.

    I used the table for HSPE=1 because I want to use high speed mode (48MHz). TRM Table 17-36 defines HSPE als "High Speed Enable" so I assumed this bit has to be set for high speed modes above 24MHz. Can I use HSPE=0 even in high speed mode with 48MHz clock?

    (I also used AM335x before, and there I had to set HSPE=1, however MMC timing of AM335x differs somewhat compared to AM437x which allowed to have reasonable trace lenghths with HSPE=1 and 48MHz).

    Best regards

       Tom

  • Thomas Langhammer said:

    I used the table for HSPE=1 because I want to use high speed mode (48MHz). TRM Table 17-36 defines HSPE als "High Speed Enable" so I assumed this bit has to be set for high speed modes above 24MHz. Can I use HSPE=0 even in high speed mode with 48MHz clock?

    (I also used AM335x before, and there I had to set HSPE=1, however MMC timing of AM335x differs somewhat compared to AM437x which allowed to have reasonable trace lenghths with HSPE=1 and 48MHz).

    For AM335x you need HSPE=1 for 48 MHz SD/MMC.  For AM437x you should use HSPE=0 for 24 MHz and 48 MHz.

    FYI, if you refer to the Linux drivers you'll see there's a device tree property called "ti,needs-special-hs-handling".  That property is applied to the AM335x MMC, but not for the AM437x MMC.

  • Hi Brad,

    I found the property in the driver code and now understand how it is used, so I am able to finish emmc timing analysis successfully.

    Thank you very much for clarifying this.

    Tom