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Dm6437 MACstatus "Ownership bit not set in SOP buffer",

VSP
Prodigy 100 points


We have implemented the tftp functionality for the DM6437 without BIOS . we are using polling for Rx and Tx and not interrupts.we are able transmit the Tftp request & get the files block by block, but we found that the baord is not able to receive after certain  datablocks. when we checked the interrupt flags it shopws HOST error & when we check the MACstatus it indicates "Ownership bit not set in SOP buffer".
Let us know what might be the reason for this? how can we fix it?

Regards

Praveen

  • 0
    Genius 3575 points

    When you give a linked list of descriptors to the emac for tx or rx, the first descriptor in that list has to have the ownership flag bit set.  Looks like you are writing a descriptor to the emac HDP register that has SOP set but not OWNER.  Don't do this.  If this only happens some of the time, you probably have a race condition or unhandled case in your code.  Are you chaining descriptors together properly? All the nasty details are in spru941.

  • 0 in reply to MattLipsey
    Prodigy 100 points
    Thanks for your inputs,
    We are setting the SOP & Owner as well.
    Please check the attached code, do you feel anything is missed out? or wrongly done?
    Regards
    Praveen
  • 0 in reply to VSP
    Genius 3575 points

    With just a quick glance, you are trying to give the single RX descriptor to the HDP in both your emac_send AND emac_rcv routines.  Without knowing how you are calling these routines, they are probably going to fail.  You shouldn't be touching the rx descriptor in the emac_send routine.

  • 0 in reply to MattLipsey
    Prodigy 100 points

    Thanks for your immediate reply.

    If we donot give rx descriptor in the emac_send routine, the tx is not happening.

    Can you suggest any simple method to over come this issue?

    Regards

    Praveen

     

  • 0 in reply to VSP
    Genius 3575 points

    First off, your ISR routines need to disable emac interrupts first thing, then re-enable them on exit.  Check out spru941, section 2.16.3 for an explanation.

    ISR() {

    EMAC_EWCTL = 0; // disable emac interrupts

    // check interrupt flags for rx or tx to process

    // process any detected interrupts

    EMAC_EWCTL = 1; // re-enable emac interrupts

    }

    You also don't need to clear all the interrupt flags at the start of your routine since you are polling.  The act of writing to the HDP registers will clear pending emac interrupt flags.

  • 0 in reply to MattLipsey
    Prodigy 100 points

    Thanks MatLipsey

    We are able to fix this issue.

    The issue was Allocation of  packet descriptor and buffer for Rx was not proper .( #pragma DATA_SECTION(packet_header, ".ExtDat1"); should be #pragma DATA_SECTION(packet_header_rx, ".ExtDat1");

    Thanks for your support.

    ALso can you please help us wrt the below issue?, if you can suggest anything?

    http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/99/p/73878/292471.aspx#292471