Because of the holidays, TI E2E™ design support forum responses will be delayed from Dec. 25 through Jan. 2. Thank you for your patience.

  • State Resolved
  • Locked Locked
  • Replies 1 reply
  • Subscribers 101 subscribers
  • Views 307 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

66AK2G12: PCIe Reference clock standard logic

Srikanth Kacchu1
Expert 1185 points
Part Number: 66AK2G12
Other Parts Discussed in Thread: EVMK2GXS

Hi

Datasheet of 66AK2G12 says PCIe reference clock input is Differential LVDS input but the evaluation board(EVMK2GXS) schematics netname is mentioned as "PCIE_CLKP_CML_100MHz".

What is the standard logic for PCIe reference clock input? Is it LVDS or CML?

Regards

Srikanth Kacchu

  • 0
    TI__Mastermind 42545 points

    Hi Srikanth,

    The reference clock specification is defined in the PCI Express Card Electromechanical Specification. The clock signals are low voltage differential signals and the inputs for the K2G are compatible with the voltage levels defined in that specification. Regardless of the labeling, the clock signal should ultimately be compatible with the PCIE CME specification.

    Regards, Bill