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[TDA4VM] PCIe RC and EP mode performance issue

felix xu
Intellectual 500 points

Hi, our project requires high data throughput between two TDA4 EVMs, I follow the guide in ti-processor-sdk-linux-automotive-j7-evm-06_01_00_05 -> 3.2.2.8. PCIe End Point, two EVMs works well finally.

When I run pcitest tool at RC, EP prints DMA speed in kernel log, EP's write speed seems normal, but EP's read speed is not so good.

In PCIe protocol, memory read transaction has lower performance than memory write transaction, since they are non-posted and posted.

I connect two EVMs in PCIex1 and PCIex2, EP's read speed has no obvious boost, but EP's write speed does.

Would you please give me some explanation about why EP's read speed has no significant difference in PCIex1 and PCIex2？

Thanks

PCIe 1 lane

WRITE => Size: 33554432 bytes     DMA: YES        Time: 0.047077395 seconds      Rate: 696045 KB/s

READ => Size: 33554432 bytes      DMA: YES        Time: 0.074904360 seconds      Rate: 437464 KB/s

PCIe 2 lane

WRITE => Size: 33554432 bytes     DMA: YES        Time: 0.023590840 seconds      Rate: 1389013 KB/s

READ => Size: 33554432 bytes      DMA: YES        Time: 0.072952270 seconds      Rate: 449170 KB/s

  • 0
    TI__Expert 8250 points

    HI

    Usually the write transactions are posted and hence we see better throughput with write. To get better throughput with read, we will need to use multiple DMA channels to drive additional traffic. Each DMA channel has a finite capacity in terms of HW FIFO space and number of outstanding commands, since reads are inherently non-posted, we can be capped once we exhaust the command limit(for outstanding transactions on a single DMA channel)

  • 0
    Guru 13202 points

    Hello,

    Aside of the root cause of slower read speed, you have processors on both sides. Why don't you instruct remote EP to make writes to RC instead of making reads on RC?