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Minimum working frequency for DM365

Andrew Stepanov
Prodigy 240 points

Hello.

All my questions is about dm365 evm.

1.

What is min working frequency for  CPU ARM926EJ-S rev 5 (v5l)?

2.

At documentation mentioned that PLL Multiplier can be from 1 to 1023.

It is possible set Multiplier to 25Mhz * 1023 = 24552 Mhz. I think that PLL can't work at this frequency, doesn't he ?

3.

For da850 board  there are few statements:

 * According to the TRM, minimum PLLM results in maximum power savings.
 * The OPP definitions below should keep the PLLM as low as possible.

 * PreDiv should be set to `1' for maximum power savings.

Dоеs this right for dm365evm ?

 

Thanks!!!!!!

  • 0
    TI__Expert 5955 points

    Hello,

    1. May I ask what are you trying to achieve? The DM365 has a power down (deep sleep) mode which all device clocks are stopped and the internal oscillators are powered down. It is impossible to generate some Hz or KHz range clocks to clock the ARM since the input clock spec is either 19.2Mhz or 24Mhz or 36Mhz.

    2. You are correct. It is out of spec. The PLL can't work at this frequency.

    3. Those statements are applicable to the DM365.

    Thanks,

    Tai

  • 0 in reply to Tai Nguyen
    Prodigy 240 points

    >1. May I ask what are you trying to achieve? The DM365 has a power down (deep sleep) mode which all device clocks are stopped and the internal oscillators are powered >down. It is impossible to generate some Hz or KHz range clocks to clock the ARM since the input clock spec is either 19.2Mhz or 24Mhz or 36Mhz.

     

    I want to attach ARM core to PLL2. All other devices to PLL1.

    (Video\Audio encoders - not usable). And dynamically change ARMSS frequency with step 1Mhz.

     

    I need to know minimum working frequency for ARMSS (ARM CPU) for normal system operation (not sleep mode).

    I have 24 Mhz clock.

    I can set Pre-DIV, Post-DIV, SYSDIV2 .

    For Example, set PreDIV to 3. Does it means that ARMSS operate on 24 / (3+1) =  8 Mhz ?????

     

    >2. You are correct. It is out of spec. The PLL can't work at this frequency.

    I need to know min and max PLL working frequency.

  • 0 in reply to Andrew Stepanov
    TI__Expert 5955 points

    Hello,

    1. Please take into account the multiplier M in the calculation. Fo= Fi(1/(Pre-DIV+1))(2M/(Post-DIV+1))(1/(Sys-DIV2+1)). And the minimum is M=1. So if you would have to set one of dividers Pre-DIV or Post-DIV or Sys-DIV2 to 5 and leaving other dividers to 1 for the ARMSS to operate on 8Mhz clock.

    2. The min and max PLL spec is 135Khz-1000Mhz.

    Thanks,

    Tai

     

  • 0 in reply to Tai Nguyen
    Prodigy 240 points

    Hello.

    1.

    I want to set frequency for ARM CORE to 289 Mhz.

    In this case:

    Multiplier = 151

    PostDivider = 25

    289 = 24 * (151*2) / (25)

    Will it work?

     

    2.

    >The min and max PLL spec is 135Khz-1000Mhz.

    In above example:

    151 * 2 * 24 = 7248 is much more than allowed 1000Mhz.


    3.

    What will be actual frequency CPU CORE?

    Using INTEGER arithmetic:

    24*(151*2) / 25 = 289

    Using FLOAT arithmetic:

    24*(151*2) / 25 = 289.92

     

    THANKS!

  • 0 in reply to Andrew Stepanov
    TI__Expert 5955 points

    Hello,

    Sorry for the delay due to Holidays.

    1. It should work using your multiplier and divider numbers.

    2. The spec of 135Mhz-1000Mhz  is for the PLL output.

    3. The actual frequency will be real close to 289.92Mhz.

    Thanks,

    -Tai