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AM3352: Emulation clocks

Motoyasu Hattori
Genius 12285 points

Part Number: AM3352

Hi,

TRM said the following on P.189-190 3.1.3.1 Clock Distribution.

「Emulation Clocking: Emulation clocks are distributed by the PRCM module and are asynchronous to the ARM core clock (ARM_FCLK) and can run at a maximum of 1/3 the ARM core clock.」

 

Can users need EMU_CLOCKS setting?

Where does users set EMU_CLOCKS?

Please let me know

Thanks and best regards,

M.HATTORI

  • 0
    TI__Genius 12285 points

    Hi,
    I ask same question in details.  Please answer it.

    TRM said the following on P.189-190 3.1.3.1 Clock Distribution.

    "Emulation Clocking: Emulation clocks are distributed by the PRCM module and are asynchronous to the ARM core clock (ARM_FCLK) and can run at a maximum of 1/3 the ARM core clock."

     

    Also, according to TRM P.1223 Figure 8-10, CORE_CLKOUTM4 is same as Debugss clka.

     

    Currently ARM plans to run at 300MHz. And CLKOUTM4 = L3F_CLK plans to be set at 200Mhz. To avoid reducing performance, we want to set 200MHz on L3 Clock.   If ARM=300MHz, L3_CLK=200MHz, is it any issue to debug ARM?

     

    We have never used ETB for ARM Core.   Please advise us.

    Thanks and best regards,

     M.HATTORI.

  • 0 in reply to Motoyasu Hattori
    TI__Guru* 93341 points

    Hattori-san,

    It looks like there is some ambiguity in the statement in the TRM.  The debug subsystem requires 3 clocks:

    atclk: trace clock

    hclk: L3 OCP master clock

    pclk: configuration/instrumentation bus clocks

    To simplify the clock tree these are all derived from one debug subsystem clock (debusss_clka), and divided as necessary within the debug subsystem.   The clock with the 1/3 restriction is pclk,  which already has a div by 2 within the debug subsystem.  The other 2 have a divide by 1.  So with an L3_CLK=200MHz, debugss_clka=atclk=hclk=200MHz, and pclk=100MHz.  So you can run ARM=300MHz and still run the debug subsystem (and L3) at 200MHz.

    Regards,

    James