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TDA4vM LPDDR4 Layout

H-J
Intellectual 300 points
Other Parts Discussed in Thread: TDA4VM

1,Does TDA4vM LPDDR4 wiring need to consider packaging delay compensation?If necessary, can you provide the TDA4vM internal packaging delay table?
2,Can you provide IBIS model for TDA4vM?
3,Why does LPDDR4_CKE0 and LPDDR4_CA0 use different impedance in TDA4vM EVM LPDDR4 routing?
LPDDR4_CKE0(6mil-40ohm & 6mil-40ohm),LPDDR4_CA0(8mil-33ohm & 3mil-66ohm)

  • 0
    TI__Guru 53695 points

    1 and 2.  Yes, the LPDDR4 delay requirements does need to include the TDA4vM package model.  Both the S-Param model of the package and the IBIS model are available on CDDS.

    3. CKE should follow the same routing requirements as CA (2x impedance for branched segments).  EVM did not do this correctly for CKE signals.