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DM365: Voice Codec: What is the sampling frequency ? 8 or 16, 16..48 or any kHz?

What is the sampling frequency for the DM365 internal Voice Codec?

 

I'm in little trouble.

 

8 or 16 kHz? 16..48kHz? Any?

 

1) 8kHz or 16kHz ? (only one of two?)

 

1a) DM365 DataSheet (Rev. November2010)

page 201

“Sampling frequency: 8 KHz or 16 KHz ”

 

1b) DM36x Voice Codec User's Guide (SPRUFI9B - Rev. Jul.2010)

page 9, page 11, page 12

“Sampling frequency: 8 KHz or 16 Khz ”

 

But, There are no any fields in any voice codec registers where we can switch 8 or 16 kHz.

 

Instead of this, we can see that 'Fs' is derived from VoiceCodec Operational Frequency as

Fs = VC_Freq / 256

 

VoiceCodec Frequency is derived from PLL2controller via PPL2C.DIV4 and PERI_CLKCTL .DIV2 dividers.

 

2) 16kHz ... 48kHz ?

 

DM36x ARM Subsytem User's Guide (SPRUFG5A - Rev.Aug.2009)

 

page 33, Section 5.2.4

The voice codec module supports the sampling frequency (Fs) from 16 KHz to 48 KHz.

 

3) Any?

 

DM36x ARM Subsytem User's Guide

page 33, Section 5.2.4

...

voice codec clock to be same or close to 256xFs.

• Voice codec clock frequency = PLLC2SYSCLK4/(DIV2+1)

 

Hmmm...

 

As I understand (look at the formula above) the value of 'DIV2' is value from PERI_CLKCTL (0x01C40048) register bits 15:7 (see page 148, section 9.12.19) and the 'PLLC2SYSCLK4' is frequency in Hz.

 

PLLC2SYSCLK4 freq = PLL2freq / (DIV4+1)

where 'DIV4' is value from PLLC2_PLLDIV4 register (0x01C40C00+0x160). See page 63, section 6.6.22.

 

Well...

 

The final formula for sampling frequency is...

 

Fs = ( ( PLL2freq / (DIV4+1) ) / (DIV2 +1) ) / 256

 

where:

  • Fs – sampling frequency (Hz) for voicecodec;

  • PLL2freq – frequency of PLL2-out (Hz);

  • DIV4 – value from PLLC2_PLLDIV4 (0x01C40C00+0x160) register, bits 4..0, and bit15=1(enable);

  • DIV2 – value from PERI_CLKCTL (0x01C40048) register, bits 15:7.

 

It's a correct? Can you confirm this?

 

If this is correct, then I can write any value in these dividers.

For example.

If PPL2freq=594MHz and DIV4=9 (value from 0x01C40C00+0x160 is 0x8009), DIV2=3 (bits 15:7 from 0x01C40048 is equal to '000000011') then...

Fs = 594MHz / (9+1) / (3+1) / 256 = 594MHz / 10 / 4 / 256 = 58 007 Hz =~ 58kHz

is sampling frequency for voicecodec will be 58 kHz ?

It's a correct?

 

---

With impatience I wait for an answer!

 

 

 

 

  • Hi, 

     

    senchuss said:

    The final formula for sampling frequency is...

     

    Fs = ( ( PLL2freq / (DIV4+1) ) / (DIV2 +1) ) / 256

     

    where:

    • Fs – sampling frequency (Hz) for voicecodec;

    • PLL2freq – frequency of PLL2-out (Hz);

    • DIV4 – value from PLLC2_PLLDIV4 (0x01C40C00+0x160) register, bits 4..0, and bit15=1(enable);

    • DIV2 – value from PERI_CLKCTL (0x01C40048) register, bits 15:7.

     

    It's a correct? Can you confirm this?

    The above formula and understanding is correct. You can control sampling rate using the PERI_CLKCTL and DIV4 register of the PLL2.

    The spec sampling frequency of the internal voice codec is only 8 and 16Khz. So you can configure the dividers in above formula to get those sampling frequencies.

    Regards,

    anshuman

    PS: Please mark this post as verified, if you think it has answered your questions. Thanks