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66AK2G12: Clock tree tool mismatch

Graziano Rufolo
Intellectual 445 points
Part Number: 66AK2G12

Hi,

I am designing a board with 66AK2G12 and I am using Clock tree tool v.1.0.0.2 that allow to select this device and silicon revision 1.0.

For my purpose I need to obtain a 25 MHz clock signal on CLKOUT ball H23 for two Ethernet phy in MII mode. According to SPRUHY8I TRM, I can use NSS/IEP PLL that generates 1GHz clock signal, divided for  20 factor, obtain 50MHz. Through a 2 factor of division and the mux enable signal set to 1, I obtain 25 Mhz at the output.  

   

Now I am checking with CTT if this choice is correct but I see that the division factor is 200 and not 20, 2.5 MHz clock signal reaches the CLKOUT pad and not 25 MHz. 

Please can you confirm that this is an error on CTT and the TRM is correct?

Regards

Graziano Rufolo

Hardware/Firmware Engineer

Hitachi Rail

  • 0
    TI__Guru**** 161600 points

    Hi Graziano,

    You should be able to change the dividers/multipliers in the CTT. See the CLKOUT description in the device Datasheet, section 5.9.3.8
    Output Clocks:
    "  The device provides several system clock outputs. Summary of these output clock outputs are as follows:
    • CLKOUT – CLKOUT port provides an option to output 50 MHz or 25 MHz clock. This clock can be used as a reference clock for RMII or MII Ethernet companion devices."

    Best Regards,
    Yordan

  • 0 in reply to Yordan Kovachev
    Intellectual 445 points

    Hi Yordan,

    thank you for your response.

    Yes, I am sure that CLKOUT can provide 50 MHz or 25 MHz reference clock respectively for RMII or MII but I think that CTT is not aligned with TRM.

    I understood that dividers/multipliers can be changed in PLLs but the dividers (DIV) outside the PLL are fixed. As you can see in first figure above (page 3399 in TRM) CLKOUT pad is driven by MUX and its input comes from the output of 20-factor divider.

    Therefore NSS PLL shall drive 1 GHz in order to have 50MHz at the output of divider and 25-50 MHz (for MII or RMII) at the output of MUX basing of enable signal driven by control module. But in CTT the corresponding divider at the input of MUX has a value of 200.

    If my explanation is correct, this version of CTT has an error and I ask if it is possible to update it in order to have a rielable tool for design.

    Regards

    Graziano Rufolo

    Hardware/Firmware Engineer

    Hitachi Rail

  • 0 in reply to Graziano Rufolo
    TI__Guru**** 161600 points

    Hi,

    If my explanation is correct, this version of CTT has an error and I ask if it is possible to update it in order to have a rielable tool for design.

    Yes, your understanding should be correct. I also came to this conclusion. I will notify the developers of the CTT and the hw team to take a look at this.

    Best Regards,
    Yordan

  • 0 in reply to Yordan Kovachev
    TI__Mastermind 42545 points

    Hi Graziano,

    I have filed a bug against the clock tree tool to get this corrected.  Watch for an update on the web in the near future.

    Regards, Bill