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[TDA4VM] About MCU RGMII Ethernet

Manwoo Kim
Intellectual 565 points
Other Parts Discussed in Thread: TDA4VM, DP83867E

Hi,

Actually, it is question about Ethernet PHY(DP83867ERGZ) and TDA4VM.

I have three qestions about RGMII RX signal (this signal goes to TDA4VM from ethernet PHY, DP83867E) of MCU ethernet PHY.

1. We have measured MCU ethernet RX signal, and this PHY signal is very unclean.

   Q) We can't upload the graph of rx signal measured, so could you please share EVM's MCU ethernet RX signal if you have?

2. We normally change the RX signal strength using damping resistors.

   Q) Could we change the RX signal strength by changing the register of PHY?

3. We try to change the internal CLK delay, when we measured the 1G ethernet.

   Q) When we set the internal CLK delay as 2ns, this quality is not good. But, we set the internal CLK delay as 2.25ns or 2.5ns, the quallity is good.

        Is it normal? We think the margin is not enough.

Please give me the commnets about the above questions.

Thanks,

Manwoo Kim

  • 0
    TI__Mastermind 27743 points

    Hello Manwoo Kim,

    I assume you enabling MCU CPSW on your custom board.

    Below are my replies to your queries -

    Manwoo Kim said:

       Q) We can't upload the graph of rx signal measured, so could you please share EVM's MCU ethernet RX signal if you have?

    As RGMII interface timing budgets are prescribed by the standard and won't vary between EVMs/boards, I would recommend you to refer to the below app note from TI which describes timing requirements for RGMII. In TI EVM as well we meet the same timing requirements of 2.5 

    Also refer to CPSW2G RGMII Timings section in device data manual.

    Manwoo Kim said:

       Q) Could we change the RX signal strength by changing the register of PHY?




    DP83867 has IO_MUX_CFG register for impedance control. You can use that.

    Manwoo Kim said:

    When we set the internal CLK delay as 2ns, this quality is not good. But, we set the internal CLK delay as 2.25ns or 2.5ns, the quallity is good.

            Is it normal? We think the margin is not enough.

    Yes, this is normal. The RGMII spec requires delay between clock and data to be 2.5ns. Now due to PCB trace length, PHY delays (if enabled), the actual delays measured can be different.

  • 0 in reply to Prasad Jondhale
    Intellectual 565 points

    Hi, Prasad Jondhale!

    Thanks for your reply!

    We have checked register for impedance control, and I have more questions.

    1. We saw the app note recommended, and there is graph of RGMII delay signal (Figure 4).

     Q) Is this figure EVM's signal? What's mean customer EVM?

    2. We think there are strap configuration pins for setting the clock skew by changing the resistors.

     Q) We have changed the resistors, but we got the same result. Does it need more process? (for example, register setting)

    3. Datasheet describes IO_IMPEDANCE_CTRL registers can set the output impedance.

     Q) Is this register for just out impedance control? If we change the IO_IMPEDANCE_CTRL registers, does it not affect TX signal?

    Please give me a answer!

    Thanks,

    Manwoo kim

  • 0 in reply to Manwoo Kim
    TI__Mastermind 27743 points

    Manwoo Kim said:

     Q) Is this figure EVM's signal? What's mean customer EVM?

    This applies to EVM or customer EVM both. It is generic diagram as per IEEE RGMII specification. 

    Manwoo Kim said:

     Q) We have changed the resistors, but we got the same result. Does it need more process? (for example, register setting)

    You can use CCS GEL scripts provided in the PDK directory to read the values of delay/skew values. You can use GEL file located at cpsw\tools\debug_gels\cpsw_mdio_config.gel. 

    Also please share CPSW statistics. To get those statistics, you need to load GEL file located at cpsw\tools\debug_gels\cpsw_stats_print_regs.gel and run get stats function for CPSW2G.

    Manwoo Kim said:

     Q) Is this register for just out impedance control? If we change the IO_IMPEDANCE_CTRL registers, does it not affect TX signal?

    As mentioned in comment of driver code. It is for output signals.

    /*! Output impedance in milli-ohms. Ranging from 35 to 70 ohms
    * in steps of 1.129 ohms */
    uint32_t impedanceInMilliOhms;

    Refer to Dp83867_setOutputImpedance function in cpsw\src\phy\dp83867.c for programming this register.

     

  • 0 in reply to Prasad Jondhale
    Intellectual 565 points

    Hi, Prasad Jondhale.

    Thanks for your reply.

    I have more questions.

    1) I don't understand about second answer exactly. Does it changed directly if I set HW resistor?

       Can we just check the skew value which is set by HW setting?

    2) We already asked about impedance of RX signal. How about TX signal? Could we chanage the impedance?

    How can we cahnge the impedance if we can?

    Thanks,

    Manwoo Kim

  • 0 in reply to Manwoo Kim
    TI__Mastermind 27743 points

    Hello Manwoo,

    Manwoo Kim said:

       Can we just check the skew value which is set by HW setting?

    Yes, you can change HW register values to get different delay values.

    Manwoo Kim said:

    2) We already asked about impedance of RX signal. How about TX signal? Could we chanage the impedance?

    How can we cahnge the impedance if we can?

    I will check on this with our PHY team. Thanks.

  • 0 in reply to Prasad Jondhale
    Intellectual 565 points

    Hi, Prasad Jondhale.

    Thanks for your response.

    I am waiting for your comment!

    Thanks,

    Manwoo Kim

  • 0 in reply to Manwoo Kim
    TI__Mastermind 27743 points

    Hello Manwoo Kim,

    Closing this thread as we are discussing the impedance issue on https://e2e.ti.com/support/j721e/f/1026/t/861708

  • 0 in reply to Prasad Jondhale
    Intellectual 565 points

    Hi,

    I think what you told the posting have not same issue.

    There is no discussion about impedance.

    I don't understand why did you recommend the posting.

    Please check the posting and give me a comment again.

    Thanks,

    Manwoo Kim.

  • 0 in reply to Manwoo Kim
    TI__Mastermind 27743 points

    Hello Manwoo Kim,

    Sorry for the confusion. I checked with PHY team and the impedance control only applies to TX pins of PHY (RX of SOC) as per them.

    In case needed for RX pins of PHY (TX of SOC), SOC needs to apply it. 

    You can follow the other thread where our apps team has replied about configuring impedance in TDA4xx/J721E devices.

  • 0 in reply to Prasad Jondhale
    Intellectual 565 points

    Hi, Prasad Jondhale

    Thanks for your reply.

    I don't understand why I follow the other thread.

    I think this post is in TDA4/J721E forum, so I believe this post can get the answer.

    Nevertheless, Should I follow the other thread? Does it mean I should make new post?

    Thanks,

    Manwoo Kim

  • 0 in reply to Manwoo Kim
    TI__Mastermind 27743 points

    Hello Manwoo Kim,

    From your earlier questions, I believe the requirement was to configure impedance for CPSW TX pins.

    Now PHY only supports configuring impedance to it's TX which is basically CPSW RX pins.

    So the only option left to enable impedance configuration on CPSW TX pins is to use SOC feature which other post has details about.

    Let me know if this clarifies. Please start a new thread with more details in case this doesn't resolve your question.