[TDA4VM] TIDL Question on optimization of the single net with multiple output

Hello All,

Currently i meet an issue which TIDL log is

"----------------------- TIDL Process with TARGET DATA FLOW ------------------------

#    0 . ..OUT_FEAT_MAP READ MSMC not enough in tidl_conv2d_mma
OUT_FEAT_MAP READ MSMC not enough in tidl_conv2d_mma "

Layer Cycles, kernelOnlyCycles, coreLoopCycles,   LayerSetupCycles,   dmaPipeupCycles, dmaPipeDownCycles, PrefetchCycles,    copyKerCoeffCycles,  LayerDeinitCycles, LastBlockCycles, paddingTrigger,   

48020086,          13189,                            13357,                 47995860,            3493,                         359,                                      1764,                  16,                                                   505,                      13189,            298,           

paddingWait,  LayerWithoutPad,  LayerHandleCopy,

1127,                 48017062,           2512

The MMA kernel cycle is only 13189. but the layersetup cycle is 47995860. So i guess the data flow should be like this: 1. move some data from msmc to DDR, then 2. move data from DDR to MSMC;

Since the input size of this net is small.  And my net is single input with multiple output. do you know any optimization or special import file configuration? Could you please help me out!

Thanks a lot!

Best Regards,

Sam