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AM5746: PRU Ethernet PHY address

rei
Mastermind 6155 points

Part Number: AM5746
Other Parts Discussed in Thread: TLK105L

Hi,
My customers hope to use PRU-ICSS as Ethernet MAC.

First, they use TMDSIDK574 and example project.
(NIMU_ICSS_BasicExample_idkAM574x_wSoCLib_armExampleproject)

They confirmed the response of ping command from PC. Next, they try the same with customer's custom board. Since the hardware is different from IDK, it changed following.

・ Enable pins PRUSS2_MDIO, PURSS2_MII0, PRUSS2_MII1
・Change phy_addr as follows

main_am57xx.c Line 140,141
/* ICSS EMAC PHY address definitions */
#define BOARD_ICSS_EMAC_PORT0_PHY_ADDR (0U) -> 0x1F
#define BOARD_ICSS_EMAC_PORT1_PHY_ADDR (1U) -> 0x1E

”ping” command does not respond on the customer's board. There is no problem with the waveform of MII, and data is sent to AM5746. However, data is not stored in OCMC_RAM of AM5746.

(PRU-ICSS2 Ethernet0)

Question1:
Isn't define just enough to change phy_addr?

Question2:
Customers review TRM and　ICSS_DUAL_EMAC_Firmware_design_Guide.
Are there other documents that are useful for PRU development?

AM5746
TI-RTOS
pdk_ am57xx_1_0_11
bios_6_76_00_08

Regards, Rei

  • 0
    TI__Guru**** 393215 points

    Hi,

    Your query has been assigned to a TI engineer. Please note that feedback may be delayed due to holidays in the USA.

  • 0 in reply to Biser Gatchev-XID
    TI__Mastermind 43296 points

    Rei,

    >>Since the hardware is different from IDK,

    Is the pinmux generated based on the specific hardware?

    Which type of PHY is used in the custom board? Is it the same as used on AM572x IDK?

    Starting from ICSS_EMAC driver loopback example is probably easier to debug than the NIMU_ICSS example.

    Regards,

    Garrett

  • 0 in reply to Garrett Ding
    Mastermind 6155 points

    Hi Garrett,
    Thank you for your reply. I confirmed to customers about pinmux and phy.
    Customers are using their custom board pinmux configuration.
    PRU.csv

    Fullscreen boardPadDelayInit_MIIMDIO.c Download 
    /* PRUSS2_MDIO - pr2_mdio_data on D14 - MyPRUSS2_MDIO1 */
     {0x16A8, 0xD000B, {0x0, 0, 0}, {0x0, 0, 0}, {0x0, 0, 0}},

/* PRUSS2_MDIO - pr2_mdio_mdclk on C14 - MyPRUSS2_MDIO1 */
     {0x16A4, 0x1000B, {0x0, 0, 0}, {0x0, 0, 0}, {0x0, 0, 0}},

/* PRUSS2_MII0 - pr2_mii_mt0_clk on F12 - MyPRUSS2_MII4 */
     {0x16B8, 0xD000B, {0x0, 0, 0}, {0x0, 0, 0}, {0x0, 0, 0}},

/* PRUSS2_MII0 - pr2_mii0_txen on B12 - MyPRUSS2_MII4 */
     {0x16D4, 0x9000B, {0x0, 0, 0}, {0x0, 0, 0}, {0x0, 0, 0}},

/* PRUSS2_MII0 - pr2_mii0_txd3 on A11 - MyPRUSS2_MII4 */
     {0x16D8, 0x9000B, {0x0, 0, 0}, {0x0, 0, 0}, {0x0, 0, 0}},

/* PRUSS2_MII0 - pr2_mii0_txd2 on B13 - MyPRUSS2_MII4 */
     {0x16DC, 0x9000B, {0x0, 0, 0}, {0x0, 0, 0}, {0x0, 0, 0}},

/* PRUSS2_MII0 - pr2_mii0_txd1 on A12 - MyPRUSS2_MII4 */
     {0x16E0, 0x9000B, {0x0, 0, 0}, {0x0, 0, 0}, {0x0, 0, 0}},

/* PRUSS2_MII0 - pr2_mii0_txd0 on E14 - MyPRUSS2_MII4 */
     {0x16E4, 0x9000B, {0x0, 0, 0}, {0x0, 0, 0}, {0x0, 0, 0}},

/* PRUSS2_MII0 - pr2_mii0_rxdv on G14 - MyPRUSS2_MII4 */
     {0x16EC, 0xD000B, {0x0, 0, 0}, {0x0, 0, 0}, {0x0, 0, 0}},

/* PRUSS2_MII0 - pr2_mii_mr0_clk on A13 - MyPRUSS2_MII4 */
     {0x16E8, 0xD000B, {0x0, 0, 0}, {0x0, 0, 0}, {0x0, 0, 0}},

/* PRUSS2_MII0 - pr2_mii0_rxd3 on F14 - MyPRUSS2_MII4 */
     {0x16F0, 0xD000B, {0x0, 0, 0}, {0x0, 0, 0}, {0x0, 0, 0}},

/* PRUSS2_MII0 - pr2_mii0_rxd2 on A19 - MyPRUSS2_MII4 */
     {0x16F4, 0x5000B, {0x0, 0, 0}, {0x0, 0, 0}, {0x0, 0, 0}},

/* PRUSS2_MII0 - pr2_mii0_crs on B18 - MyPRUSS2_MII4 */
     {0x1724, 0x5000B, {0x0, 0, 0}, {0x0, 0, 0}, {0x0, 0, 0}},

/* PRUSS2_MII0 - pr2_mii0_rxer on G12 - MyPRUSS2_MII4 */
     {0x16B4, 0xD000B, {0x0, 0, 0}, {0x0, 0, 0}, {0x0, 0, 0}},

/* PRUSS2_MII0 - pr2_mii0_rxd1 on A18 - MyPRUSS2_MII4 */
     {0x16F8, 0xD000B, {0x0, 0, 0}, {0x0, 0, 0}, {0x0, 0, 0}},

/* PRUSS2_MII0 - pr2_mii0_rxd0 on C15 - MyPRUSS2_MII4 */
     {0x170C, 0xD000B, {0x0, 0, 0}, {0x0, 0, 0}, {0x0, 0, 0}},

/* PRUSS2_MII0 - pr2_mii0_col on F15 - MyPRUSS2_MII4 */
     {0x1728, 0xD000B, {0x0, 0, 0}, {0x0, 0, 0}, {0x0, 0, 0}},

/* PRUSS2_MII0 - pr2_mii0_rxlink on A16 - MyPRUSS2_MII4 */
     {0x1710, 0xD000B, {0x0, 0, 0}, {0x0, 0, 0}, {0x0, 0, 0}},

/* PRUSS2_MII1 - pr2_mii_mt1_clk on AC5 - MyPRUSS2_MII5 */
     {0x1774, 0x5000B, {0x0, 0, 0}, {0x0, 0, 0}, {0x0, 0, 0}},

/* PRUSS2_MII1 - pr2_mii1_txen on AB4 - MyPRUSS2_MII5 */
     {0x1778, 0x1000B, {0x0, 0, 0}, {0x0, 0, 0}, {0x0, 0, 0}},

/* PRUSS2_MII1 - pr2_mii1_txd3 on AD4 - MyPRUSS2_MII5 */
     {0x177C, 0x1000B, {0x0, 0, 0}, {0x0, 0, 0}, {0x0, 0, 0}},

/* PRUSS2_MII1 - pr2_mii1_txd2 on AC4 - MyPRUSS2_MII5 */
     {0x1780, 0x1000B, {0x0, 0, 0}, {0x0, 0, 0}, {0x0, 0, 0}},

/* PRUSS2_MII1 - pr2_mii1_txd1 on AC7 - MyPRUSS2_MII5 */
     {0x1784, 0x1000B, {0x0, 0, 0}, {0x0, 0, 0}, {0x0, 0, 0}},

/* PRUSS2_MII1 - pr2_mii1_txd0 on AC6 - MyPRUSS2_MII5 */
     {0x1788, 0x1000B, {0x0, 0, 0}, {0x0, 0, 0}, {0x0, 0, 0}},

/* PRUSS2_MII1 - pr2_mii1_rxdv on AC3 - MyPRUSS2_MII5 */
     {0x1790, 0x5000B, {0x0, 0, 0}, {0x0, 0, 0}, {0x0, 0, 0}},

/* PRUSS2_MII1 - pr2_mii_mr1_clk on AC9 - MyPRUSS2_MII5 */
     {0x178C, 0x5000B, {0x0, 0, 0}, {0x0, 0, 0}, {0x0, 0, 0}},

/* PRUSS2_MII1 - pr2_mii1_rxd3 on AC8 - MyPRUSS2_MII5 */
     {0x1794, 0x5000B, {0x0, 0, 0}, {0x0, 0, 0}, {0x0, 0, 0}},

/* PRUSS2_MII1 - pr2_mii1_rxd2 on AD6 - MyPRUSS2_MII5 */
     {0x1798, 0x5000B, {0x0, 0, 0}, {0x0, 0, 0}, {0x0, 0, 0}},

/* PRUSS2_MII1 - pr2_mii1_crs on E17 - MyPRUSS2_MII5 */
     {0x1698, 0x5000B, {0x0, 0, 0}, {0x0, 0, 0}, {0x0, 0, 0}},

/* PRUSS2_MII1 - pr2_mii1_rxer on B19 - MyPRUSS2_MII5 */
     {0x172C, 0xD000B, {0x0, 0, 0}, {0x0, 0, 0}, {0x0, 0, 0}},

/* PRUSS2_MII1 - pr2_mii1_rxd1 on AB8 - MyPRUSS2_MII5 */
     {0x179C, 0x5000B, {0x0, 0, 0}, {0x0, 0, 0}, {0x0, 0, 0}},

/* PRUSS2_MII1 - pr2_mii1_rxd0 on AB5 - MyPRUSS2_MII5 */
     {0x17A0, 0x5000B, {0x0, 0, 0}, {0x0, 0, 0}, {0x0, 0, 0}},

/* PRUSS2_MII1 - pr2_mii1_col on D18 - MyPRUSS2_MII5 */
     {0x1694, 0x5000B, {0x0, 0, 0}, {0x0, 0, 0}, {0x0, 0, 0}},

/* PRUSS2_MII1 - pr2_mii1_rxlink on C17 - MyPRUSS2_MII5 */
     {0x1730, 0xD000B, {0x0, 0, 0}, {0x0, 0, 0}, {0x0, 0, 0}},

    PHY：LAN8700(microchip)
    Port：PRU-ICSS2 Ethernet0

    Customers sent additional information to me.

    They checked PRU_CONTROL and PRU_STATUS registers.
    Registers are following state(value) before/after receiving the packet.

    Before:
    PRU_CONTROL:0x8003
    PRU_STATUS:0x0~0x2FF
    After:
    PRU_CONTROL:0x1
    PRU_STATUS:0x1F

    PRU_CONTROL:ENABLE field is 0 affter receiving and PRU_STATUS:PCOUNTER is 0x1F.

    I checked TRM and following documents, but I can't know the meaning what STATUS:0x1F .
    processors.wiki.ti.com/.../PRU-ICSS
    elinux.org/.../Am335xPruReferenceGuide.pdf

    Regards, Rei

  • 0 in reply to rei
    Intellectual 310 points

    Hi Garrett,

    Thank you for your help.
    We are expecting your reply.

    Best regards,

    Hajime

  • 0 in reply to Hajime.k
    TI__Mastermind 43296 points

    Hi Hajime,

    It was U.S holiday. I will look into Rei's update and see if anything may be mis-configured...

    Regards,
    Garrett

  • 0 in reply to Garrett Ding
    TI__Mastermind 43296 points

    Hi Rei, Hajime,

    PRU_STATUS:0x1F indicates the PRU is accessing the IRAM address 0x1F x 4 = 0x7C. 

    You may review the document -  to first check if alive/link bits are set in MDIO registers...

    Regards,
    Garrett

  • 0 in reply to Garrett Ding
    Intellectual 310 points

    Hi Garrett,


    When the PRU stopped its operating immediately after receiving the frame and then PCOUNTER indicates 0x1F, we confirmed that the following instruction was executed.

    Micro_scheduler.asm : Line 211 "HALT"

    What abnormalities cause the above HALT?
    For example, what kind of frame is received to reach HALT?

    Best regards,
    Hajime

  • 0 in reply to Hajime.k
    TI__Mastermind 43296 points

    Hajime,

    The NIMU_ICSS_BasicExample_idkAM574x_wSoCLib_armExampleproject is based on AM57x with TLK105L PHY. Before you dig into the PRU instruction, you may need compare the PHY difference between TLK105L and LAN8700, and re-configure the LAN8700 registers properly, make sure the PHY alive and link is up...

    As the code commented, ERROR: HALT should never happen.

    Regards,
    Garrett

  • 0 in reply to Garrett Ding
    Intellectual 310 points

    Hi Garrett, rei

    We were able to notice a mistake.
    Thank you for your cooperation.

    Best regards,

    Hajime