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AM3505 DDR2 data align problem

When I write as follows "test code" 32-bit*8 into DDR2 and clock = 166Mhz, have incorrect on as follows "read back result"

but I adjust clock = 96Mhz that it's can correctly.

What codes or registers cause like as this problem, thanks!

 

test code:

        __u32 i,j;
        __u32 data[8];
        volatile __u32 *ptr = (__u32 *) RAM_BASE;


        debug( "\n\r> sdram testing : #" , 0 );

#if 1
 
         ptr = (__u32 *) RAM_BASE;

                   ptr[0] = 0;
                   ptr[1] = 1;
                   ptr[2] = 2;
                   ptr[3] = 3;
                   ptr[4] = 4;
                   ptr[5] = 5;
                   ptr[6] = 6;
                   ptr[7] = 7;

 
        while( 1 ) {

                   ptr = (__u32 *) RAM_BASE;

                   data[0] = ptr[0] ;
                   data[1] = ptr[1] ;
                   data[2] = ptr[2] ;
                   data[3] = ptr[3] ;
                   data[4] = ptr[4] ;
                   data[5] = ptr[5] ;
                   data[6] = ptr[6] ;
                   data[7] = ptr[7] ;

                   for(i=0; i<8; i++) {
                       debug( "\n\r> [%x] :", i );
                       debug( "sdram val = %x " ,  data[i]  );
                  }

                   if( getcode() != -1 ) break;
        }


read back result (incorrect):

> [00000000] :sdram val = 00000001 (should be 00000000)
> [00000001] :sdram val = 00000002 (should be 00000001)
> [00000002] :sdram val = 00000003 (should be 00000002)
> [00000003] :sdram val = 00000000 (should be 00000003)
> [00000004] :sdram val = 00000005 (should be 00000004)
> [00000005] :sdram val = 00000006 (should be 00000005)
> [00000006] :sdram val = 00000007 (should be 00000006)
> [00000007] :sdram val = 00000004 (should be 00000007)