Part Number: DRA72XEVM
Hi TI Forum,
We are trying to enable Reverse View Camera usecase on our custom board having TDA2xx SoC. We are using Vision SDK 3.0.7
According to the Steps as specified in VisionSDK_Linux_UserGuide.pdf - > 3.5 - Early M4 based chains for VSDK-Linux builds
enabled the EARLY_USECASE_ENABLE to "yes" in the below cfg.mk file
vision_sdk/apps/configs/tda2xx_evm_linux_all/cfg.mk
#Enable/Disable early use-cases (yes/no)
EARLY_USECASE_ENABLE=yes
And also enabled early_capture_late_weston usecase in uc_cfg.mk file
To ensure the Reverse camera gets started early within 5-6 seconds, we are loading IPU2 core during uboot.We disabled the pheripherals used by ipu core in dts as per the document :
DISABLE_COMPLETE(vip1);
DISABLE_COMPLETE(dss);
But with dss disabled, it leads to an error when apps.out is executed.In we enable dss in kernel the displays goes off and shows "out of range" signal.
Below is the Error message that appears after running apps.out: The usecase will not run as the execution is stuck in System_init(chains_main.)
### WARNING ###: use the following [read | write | set bit | clear bit | dump] commands at your own risk!
No address check done, may generate:
- bus error (invalid or not accessible <physical address>,
- platform crash/hang (bad <value>).
Read any OMAP memory address (register), given its <physical address> or <name> as listed in TRM.
Write <value> at any OMAP memory address (register), given its <physical address> or <name> as listed in TRM.
Set bit at <position> into any OMAP memory address (register), given its <physical address> or <name> as listed in TRM.
Clear bit at <position> into any OMAP memory address (register), given its <physical address> or <name> as listed in TRM.
Dump a range of OMAP memory addresses, from <start address> to <end address>.
Note all addresses within given range must be valid and accessible.
### WARNING ###: use the following I2C [read | write] commands at your own risk!
No address check done, may generate:
- I2C bus error (invalid or not accessible <physical address>,
- platform crash/hang (bad <value>).
Read I2C register at address <addr> from I2C chip at <chip-addr> on I2C <bus>.
Write <value> in I2C register at address <addr> from I2C chip at <chip-addr> on I2C <bus>.
Calling System_init
[HOST] OSA: MEM: 0: Mapped 0xa0100000 to 0xb6000000 of size 0x00100000
[HOST] OSA: MEM: 1: Mapped 0x84203000 to 0xa3400000 of size 0x12c00NET: Registered protocol family 41
000
[HOST] OSA: MEM: 2: Mapped 0xa0200000 to 0xb620f000 of size 0x00040000
[HOST] OSA: MEM: 3: Mapped 0xa02c0000 to 0xb624f000 of size 0x00080000
[HOST] OSA: MEM: 4: Mapped 0x00000000 to 0x00000000 of size 0x00000000
This is the dts file with late attach configurations:
/*
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/* dummy comment */
#include "dra7-evm-vision.dts"
#define DISABLE_PRCM(label) &label { ti,no-idle; ti,no-reset-on-init; }
#define DISABLE_COMPLETE(label) &label { status = "disabled"; ti,no-idle; ti,no-reset-on-init; }
#define LATE_ATTACH(label) &label { ti,late-attach; ti,no-idle; ti,no-reset-on-init; }
#define NO_MAP(label) &label { \
/delete-property/ reusable; \
no-map; }
DISABLE_COMPLETE(vip1);
/*DISABLE_COMPLETE(dss);*/
LATE_ATTACH(ipu1);
LATE_ATTACH(timer11);
LATE_ATTACH(timer7);
LATE_ATTACH(timer8);
LATE_ATTACH(mmu_ipu1);
NO_MAP(ipu1_cma_pool);
LATE_ATTACH(ipu2);
LATE_ATTACH(timer3);
LATE_ATTACH(timer4);
LATE_ATTACH(timer9);
LATE_ATTACH(mmu_ipu2);
NO_MAP(ipu2_cma_pool);
#if 1
/*
* Memory reserved for IOMMU table carveout 0xbfc00000 for length 0x100000
* Page Table Address for IPU1 0xbfc00000
* Page Table Address for IPU2 0xbfc08000
* Page Table Address for DSP1 0xbfc10000
* Page Table Address for DSP2 0xbfc18000
*/
&reserved_mem {
latea_pagetbl: late_pgtbl@bfc00000 {
reg = <0x0 0xbfc00000 0x0 0x100000>;
no-map;
status = "okay";
};
};
#endif
&ipu2_cma_pool {
reg = <0x0 0x99000000 0x0 0x5000000>;
};
&dsp1_cma_pool {
reg = <0x0 0xa1000000 0x0 0x2000000>;
};
&ipu1_cma_pool {
reg = <0x0 0x9e000000 0x0 0x2000000>;
};
&dsp2_cma_pool {
reg = <0x0 0xa3000000 0x0 0x2000000>;
};
&dispc{
ti,no-reset-on-init;
ti,no-idle;
};
&dss {
/delete-property/ ti,enable-opt-clks-on-reset;
ti,no-reset-on-init;
ti,no-idle;
is_shared=<1>;
};
&reserved_mem {
cmem_ocmc: cmem@40300000 {
compatible = "shared-dma-pool";
reg = <0x0 0x40300000 0x0 0x300000>;
sram = <&ocmcram1>;
no-map;
status = "okay";
};
cmem_pool: cmem@A8000000 {
compatible = "shared-dma-pool";
reg = <0x0 0xA8000000 0x0 0x4000000>;
no-map;
status = "okay";
};
vsdk_sr1_mem: vsdk_sr1_mem@84000000 {
compatible = "shared-dma-pool";
reg = <0x0 0x84000000 0x0 0x10000000>;
status = "okay";
};
vsdk_sr0_mem: vsdk_sr0_mem@A0000000 {
compatible = "shared-dma-pool";
reg = <0x0 0xA0000000 0x0 0x1000000>;
status = "okay";
};
#if 0
vsdk_eve_mem: vsdk_eve_mem@A2000000 {
compatible = "shared-dma-pool";
reg = <0x0 0xA5000000 0x0 0x4000000>;
status = "okay";
};
#endif
};
