• State TI Thinks Resolved
  • Locked Locked
  • Replies 2 replies
  • Answers 1 answer
  • Subscribers 99 subscribers
  • Views 360 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AM6548: HyperBUS 100MHz switching characteristics

Marcus Frech
Intellectual 1470 points
Part Number: AM6548

Hi,

I have a question about HyperBus 100 MHz Switching Characteristics.

According to JEDEC the RWDS transition to DQ is  -0.8 ns  minimum

According to datasheet AM6548,  RWDS transition to DQ  is  -0.81 ns  (“tsetup input”  and  “thold input” RWDS to DQ )

Please can you confirm LFD5 =  -0.81ns?

The timing is too tight (10ps will be consumed by interconnection delay like traces, vias, ...).
 

Does AM6548 has an internal delay per pin or of RWDS for HyperBUS to achieve good setup and hold margins on read operations?

Many thanks and best regards

Marcus

  • 0
    TI__Guru**** 393215 points

    Hi,

    Your query has been assigned to a TI engineer. Please note that feedback may be delayed due to holidays in the USA.

  • 0
    TI__Mastermind 30140 points

    Hi Marcus,

    The HyperBus specification from Cypress states that RWDS and Data are edge aligned during Reads - the memory sources both RWDS and Data to the Processor at the same time.

    The signals won't be exactly synchronized, so the memory datasheet provides a tolerance or skew of -0.80ns to +0.80ns between these two signals that are launched at the same time.

    The processor cannot use the RWDS signal to latch the Data signal since they are both launched at the same time (it would need a RWDS strobe that is centered in the data valid window). The actual latch must use an internal signal that is centered between the Data valid window - a delayed version of the RWDS edge.

    The AM6548 datasheet Table 5-56. HyperBus 100 MHz Switching Characteristics includes the requirement LFD5 tskn(rwdsX-dV) from -0.81ns to +0.81ns which is larger than the HyperBus specification of -0.80ns to +0.80ns. This allows for a trace length mismatch of 50mils between these two traces.

    50 mils in a typical FR4 PCB material equates to 9ps (assuming 180ps/inch propagation delay). This is how we arrived at the -0.81ns to +0.81ns requirement (0.009ns rounded up to 0.010ns + 0.80 = 0.81ns)

    The RWDS and all data signals must be trace length matched to within 50mils of each other to comply.

    From https://www.cypress.com/file/213356/download

    Hope this helps,
    Mark