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EVENTQ_3 in ioctl DM365MMAP_IOCMEMCPY

Hi all,

in ioctl DM365MMAP_IOCMEMCPY , present inside Dm365mmap.c

what does EVENTQ_3 means in the davinci_request_dma() call

if i make it to EVENTQ_1 what is the problem.

does it related to the *.cfg file's following setting ?

var EDMA3CHAN = xdc.useModule('ti.sdo.fc.ires.edma3chan.EDMA3CHAN');

  • Sujit,

    EVENTQ_3 has nothing to do with EDMA3CHAN of the cfg file.  In DM36x, there are 4 event queues in the EDMA module. EVENT_Q 0, 1, and 2 are used by codec and the 3rd one is left for system/app for its DMA tranfers. You can see DM36x ARM subsystem guide for details.

    Why do you want to change it to EVENTQ_1 ? Note that eventQ 3 is at the highest priority, and is reccomended to be used for audio. In case you have some general tranfers to be done, you may like to play with different eventQ and see which gives best performance in system. 

     

    regards

    Yashwant

  • thanks yashwant,

    i was checking this for performance .

    also in my another post today i had mentioned about some strange behaivour in chain mode with H264 platinum codec.

    for solving that i was trying this.

    i will go through the ARM Subsystem user guide once.

  • Yashwant,

    in SPRUFI0.pdf , sec 2.10 it has mentioned that EVENQ0 has high priority.

    ------------------------

    There are four event queues (Queue0,Queue1,Queue2 and Queue3) for the device. Events in Queue0

    result in submission of its associated transfer requests (TRs) to TC0. Similarly, transfer requests

    associated with events in Queue1 are submitted to TC1, Queue2 are submitted to TC2 and Queue3 are

    submitted to TC3 .

    An event that wins prioritization against other DMA and/or QDMA pending events is placed at the end of

    the appropriate event queue. Each event queue is serviced in a FIFO (first in–first out) order. Once the

    event reaches the head of its queue and the corresponding transfer controller is ready to receive another

    TR, the event is dequeued and the PaRAM set corresponding to the dequeued event is processed and

    submitted as a transfer request packet (TRP) to the associated EDMA3 transfer controller.

    Queue0 has higher priority than Queue1, if Queue0 and Queue1 both have at least one event entry and if

    both TC0 and TC1 can accept transfer requests, then the event in Queue0 is dequeued first and its

    associated PaRAM set is processed and submitted as a transfer request (TR) to TC0.

    ------------------------

  • In DM36x, event3 has the highest priority. There is QUEPRI register in EDMA which programs this priority. In case of all the Q has the same priority as programmed in QUEPRI, then eventQ0 takes the highest priority followed by 1, 2 and 3.

    regards

    Yashwant