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AM6526: GPMC DMA transfer

Alexander Helbig
Prodigy 20 points
Part Number: AM6526

Hello,

looking at the datasheet section 12.3.4 of the AM6526 it is not clear what type of features the GPMC is supporting:

can you please clarify if a GPMC transfer is possible like supported on AM335x?

Thank you and best regards,

Alex

  • 0
    TI__Mastermind 30140 points

    Hi Alex,

    I believe the DMA mode not supported relates to the Prefetch and Write-Posting Engine. An unsupported feature is for the Prefetch and Write-Posting Engine to automatically trigger a DMA transfer when the FIFO gets low or full.

    There is no GPMC DMA event connection from GPMC to the DMA engine. You must instead use interrupts to service the FIFO in the Prefetch and Write-Posting Engine. GPMC_PREFETCH_CONFIG1[2] DMAMODE must be set to 0.
    Refer to TRM 12.3.4.4.5 GPMC Interrupt Requests.
    Refer also to TRM 12.3.4.4.12.4 Prefetch and Write-Posting Engine

    The Prefetch and Write-Posting Engine only works with NAND flash accesses.

    You may initiate DMA transfers to/from GPMC space with non-NAND accesses. But there are no DMA events coming from GPMC, so the CPU must initiate these DMA transfers and monitor the status of the DMA engine.

    On AM335x  GPMC generates one DMA event, from GPMC (GPMC_DMA_REQ) to the eDMA: e_DMA_53. AM654x does not have this DMA event connected.

    Regards,
    Mark