Hi at all,
i wrote an i2c slave support for i2c-davinci driver in 2.6.32 Kernel. But there is some behaviour of the hardware that is not really good for slave mode "imho".
In user guide "TMS320C674x/OMAP-L1x Processor Inter-Integrated Circuit (I2C) Module" section 2.7 table 1. slave-transmitter mode:
"While a slave, the I2C peripheral does not generate the clock signal, but it can hold I2Cx_SCL low while the
intervention of the processor is required (XSMT = 0 in ICSTR) after data has been transmitted."
This is a real problem in slave mode. I2C peripheral hold SCL definitely low when interrupt AAS or ICXRDY in ICIVR is generatetd and no new data are available (XSMT = 0) . This blocks the whole bus. A init does not work, only a reboot works.This occures also when master want to read more data then slave has to transmit.
The slave does not know when a data request will happen so i tried a NACK when AAS occur but ISR is not fast enough. I am not sure when AAS will be initiated. After I2C pheriperal recognized slave adress our after slave address and r/w-Bit. However time is to short to send a NACK.
Then i figured out to send zero bytes when no data available, but there is a behaviour of hardware i do not understand. After write a byte in ICDXR register this value will be copied to ICXSR shift register. So far so goog, but when i write i new byte to ICDXR while ICXSR does not send the first byte this has no effect even i clear ICXRDY-Bit in MDR register. The peripheral send after geting a read bit from master the first bit which was copied to ICDXR and then the second one. Even after a reset. and this is not good because in transmision before, driver does not when stop condition will occur, so driver copy after every ICXRDY interruppt new send byte to IXCDXR.
I am not quite sure whether i understand something wrong or hardware really worked as discribed or i read over something.
Kindly regards and a happy new year
Hans