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AM5746: Data control in caches

rei
Mastermind 6155 points
Part Number: AM5746

Hi,

My customers are concerned about garbled data in A15 core's L1 and L2 caches.
They hope to detect garbled data, because L1 and L2 caches don't have ECC/parity.

Question 1:
Are there any way to clean L1 instruction cache (like data cache) from user program?

Question 2:
If data cache(instruction cache) is cleaned before dirty, is SDRAM updated with cache data?

Question 3:
Can Core1 L1 cache be handled(clean, invalidate, etc.) by Core0 program? (SMP mode)

AM5746
CCS v8
GCC GNU v6.3.1(Linaro)
SMP mode
pdk_am57xx_1_0_11
bios_6_76_00_08
XDCTools 3.50.3.33

Regards, Rei

  • 0
    TI__Mastermind 29388 points

    Hi Rei,

    The SMP mode Cache API is documented here: <BIOS>/docs/cdoc/index.html, open ti->sysbios->family->arm->a15->smp->Cache.

    Please be aware of the following note: 

    Note: The invalidate instruction is implemented as a clean/invalidate instruction on A15. Therefore, calls to Cache_inv()/Cache_invAll() will behave like Cache_wbInv()/Cache_wbInvAll() on A15.

    Q1: It seems you would use the Cache_wb() API function with the 'type' argument set to "Cache_Type_L1P'

    Q2: I think the cache line should be marked as dirty, or the write back won't occur. I need to investigate further to be sure.

    Q3: I don't see anything in the API functions which indicate this is possible. I need to investigate further to be sure.

    I'll check further on Q2 & Q3 and get back with you.

    Regards,
    Frank

  • 0 in reply to Frank Livingston
    Mastermind 6155 points

    Hi Frank,

    Thank you for your reply. I'm waiting for your update.

    Regards, Rei

  • 0 in reply to rei
    Mastermind 6155 points

    Hi Frank,

    Any updates?

    Regards, Rei

  • 0 in reply to rei
    TI__Mastermind 29388 points

    Rei,

    Not at this time. I suggest you review the BIOS documentation I shared earlier. Other relevant documents from ARM include:

    • DDI0406C_C_arm_architecture_reference_manual.pdf : ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition.,
    • DDI0438I_cortex_a15_r4p0_trm.pdf : ARM Cortex-A15 MPCore Processor, Revision r4p0.
    • DEN0013D_cortex_a_series_PG.pdf : ARM Cortex-A Series, Version 4.0

    These can be downloaded from ARM websites.

    Regards,
    Frank