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AM5728: SPI bit-banged over GPIO

AnotherEmbeddedGuy
Prodigy 160 points

Part Number: AM5728

I have working bit-banged SPI transfers using GPIO pins with the following device tree.

But I need to slow down the "SPI" clock frequency.  Even though device tree has "spi-max-frequency = <100000>;" entries in the device tree, the actual transfer is
taking place at 400000 (400 KHz).  Changing the <100000> to a lower number does not affect the actual observed SPI clock rate coming out of the GPIO pin.

What is the correct way to set the SPI transfer speed in this situation?

&dra7_pmx_core {
    ....
    spi_led_pins: spi_led_pins {
        pinctrl-single,pins = <
            0x2BC (PIN_OUTPUT_PULLUP | MUX_MODE14)  /*MCASP1_AXR2, MOSI, gpio5_4*/
            0x2C0 (PIN_OUTPUT_PULLUP | MUX_MODE14)  /*MCASP1_AXR3, SCLK, gpio5_5*/
            0x2C4 (PIN_OUTPUT_PULLUP | MUX_MODE14)  /*MCASP1_AXR4, CS0,  gpio5_6*/
            0X2C8 (PIN_INPUT_PULLUP  | MUX_MODE14)  /*MCASP1_AXR5, MISO, gpio5_7*/
            0x218 (PIN_OUTPUT_PULLUP | MUX_MODE14)  /*VOUT1_D15, CS1, gpio8_15*/
            0x21C (PIN_OUTPUT_PULLUP | MUX_MODE14)  /*VOUT1_D16, CS2, gpio8_16*/
            0x220 (PIN_OUTPUT_PULLUP | MUX_MODE14)  /*VOUT1_D17, CS3, gpio8_17*/
        >;
    };
};
....
/ {
    spi_led: spi_led@0{
        compatible = "spi-gpio";
        #address-cells = <0x1>;
        #size-cells = <0x0>;
        pinctrl-names = "default";
        pinctrl-0 = <&spi_led_pins>;
        gpio-sck = <&gpio5 5 0>;
        gpio-mosi = <&gpio5 4 0>;
        gpio-miso = <&gpio5 7 0>;
        cs-gpios = <&gpio5 6 0 &gpio8 15 0 &gpio8 16 0 &gpio8 17 0>;
        num-chipselects = <4>;
        spidevled@0 {
            compatible = "linux,spidev";
            spi-max-frequency = <100000>;
            reg = <0>;
            status = "okay";
        };
        spidevled@1 {
            compatible = "linux,spidev";
            spi-max-frequency = <100000>;
            reg = <1>;
            status = "okay";
        };
        spidevled@2 {
            compatible = "linux,spidev";
            spi-max-frequency = <100000>;
            reg = <2>;
            status = "okay";
        };
        spidevled@3 {
            compatible = "linux,spidev";
            spi-max-frequency = <100000>;
            reg = <3>;
            status = "okay";
        };        
    };
}

  • 0
    TI__Guru**** 170625 points

    Hello,

    spi-max-frequency entry impact McSPI module clock pin frequency, spix_sclk.  You can monitor how this entry (with different values) impact McSPI register MCSPI_CHxCONF[5:2] CLKD, thus McSPI clock pin. For more info, refer to AM572x TRM, ch 24.4 McSPI

    If you need to slow down McSPI module (not only McSPI clock pin), you need to reduce McSPI module functional clock, PER_48M_GFCLK.

    Regards,
    Pavel

  • 0 in reply to Pavel Botev
    Prodigy 160 points

    This question was regarding SPI over GPIO (using bit-bang SPI driver, compatible = "spi-gpio";).   I am not using McSPI module in this case.

    My original question still remains - how to set SPI clock rate when it is implemented using bit-banged GPIO.

    SPI transfers are happening as expected.  I just need to slow down the SPI clock.

  • 0 in reply to AnotherEmbeddedGuy
    TI__Guru**** 170625 points

    AnotherEmbeddedGuy said:

    My original question still remains - how to set SPI clock rate when it is implemented using bit-banged GPIO.

    SPI transfers are happening as expected.  I just need to slow down the SPI clock.

    If you need to slow down McSPI module, you need to reduce McSPI module functional clock, PER_48M_GFCLK.

    If you need to slow down GPIO5 module, you need to reduce GPIO5 module clock, GPIO5_ICLK.


    For more info, refer to:

    AM572x DM, Table 5-9. Maximum Supported Frequency

    AM572x TRM, 3.6.3.2.1 CM_CORE_AON Clock Generator and  27.4.3 General-Purpose Interface Clock Configuration

    Regards,
    Pavel

  • 0 in reply to Pavel Botev
    Prodigy 160 points

    Since the CLOCK in this case is generated on a GPIO pin by the bit-bang software driver, isn't there way to set the clock rate by

    passing a parameter into the driver invocation or by making an IOCTL call ?

  • 0 in reply to AnotherEmbeddedGuy
    TI__Guru**** 170625 points

    AnotherEmbeddedGuy said:

    Since the CLOCK in this case is generated on a GPIO pin by the bit-bang software driver, isn't there way to set the clock rate by

    passing a parameter into the driver invocation or by making an IOCTL call ?

    I can not find such option in "spi-gpio" driver and DTS.

    For a precise visual representation how to alter any clock configuration within the device, you can explore the CTT tool:

    http://www.ti.com/tool/CLOCKTREETOOL

    Check also if clock framework will be in help:

    http://processors.wiki.ti.com/index.php/Clock_Framework_User_Guide

    linux-kernel/drivers/clk/ti/clk-7xx.c

    linux-kernel/arch/arm/boot/dts/dra7xx-clocks.dtsi

    linux-kernel/arch/arm/mach-omap2/omap_hwmod_7xx_data.c

    Regards,
    Pavel