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TMS320C6748: Advisory 2.3.18 's work around (a)

rei
Mastermind 6155 points
Part Number: TMS320C6748

Hi,

A power failure occurred in a customer's product using TMS320C6748.

Upon reviewing the symptoms, it was very similar to Advisory 2.3.18 of TMS320C6748 errata.

They want to try the workaround.
There were some questions about workarounds.

It is understood that Workaround (a) suppresses the amount of current to 140 mA or less with a capacitor. We can't understand this.

Capacitors charge and discharge, and they think the problem cannot be solved by the OFF time, but why is adjustment with capacitors?

*********Work around (a)*********
Maintain sufficient bulk capacitance on the DVDD18 supply such that the charging current for these capacitors provides all or part of the required >140 mA. Bulk capacitance in this context means the total capacitance seen by the DVDD18 supply (filter capacitors, bypass capacitors, etc.). Capacitor charging current is defined as I = C*(dV/dt).
So the ramp rate of the DVDD3318_x supply and the total bulk capacitance on the DVDD18 supply can be used to calculate the current produced.
This solution provides additional power supply filtering and little current leakage after the supplies are ramped (depending on the type of capacitors used). The table below shows some examples of the bulk capacitance that would be required to use this solution alone:
*********Work around (a)*********

Question 1:
Please let me know a little more.

Question 2:
If State is error state (Error state of the IO buffer during Zone G)
How does C6748 behave?
Will it break? Does it not work according to the characteristics of DS?

Regards, Rei

  • 0
    TI__Mastermind 30120 points

    Hi Rei,

    Advisory 2.3.18 affects Silicon Revisions 2.3 and earlier. DEVICE REVISION CODE E (SILICON REVISION 2.3) is the latest revision, so this advisory applies to all silicon revisions.

    Regarding Question 1:
    The idea behind Work around (a) is that a fully discharged capacitor draws current (I=C*(dV/dt)) when the 1.8V is applied - this current charges the capacitor(s). The current draw needs to exceed 140uA during zone G to prevent the dual-voltage IO buffers voltage detection circuitry from entering the undesired state where current flows between the 3.3V Mode Logic and the 1.8V Mode Logic.

    Since the timings of the voltage ramps differ across designs, Table 12. Bulk Capacitance lists various calculations of capacitance that should prevent the phenomenon for each ramp time.

    If the capacitors are not fully discharged when the power is (re)applied, I imagine similar calculations for a partially discharged capacitor are required to ensure it draws 140uA during zone G to prevent the phenomenon.

    I personally prefer workaround 1.(c) a resistor to GND that can be disabled after Zone G or workaround 2 - using a buck converter with external inductance to pulldown the regulated voltage when necessary.

    Regarding Question 2:
    I am not certain of the impact, but I will ask internally.
    I imagine a leakage path inside the logic could shorten the lifetime of the device from the datasheet Power on Hours. If the 3.3V mode logic is enabled for a 1.8V rail, a logic high and low may differ from the datasheet recommended operating conditions.
    I will ask for more details and hope to get back to you by next week.

    Regards,
    Mark

  • 0 in reply to Mark M
    TI__Guru* 83955 points

    Rei

    Mark asked for some additional guidance on #2 - based on past experience with customers encountering this issue where w/o the workaround the 1.8V gets lifted to 2.7V instead, we have seen devices failing to function within 2-3 days and there is damage where these units will not function.

    It is important that you chose one of the recommended workarounds.

    There are no additional details beyond what we publish in the errata.

    Hope this helps. 

    Regards

    Mukul 

  • 0 in reply to Mukul Bhatnagar
    Mastermind 6155 points

    Hi Mark, Mukul,

    Thank you for your reply.
    Customers have next questions.

    Question 3:
    Would you explain the mechanism of this phenomenon to us using the switching circuit inside the device?

    Question 4:
    Are there any way to take measures without turning off the power when this 2.7V pull-up state is reached?

    My apologies for asking so much of you.

    Regards, Rei

  • 0 in reply to rei
    TI__Guru* 83955 points

    Hi Rei

    On Q3 , unfortunately we will not be able to support or share any information beyond what is in the errata. This is an old device with several 100's of customers in production and most of them have worked through this errata with the information publically provided in the errata. Please ask your customer to work with the information available. 

    On Q4 I don't quite understand the query , but if you do get in state where 1.8V is at 2.7V due to lack of workaround implementation, there is no way to remove that condition without turning off the power etc. 

  • 0 in reply to Mukul Bhatnagar
    Mastermind 6155 points

    Hi Mukul,

    Thank you for your reply. I confirmed Revision History.

    "Advisory 2.0.18" was added during SPRZ303B to SPRZ303C.

    Would you check the date of update to “SPRZ303C”?

    Regards, Rei

  • 0 in reply to rei
    TI__Guru* 83955 points

    Internal archive mention a creation date of Dec 2010 for SPRZ303C. 

    Regards

    Mukul 

  • 0 in reply to Mukul Bhatnagar
    Mastermind 6155 points

    Hi Mukul,

    Thank you for your prompt reply. I will talk to customers.

    Regards, Rei

  • 0 in reply to rei
    Mastermind 6155 points

    Hi,

    I'm sorry to bother you again. I gave this information to customers. And they tried Workaround(a).

    DVDD3318_x ramp times is 400µs, so customers added 22µF capacitance. However, this power failure occurred. Next, adding 40µF solved this issue.

    Is there a case where capacitance higher than theoretical value is required?

    It would be very helpful if you have detail data.

    Regards, Rei

  • 0 in reply to rei
    TI__Guru* 83955 points

    Rei-san

    As previously explained there is no additional detailed data beyond what is published in the errata.

    This is almost a 10+ yr old errata and several customers have used the errata to workaround the issue.  From experience I have seen that the option b/c are more reliable than cap loading. I am not sure what maybe causing the 40 uF to work but not 22 uF - they should consider adding more boards and make sure they have the ramp time understood as well ensure that the bulk cap is sufficient to generate the 140 mA load during power up. 

    You will see several older posts in general 

    https://e2e.ti.com/support/processors/f/791/p/429351/1544431

    Customer should be able to use the guidance in the errata to pick the right solution for them. 

    Hope this helps.

    Regards

    Mukul