Part Number: 66AK2H06
Tool/software: Code Composer Studio
Hi,
My customer using 66AK2H06 reported an error with CCS while they are debugging C66x codes on EVMK2H.
(all file extension are changed to *.txt)
Please see below CCS console log.
When target is connected, GEL file runs correctly and finish at line#47.
Then customer tried to load program, and Error -1176 were generated.
It seems the code are load at address 0x0 where is not memory mapped.
C66xx_0: GEL Output: Connecting Target... C66xx_0: GEL Output: TCI6638K2K GEL file Ver is 1.70000005 C66xx_0: GEL Output: Detected PLL bypass enabled: SECCTL[BYPASS] = 0x00800000 C66xx_0: GEL Output: (2a) MAINPLLCTL1 = 0x00000040 C66xx_0: GEL Output: (2b) PLLCTL = 0x00000048 C66xx_0: GEL Output: (2c) PLLCTL = 0x00000048 C66xx_0: GEL Output: (2d) Delay... C66xx_0: GEL Output: (2e) SECCTL = 0x00810000 C66xx_0: GEL Output: (2f) PLLCTL = 0x0000004A C66xx_0: GEL Output: (2g) Delay... C66xx_0: GEL Output: (2h) PLLCTL = 0x00000048 C66xx_0: GEL Output: (4)PLLM[PLLM] = 0x0000000F C66xx_0: GEL Output: MAINPLLCTL0 = 0x05000000 C66xx_0: GEL Output: (5) MAINPLLCTL0 = 0x07000000 C66xx_0: GEL Output: (5) MAINPLLCTL1 = 0x00000040 C66xx_0: GEL Output: (6) MAINPLLCTL0 = 0x07000000 C66xx_0: GEL Output: (7) SECCTL = 0x00890000 C66xx_0: GEL Output: (8a) Delay... C66xx_0: GEL Output: PLL1_DIV3 = 0x00008002 C66xx_0: GEL Output: PLL1_DIV4 = 0x00008004 C66xx_0: GEL Output: PLL1_DIV7 = 0x00000000 C66xx_0: GEL Output: (8d/e) Delay... C66xx_0: GEL Output: (10) Delay... C66xx_0: GEL Output: (12) Delay... C66xx_0: GEL Output: (13) SECCTL = 0x00090000 C66xx_0: GEL Output: (Delay... C66xx_0: GEL Output: (Delay... C66xx_0: GEL Output: (14) PLLCTL = 0x00000041 C66xx_0: GEL Output: PLL has been configured (CLKIN * PLLM / PLLD / PLLOD = PLLOUT): C66xx_0: GEL Output: PLL has been configured (122.879997 MHz * 16 / 1 / 2 = 983.039978 MHz) C66xx_0: GEL Output: DISABLESTAT ---> 0x000007FF C66xx_0: GEL Output: Power on all PSC modules and DSP domains... C66xx_0: GEL Output: Power on all PSC modules and DSP domains... Done. C66xx_0: GEL Output: WARNING: SYSCLK is the input to the PA PLL. C66xx_0: GEL Output: Completed PA PLL Setup C66xx_0: GEL Output: PAPLLCTL0 - before: 0x0x098804C0 after: 0x0x09080500 C66xx_0: GEL Output: PAPLLCTL1 - before: 0x0x00000040 after: 0x0x00002040 C66xx_0: GEL Output: DDR begin C66xx_0: GEL Output: XMC setup complete. C66xx_0: GEL Output: DDR3 PLL (PLL2) Setup ... C66xx_0: GEL Output: DDR3 PLL Setup complete, DDR3A clock now running at 666 MHz. C66xx_0: GEL Output: DDR3A initialization complete C66xx_0: GEL Output: DDR3 PLL Setup ... C66xx_0: GEL Output: DDR3 PLL Setup complete, DDR3B clock now running at 800MHz. C66xx_0: GEL Output: DDR3B initialization complete C66xx_0: GEL Output: DDR done C66xx_0: Trouble Writing Register PC: (Error -1176 @ 0x0) Unable to access device memory. Verify that the memory address is in valid memory. If error persists, confirm configuration, power-cycle board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 8.0.903.2) C66xx_0: Symbol Manager: the object file contains multiple sets of debug information; only the first set will be used. C66xx_0: Trouble Setting Breakpoint with the Action "Terminate Program Execution" at 0x86800: (Error -1176 @ 0x8681C) Unable to access device memory. Verify that the memory address is in valid memory. If error persists, confirm configuration, power-cycle board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 8.0.903.2) C66xx_0: Breakpoint Manager: Retrying with a AET breakpoint C66xx_0: Trouble Setting Breakpoint with the Action "Finish Auto Run" at 0x85bc0: (Error -1176 @ 0x85BDC) Unable to access device memory. Verify that the memory address is in valid memory. If error persists, confirm configuration, power-cycle board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 8.0.903.2) C66xx_0: Breakpoint Manager: Retrying with a AET breakpoint
Customer checked *.map files (see below) and found;
- According to SECTION ALLOCATION MAP, nothing is mapped at 0x0, 0x8681C or 0x85BDC.
- GLOBAL SYMBOLS(line#3181) shows many symbols are mapped at 0x0 or other region outside of MEMORY CONFIGURATION.
memory map.txt
The linker command file used by customer is below.
/****************************************************************************/
/* 66AK2Gxx_C66.cmd */
/* Copyright (c) 2016 Texas Instruments Incorporated */
/* Author: Rafael de Souza */
/* */
/* Description: This file is a sample linker command file that can be */
/* used for linking programs built with the C compiler and */
/* running the resulting .out file on the C66x DSP core of */
/* a 66AK2Gxx device. */
/* Use it as a guideline. You will want to */
/* change the memory layout to match your specific */
/* target system. You may want to change the allocation */
/* scheme according to the size of your program. */
/* */
/****************************************************************************/
-c
-stack 0x4000
MEMORY
{
/* ---- DSP 0: 0x0C200000 - 0x0C3FFFFF (2MB) ---- */
L2_SRAM_0 : o = 0x00800000 l = 0x00080000 /* 512kB internal SRAM */
L2_SRAM_1 : o = 0x00880000 l = 0x00080000 /* 512kB internal SRAM */
/* MSMC_SRAM : o = 0x0C000000 l = 0x00100000 /* 1MB MSMC Shared SRAM */
MSMC_SRAM_A : o = 0x0C200000 l = 0x00001000
MSMC_SRAM_B : o = 0x0C201000 l = 0x001FF000
/* DDR0 : o = 0x80000000 l = 0x80000000 /* 2GB external DDR0 */
DDR_C : origin = 0x80f00000, length = 0x100000
}
SECTIONS
{
.root : {} > MSMC_SRAM_A
GROUP: > MSMC_SRAM_B
{
.info
.vectors
.cinit
.const
.switch
.text
.romend
.stack
.firm
.far
.fardata
.bss
.neardata
.cio
.data
.sysmem
.args
.ppinfo
.ppdata
.pinit
.binit
.init_array
.rodata
.c6xabi.exidx
.c6xabi.extab
.objects
.heap
}
.noncache > DDR_C
}
What is the root cause of the errors?
Thanks and regards,
Koichiro Tashiro
