Hi Sitara support Team,
I would like to make sure about the EEPROM PDI Access State register.
-ET1100 Datasheet shows
bit0: Access to EEPROM: 0: PDI releases EEPROM access 1: PDI takes EEPROM access (PDI has EEPROM control) r/- r/(w) 0 7:1 Reserved, write 0 r
-PRU_ICSS_EtherCAT_Slave_Controller_Register_List Wiki site shows
bit0 Access to EEPROM: 0: PDI takes EEPROM access 1: PDI releases EEPROM access (PDI has EEPROM control) r/- r/(w) 0 7:1 Reserved, write 0 r
processors.wiki.ti.com/.../PRU_ICSS_EtherCAT_Slave_Controller_Register_List
Could I ignore the Wiki site because of the old date without maintenance?
Is this TI Wiki information just typo, right?
Best regards,
Kanae
