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TCI6638K2K: TCI6638K2K SRIO issue

Part Number: TCI6638K2K

Dear colleague,

Our customer encounters below issue:

Could you please give us some explain?

  1. When FPGA just send NREAD, DSP response time is fixed. But when FPGA sends NREAD and SWRITE, DSP response time will not be fixed, sometimes response is too long.
  2. Are there any effects between the 4 X1 SRIO? There are 2 x1 channels that must send SWRITE.
  3. Whether we have register in TCI6638 that could record receive NREAD and send NREAD action? Because now DSP response time is not fixed, customer wants to use this register to calculate the time from receiving a packet to sending a packet.
  4. When FPGA has a number of requests, DSP doesn’t return the data in the order of request. Such as DSP send the 2nd request data when the data for the 1st  request is not yet complete. How to avoid and why it will happen?

Thanks a lot!

Best Regards,

Rock Su

  • Hi,

    Do you use Processor SDK RTOS or are you using bare metal code to program the SRIO communication?

    Best Regards,
    Yordan

  • Hi,

    Customers use C program language.

    SRIO interface initialization code is reference code in TI.com:

    C:\ti\pdk_keystone2_3_00_03_15\packages\ti\drv\srio\device\k2k\src\device_srio_loopback.c     SrioDevice_init()

    Customer don't change the code.

    After initialization, FPGA send the read/write request. 

    Thanks!

    Best Regards,

    Rock Su

  • Rock,

    Thanks for the info! We have little SRIO expertise left here. NREAD needs a response and SWRITE doesn't. What is the SRIO topology here? You have a K2K connected to 4 different devices each of one port? And 2 are doing the SWRITE, and another 2 are doing NREAD? Or the NREAD and SWRITE on the same FPGA device?

    For SRIO user guide:  2.3.3 Message Passing

    Out-of-order responses are allowed

    Due to the nature of SRIO RETRY and out of order reception of message segments, the
    requirement is that a type 11 message must use only one descriptor/buffer. Behavior of
    the RXU is undefined if this is not the case. The SRIO only support Host Packet
    descriptor types.

    Regards, Eric

  • Hi,

    Here are the suggestions from our SRIO expert:

    -        If they want ordered transactions and better determinism, they need to think about the packets priorities and the LSUs that they are using.  There is a section in the user’s guide that talks about this, but from memory, they need to use the same LSU and same priority to guarantee in order delivery.

    -        This is a packet based system, not TDM, so timing will change depending on loading with packets and number of ports used, etc.

    -        If they want to force the NREADs first, make them higher priority than the NWRITEs.

    -        They may also adjust the NREAD and/or SWRITE payload size per LSU write to see different results if latency is a concern.  They will have to play with it though.

    they could play with the LSU shadow registers too.

    Regards, Eric

  • Hi Eric,

    The customer said they have tried your solution, the effect improved, but not significantly.

    And at the same time, they also have some questions about your reply:

    1. LSU: Does FPGA or DSP send LSU?

    2. How to configure LSU shadow? 

    At the same time, the customer wants to have a call with you...what do you think?

    Best Regards,

    Rock Su

  • Hi,

    I thought in your case, the FPGA sends LSU. For configure shadow LSU, please see an application note: 

    and some discussion:

    https://e2e.ti.com/support/processors/f/791/t/331629

    Regards, Eric