Dear colleague,
Our customer encounters below issue:
Could you please give us some explain?
- When FPGA just send NREAD, DSP response time is fixed. But when FPGA sends NREAD and SWRITE, DSP response time will not be fixed, sometimes response is too long.
- Are there any effects between the 4 X1 SRIO? There are 2 x1 channels that must send SWRITE.
- Whether we have register in TCI6638 that could record receive NREAD and send NREAD action? Because now DSP response time is not fixed, customer wants to use this register to calculate the time from receiving a packet to sending a packet.
- When FPGA has a number of requests, DSP doesn’t return the data in the order of request. Such as DSP send the 2nd request data when the data for the 1st request is not yet complete. How to avoid and why it will happen?
Thanks a lot!
Best Regards,
Rock Su